diff --git a/lib/CPUs/MIPS/src/async_defs.vhd b/lib/CPUs/MIPS/src/async_defs.vhd
index e704e8c..63c9045 100644
--- a/lib/CPUs/MIPS/src/async_defs.vhd
+++ b/lib/CPUs/MIPS/src/async_defs.vhd
@@ -40,6 +40,7 @@ package async_defs is
 		pol_cs					=> '0',
 		pol_oe					=> '0',
 		pol_we					=> '0',
+		pol_be					=> '0',
 		pol_rst					=> '0'
 	);
 
@@ -54,6 +55,7 @@ package async_defs is
 		pol_cs					=> '0',
 		pol_oe					=> '0',
 		pol_we					=> '0',
+		pol_be					=> '0',
 		pol_rst					=> '0'
 	);
 
diff --git a/lib/misc/async_port_wb.vhd b/lib/misc/async_port_wb.vhd
index efc8e75..ab572d2 100644
--- a/lib/misc/async_port_wb.vhd
+++ b/lib/misc/async_port_wb.vhd
@@ -1,5 +1,5 @@
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.4 2009-01-18 21:44:57 Jens Exp $
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.5 2009-02-08 17:34:18 Jens Exp $
 -----------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
@@ -32,8 +32,9 @@ entity async_port_wb is
 		async_a		: out unsigned(addr_width-1 downto 0);
 		async_d		: inout unsigned(data_width-1 downto 0);
 		async_cs	: out std_logic;
-		async_wr	: out unsigned(byte_sel_width-1 downto 0);
+		async_wr	: out std_logic;
 		async_rd	: out std_logic;
+		async_be	: out unsigned(byte_sel_width-1 downto 0);
 		async_rst	: out std_logic
 	);
 end async_port_wb;
@@ -209,7 +210,8 @@ architecture Behavioral of async_port_wb is
 	begin
 		if rising_edge(CLK_I) then
 			async_cs	<= (not async_timespec.pol_cs) xor as.cs;
-			async_wr	<= ((byte_sel_width-1 downto 0 => as.wr) and byte_en) xor (byte_sel_width-1 downto 0 => not async_timespec.pol_we);
+			async_be	<= (byte_sel_width-1 downto 0 => not async_timespec.pol_be) xor ((byte_sel_width-1 downto 0 => as.cs) and byte_en);
+			async_wr	<= (not async_timespec.pol_we) xor as.wr;
 			async_rd	<= (not async_timespec.pol_oe) xor as.rd;
 			async_rst	<= (not async_timespec.pol_rst) xor as.rst;
 		end if;
diff --git a/lib/misc/async_types.vhd b/lib/misc/async_types.vhd
index af6eb9a..cdca24d 100644
--- a/lib/misc/async_types.vhd
+++ b/lib/misc/async_types.vhd
@@ -37,6 +37,7 @@ package async_types is
 		pol_cs			: std_logic;
 		pol_oe			: std_logic;
 		pol_we			: std_logic;
+		pol_be			: std_logic;
 		pol_rst			: std_logic;
 	end record;