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git-svn-id: http://moon:8086/svn/vhdl/trunk@1566 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-29 08:39:50 +00:00
parent 736cf3464d
commit 51899a014d
2 changed files with 160 additions and 141 deletions
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projects/vga_ctrl/src/tb_vga_ctrl.vhd
+31 -16
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@@ -32,23 +32,26 @@ use IEEE.NUMERIC_STD.ALL;
use work.vga_types.all;
ENTITY tb_vga_ctrl_vhd IS
END tb_vga_ctrl_vhd;
ENTITY tb_vga_ctrl IS
END tb_vga_ctrl;
ARCHITECTURE behavior OF tb_vga_ctrl_vhd IS
ARCHITECTURE behavior OF tb_vga_ctrl IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT vga_ctrl_top
GENERIC
(
sys_freq : real;
fifo_depth : integer;
tsvga : vga_timespec_t
);
PORT
(
sys_rstn_in : IN std_logic;
sys_clk_in : IN std_logic;
sys_rst_in : IN std_logic;
sys_clk_in : IN std_logic;
-- VGA signals
sys_vga_clk_out : OUT std_logic;
sys_vga_clk_in : IN std_logic;
sys_vga_clk_ce : IN std_logic;
sys_vga_red : OUT unsigned(7 downto 0);
sys_vga_green : OUT unsigned(7 downto 0);
sys_vga_blue : OUT unsigned(7 downto 0);
@@ -56,7 +59,8 @@ ARCHITECTURE behavior OF tb_vga_ctrl_vhd IS
sys_vga_sync_n : OUT std_logic;
sys_vga_hsync : OUT std_logic;
sys_vga_vsync : OUT std_logic;
sys_vga_clk : OUT std_logic;
-- Buttons and LEDs
sys_dip : in unsigned(7 downto 0);
sys_btn : in unsigned(4 downto 0);
sys_led : out unsigned(8 downto 0)
@@ -67,13 +71,16 @@ ARCHITECTURE behavior OF tb_vga_ctrl_vhd IS
constant PERIOD : time := 9.9304865938430983118172790466733 ns;
--Inputs
SIGNAL sys_rstn_in : std_logic := '0';
SIGNAL sys_rst_in : std_logic := '1';
SIGNAL sys_clk_in : std_logic := '0';
SIGNAL sys_color_en : unsigned(2 downto 0) := (others => '0');
SIGNAL sys_dip : unsigned(7 downto 0) := (others => '0');
SIGNAL sys_btn : unsigned(4 downto 0) := (others => '0');
--Outputs
SIGNAL sys_vga_clk_ce : std_logic := '1';
SIGNAL sys_vga_clk_in : std_logic := '0';
SIGNAL sys_vga_clk_out : std_logic;
SIGNAL sys_vga_red : unsigned(7 downto 0);
SIGNAL sys_vga_green : unsigned(7 downto 0);
SIGNAL sys_vga_blue : unsigned(7 downto 0);
@@ -81,7 +88,6 @@ ARCHITECTURE behavior OF tb_vga_ctrl_vhd IS
SIGNAL sys_vga_sync_n : std_logic;
SIGNAL sys_vga_hsync : std_logic;
SIGNAL sys_vga_vsync : std_logic;
SIGNAL sys_vga_clk : std_logic;
SIGNAL sys_led : unsigned(8 downto 0);
constant f_sys : real := 100.0;
constant f_vga : real := 130.0;
@@ -94,13 +100,16 @@ BEGIN
uut: vga_ctrl_top
GENERIC MAP
(
sys_freq => f_sys,
fifo_depth => 2048,
tsvga => ts_vga_testbench
)
PORT MAP(
sys_rstn_in => sys_rstn_in,
PORT MAP
(
sys_rst_in => sys_rst_in,
sys_clk_in => sys_clk_in,
sys_vga_clk_in => sys_vga_clk_in,
sys_vga_clk_out => sys_vga_clk_out,
sys_vga_clk_ce => sys_vga_clk_ce,
sys_vga_red => sys_vga_red,
sys_vga_green => sys_vga_green,
sys_vga_blue => sys_vga_blue,
@@ -108,7 +117,7 @@ BEGIN
sys_vga_sync_n => sys_vga_sync_n,
sys_vga_hsync => sys_vga_hsync,
sys_vga_vsync => sys_vga_vsync,
sys_vga_clk => sys_vga_clk,
sys_dip => sys_dip,
sys_btn => sys_btn,
sys_led => sys_led
@@ -120,12 +129,18 @@ BEGIN
wait for PERIOD/2;
END PROCESS;
vga_clk : PROCESS
BEGIN
sys_vga_clk_in <= not sys_vga_clk_in;
wait for PERIOD/2;
END PROCESS;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 20*PERIOD;
sys_rstn_in <= '1';
sys_rst_in <= '0';
wait for PERIOD;
sys_dip <= X"AA";