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git-svn-id: http://moon:8086/svn/vhdl/trunk@1566 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-29 08:39:50 +00:00
parent 736cf3464d
commit 51899a014d
2 changed files with 160 additions and 141 deletions
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projects/vga_ctrl/src/tb_vga_ctrl.vhd
+31 -16
View File
@@ -32,23 +32,26 @@ use IEEE.NUMERIC_STD.ALL;
use work.vga_types.all;
ENTITY tb_vga_ctrl_vhd IS
END tb_vga_ctrl_vhd;
ENTITY tb_vga_ctrl IS
END tb_vga_ctrl;
ARCHITECTURE behavior OF tb_vga_ctrl_vhd IS
ARCHITECTURE behavior OF tb_vga_ctrl IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT vga_ctrl_top
GENERIC
(
sys_freq : real;
fifo_depth : integer;
tsvga : vga_timespec_t
);
PORT
(
sys_rstn_in : IN std_logic;
sys_clk_in : IN std_logic;
sys_rst_in : IN std_logic;
sys_clk_in : IN std_logic;
-- VGA signals
sys_vga_clk_out : OUT std_logic;
sys_vga_clk_in : IN std_logic;
sys_vga_clk_ce : IN std_logic;
sys_vga_red : OUT unsigned(7 downto 0);
sys_vga_green : OUT unsigned(7 downto 0);
sys_vga_blue : OUT unsigned(7 downto 0);
@@ -56,7 +59,8 @@ ARCHITECTURE behavior OF tb_vga_ctrl_vhd IS
sys_vga_sync_n : OUT std_logic;
sys_vga_hsync : OUT std_logic;
sys_vga_vsync : OUT std_logic;
sys_vga_clk : OUT std_logic;
-- Buttons and LEDs
sys_dip : in unsigned(7 downto 0);
sys_btn : in unsigned(4 downto 0);
sys_led : out unsigned(8 downto 0)
@@ -67,13 +71,16 @@ ARCHITECTURE behavior OF tb_vga_ctrl_vhd IS
constant PERIOD : time := 9.9304865938430983118172790466733 ns;
--Inputs
SIGNAL sys_rstn_in : std_logic := '0';
SIGNAL sys_rst_in : std_logic := '1';
SIGNAL sys_clk_in : std_logic := '0';
SIGNAL sys_color_en : unsigned(2 downto 0) := (others => '0');
SIGNAL sys_dip : unsigned(7 downto 0) := (others => '0');
SIGNAL sys_btn : unsigned(4 downto 0) := (others => '0');
--Outputs
SIGNAL sys_vga_clk_ce : std_logic := '1';
SIGNAL sys_vga_clk_in : std_logic := '0';
SIGNAL sys_vga_clk_out : std_logic;
SIGNAL sys_vga_red : unsigned(7 downto 0);
SIGNAL sys_vga_green : unsigned(7 downto 0);
SIGNAL sys_vga_blue : unsigned(7 downto 0);
@@ -81,7 +88,6 @@ ARCHITECTURE behavior OF tb_vga_ctrl_vhd IS
SIGNAL sys_vga_sync_n : std_logic;
SIGNAL sys_vga_hsync : std_logic;
SIGNAL sys_vga_vsync : std_logic;
SIGNAL sys_vga_clk : std_logic;
SIGNAL sys_led : unsigned(8 downto 0);
constant f_sys : real := 100.0;
constant f_vga : real := 130.0;
@@ -94,13 +100,16 @@ BEGIN
uut: vga_ctrl_top
GENERIC MAP
(
sys_freq => f_sys,
fifo_depth => 2048,
tsvga => ts_vga_testbench
)
PORT MAP(
sys_rstn_in => sys_rstn_in,
PORT MAP
(
sys_rst_in => sys_rst_in,
sys_clk_in => sys_clk_in,
sys_vga_clk_in => sys_vga_clk_in,
sys_vga_clk_out => sys_vga_clk_out,
sys_vga_clk_ce => sys_vga_clk_ce,
sys_vga_red => sys_vga_red,
sys_vga_green => sys_vga_green,
sys_vga_blue => sys_vga_blue,
@@ -108,7 +117,7 @@ BEGIN
sys_vga_sync_n => sys_vga_sync_n,
sys_vga_hsync => sys_vga_hsync,
sys_vga_vsync => sys_vga_vsync,
sys_vga_clk => sys_vga_clk,
sys_dip => sys_dip,
sys_btn => sys_btn,
sys_led => sys_led
@@ -120,12 +129,18 @@ BEGIN
wait for PERIOD/2;
END PROCESS;
vga_clk : PROCESS
BEGIN
sys_vga_clk_in <= not sys_vga_clk_in;
wait for PERIOD/2;
END PROCESS;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 20*PERIOD;
sys_rstn_in <= '1';
sys_rst_in <= '0';
wait for PERIOD;
sys_dip <= X"AA";
projects/vga_ctrl/src/vga_ctrl_top.vhd
+129 -125
View File
@@ -27,14 +27,17 @@ use work.cpu_pkg.all;
entity vga_ctrl_top is
Generic
(
sys_freq : real := 100.0;
fifo_depth : integer := 2048;
tsvga : vga_timespec_t := ts_vga_1280_1024_72
);
Port
(
sys_rstn_in : in std_logic;
sys_rst_in : in std_logic;
sys_clk_in : in std_logic;
-- VGA signals
sys_vga_clk_in : in std_logic;
sys_vga_clk_out : out std_logic;
sys_vga_clk_ce : in std_logic;
sys_vga_red : out unsigned(7 downto 0);
sys_vga_green : out unsigned(7 downto 0);
sys_vga_blue : out unsigned(7 downto 0);
@@ -42,7 +45,7 @@ entity vga_ctrl_top is
sys_vga_sync_n : out std_logic;
sys_vga_hsync : out std_logic;
sys_vga_vsync : out std_logic;
sys_vga_clk : out std_logic;
-- Buttons and LEDs
sys_btn : in unsigned(4 downto 0);
sys_dip : in unsigned(7 downto 0);
@@ -55,36 +58,53 @@ architecture Behavioral of vga_ctrl_top is
-- System signal
signal rst : std_logic;
signal clk : std_logic;
signal vga_rst : std_logic;
signal vga_clk : std_logic;
signal vga_ready : std_logic;
-- Timing
signal scan_rdy : std_logic;
signal scan_rdy_h : std_logic;
signal scan_rdy_v : std_logic;
signal vga_scan_x : std_logic;
signal vga_scan_y : std_logic;
signal hsync : std_logic;
signal vsync : std_logic;
signal src_pos_x : natural range 0 to tsvga.ts_h.ncyc_scan-1;
signal src_pos_x : natural range 0 to tsvga.ts_h.ncyc_scan-1;
signal src_pos_y : natural range 0 to tsvga.ts_v.ncyc_scan-1;
signal vga_pos_x : natural range 0 to tsvga.ts_h.ncyc_scan-1;
signal vga_pos_y : natural range 0 to tsvga.ts_v.ncyc_scan-1;
-- Line buffers
signal color_w : color_t;
signal vga_color : color_t;
signal color_we : std_logic;
signal fifo_full : std_logic;
signal fifo_almost_full : std_logic;
signal scan_enable : std_logic;
signal src_enable : std_logic;
signal src_cnt_en : std_logic;
signal char_draw_en : std_logic;
signal cg_en : std_logic;
signal cpu_color : color_t;
-- Backend signals
signal scan_rdy : std_logic;
signal ctrl_scan_en : std_logic;
signal color_in : color_array_t;
signal color_op : color_op_t;
signal color_en : unsigned (VGA_NUM_CH-1 downto 0);
signal stat_vga_rdy : std_logic;
signal stat_hready : std_logic;
signal stat_vready : std_logic;
signal stat_scan : std_logic;
signal stat_hscan : std_logic;
signal stat_vscan : std_logic;
signal stat_hsync : std_logic;
signal stat_vsync : std_logic;
signal stat_hpos : natural range 0 to tsvga.ts_h.ncyc_scan-1;
signal stat_vpos : natural range 0 to tsvga.ts_v.ncyc_scan-1;
-- CG signals
signal cg_en : std_logic;
signal cg_rdy : std_logic;
signal cg_draw : std_logic;
signal cg_clr_screen : std_logic;
signal cg_clr_line : std_logic;
signal cg_din : unsigned(7 downto 0);
signal cg_dout : unsigned(7 downto 0);
signal cg_ascii_we : std_logic;
signal cg_posy_we : std_logic;
signal cg_posx_we : std_logic;
signal cg_color : color_t;
signal cg_csr_pos_x : natural range 0 to 80-1;
signal cg_csr_pos_y : natural range 0 to 32-1;
signal vga_scan_rdy : std_logic;
-- CPU signals
signal cpu_rst : std_logic;
@@ -99,56 +119,67 @@ architecture Behavioral of vga_ctrl_top is
signal cpu_addr : dmem_addr_t;
signal cpu_xrom_data : dmem_data_t;
signal cg_ready : std_logic;
signal cg_clr_screen : std_logic;
signal cg_clr_line : std_logic;
signal cg_ascii_data : dmem_data_t;
signal cg_ascii_data_we : std_logic;
signal cg_ascii_posy_we : std_logic;
signal cg_ascii_posx_we : std_logic;
signal cpu_led : dmem_data_t;
signal cpu_red : dmem_data_t;
signal cpu_green : dmem_data_t;
signal cpu_blue : dmem_data_t;
signal cpu_color : color_t;
signal proc_color : color_t;
begin
inst_vga_backend: entity work.vga_backend
inst_vga_backend : entity work.vga_backend
GENERIC MAP
(
sys_freq => sys_freq,
fifo_depth => fifo_depth,
tsvga => tsvga
)
tsvga => tsvga
)
PORT MAP
(
sys_rst => vga_rst,
sys_clk => clk,
vga_ready => vga_ready,
color_in => color_w,
color_fifo_we => color_we,
color_fifo_full => fifo_full,
color_fifo_afull => fifo_almost_full,
direct_color_in => cpu_color,
direct_draw_en => char_draw_en,
stat_hsync => hsync,
stat_vsync => vsync,
stat_hready => scan_rdy_h,
stat_vready => scan_rdy_v,
stat_hscan => vga_scan_x,
stat_vscan => vga_scan_y,
stat_hpos => vga_pos_x,
stat_vpos => vga_pos_y,
vga_clk_out => vga_clk,
vga_color_out => vga_color,
vga_blank_n => sys_vga_blank_n,
vga_sync_n => sys_vga_sync_n,
vga_hsync => sys_vga_hsync,
vga_vsync => sys_vga_vsync
-- System signals
sys_rst => rst,
sys_clk => clk,
-- Color channels
color_in => color_in,
color_op => color_op,
color_en => color_en,
-- Control signals
ctrl_scan_en => ctrl_scan_en,
-- Status signals
stat_vga_rdy => stat_vga_rdy,
stat_scan => stat_scan,
stat_hsync => stat_hsync,
stat_vsync => stat_vsync,
stat_hready => stat_hready,
stat_vready => stat_vready,
stat_hscan => stat_hscan,
stat_vscan => stat_vscan,
stat_hpos => stat_hpos,
stat_vpos => stat_vpos,
-- VGA domain signals
vga_clk_in => sys_vga_clk_in,
vga_clk_ce => sys_vga_clk_ce,
vga_red => sys_vga_red,
vga_green => sys_vga_green,
vga_blue => sys_vga_blue,
vga_blank_n => sys_vga_blank_n,
vga_sync_n => sys_vga_sync_n,
vga_hsync => sys_vga_hsync,
vga_vsync => sys_vga_vsync
);
vga_clk <= sys_vga_clk_in;
ctrl_scan_en <= '1';
color_en(0) <= '1';
color_en(1) <= cg_draw;
color_in(0) <= cpu_color;
color_in(1) <= cg_color; --(X"FF", X"FF", X"FF", X"FF"); -- white opaque
color_op <= op_over;
vga_scan_rdy <= stat_hready and stat_vready;
inst_char_gen : entity work.char_gen
GENERIC MAP
(
@@ -173,18 +204,22 @@ begin
frame_pulse => scan_rdy,
clr_screen => cg_clr_screen,
clr_line => cg_clr_line,
ascii_data => cg_ascii_data,
ascii_data_we => cg_ascii_data_we,
ascii_posy_we => cg_ascii_posy_we,
ascii_posx_we => cg_ascii_posx_we,
ready => cg_ready,
pos_x => vga_pos_x,
pos_y => vga_pos_y,
char_draw_en => char_draw_en
din => cg_din,
dout => cg_dout,
ascii_we => cg_ascii_we,
posy_we => cg_posy_we,
posx_we => cg_posx_we,
ready => cg_rdy,
scan_pos_x_in => stat_hpos,
scan_pos_y_in => stat_vpos,
csr_pos_x_out => cg_csr_pos_x,
csr_pos_y_out => cg_csr_pos_y,
char_draw_en => cg_draw
);
inst_cpu_embedded: entity work.cpu_embedded
PORT MAP(
PORT MAP
(
rst => cpu_rst,
clk => clk,
ce => cpu_ce,
@@ -199,7 +234,8 @@ begin
);
inst_xrom: entity work.xrom
PORT MAP(
PORT MAP
(
clk => clk,
ce => cpu_ce,
addr => cpu_addr,
@@ -207,19 +243,11 @@ begin
);
---------------------------------------------------------------------------------------------
rst <= not vga_ready;
vga_rst <= not sys_rstn_in;
-- clk <= vga_clk;
rst <= sys_rst_in;
clk <= sys_clk_in;
scan_rdy <= scan_rdy_h and scan_rdy_v;
sys_vga_clk <= vga_clk;
sys_vga_red <= vga_color(r);
sys_vga_green <= vga_color(g);
sys_vga_blue <= vga_color(b);
cg_en <= vga_scan_x and vga_scan_y;
cpu_ce <= '1';
@@ -246,7 +274,7 @@ cpu_reg_read:
when X"05" => -- 05
reg := unsigned(sys_dip);
when X"0B" =>
reg := "000000" & cg_ready & vga_ready;
reg := "000000" & cg_rdy & '0';
when others => null;
end case;
end if;
@@ -265,10 +293,10 @@ cpu_reg_write:
begin
if (rst = '1') then
cpu_led <= (others => '0');
cg_ascii_data <= (others => '0');
cg_ascii_posy_we <= '0';
cg_ascii_posx_we <= '0';
cg_ascii_data_we <= '0';
cg_din <= (others => '0');
cg_posy_we <= '0';
cg_posx_we <= '0';
cg_ascii_we <= '0';
cg_clr_line <= '0';
cg_clr_screen <= '0';
cpu_red <= X"80";
@@ -276,9 +304,9 @@ cpu_reg_write:
cpu_blue <= X"80";
elsif rising_edge(clk) then
cg_ascii_posy_we <= '0';
cg_ascii_posx_we <= '0';
cg_ascii_data_we <= '0';
cg_posy_we <= '0';
cg_posx_we <= '0';
cg_ascii_we <= '0';
cg_clr_line <= '0';
cg_clr_screen <= '0';
addr := cpu_addr;
@@ -294,14 +322,14 @@ cpu_reg_write:
when X"04" => -- 04
cpu_blue <= cpu_dout;
when X"08" => -- 08
cg_ascii_data <= cpu_dout;
cg_ascii_posx_we <= '1';
cg_din <= cpu_dout;
cg_posx_we <= '1';
when X"09" => -- 09
cg_ascii_data <= cpu_dout;
cg_ascii_posy_we <= '1';
cg_din <= cpu_dout;
cg_posy_we <= '1';
when X"0A" => -- 0A
cg_ascii_data <= cpu_dout;
cg_ascii_data_we <= '1';
cg_din <= cpu_dout;
cg_ascii_we <= '1';
when X"0B" => -- 0B
cg_clr_screen <= cpu_dout(0);
cg_clr_line <= cpu_dout(1);
@@ -324,37 +352,13 @@ cpu_reg_write:
end if;
end process;
scan_start: process (rst, clk)
begin
if (rst = '1') then
scan_enable <= '0';
elsif rising_edge(clk) then
scan_enable <= '1';
end if;
end process;
color_sel: process (vga_clk)
begin
if rising_edge(vga_clk) and scan_rdy = '1' then
cpu_color <= (cpu_red, cpu_green, cpu_blue);
cpu_color <= (cpu_red, cpu_green, cpu_blue, X"00");
end if;
end process;
color_we <= scan_enable and src_enable and not fifo_full;
src_inc_reg: process (rst, clk)
begin
if (rst = '1') then
src_enable <= '0';
elsif rising_edge(clk) then
if fifo_full = '1' then
src_enable <= '0';
elsif fifo_almost_full = '0' then
src_enable <= '1';
end if;
end if;
end process;
color_ctrl: process (rst, clk)
variable enable : std_logic;
begin
@@ -362,7 +366,7 @@ cpu_reg_write:
src_pos_x <= 0;
src_pos_y <= 0;
elsif rising_edge(clk) then
if color_we = '1' then
if stat_scan = '1' then
if src_pos_x < tsvga.ts_h.ncyc_scan-1 then
src_pos_x <= src_pos_x + 1;
else
@@ -377,17 +381,17 @@ cpu_reg_write:
end if;
end process;
color_gen: process (src_pos_x, src_pos_y)
color_proc: process (src_pos_x, src_pos_y)
begin
color_w <= (X"00", X"00", X"00");
proc_color <= (X"00", X"00", X"00", X"00");
if src_pos_y = 0 then
color_w <= (X"00", X"FF", X"00");
proc_color <= (X"00", X"FF", X"00", X"00");
elsif src_pos_y = (tsvga.ts_v.ncyc_scan-1) then
color_w <= (X"00", X"FF", X"00");
proc_color <= (X"00", X"FF", X"00", X"00");
elsif src_pos_x = 0 then
color_w <= (X"FF", X"00", X"00");
proc_color <= (X"FF", X"00", X"00", X"00");
elsif src_pos_x = (tsvga.ts_h.ncyc_scan-1) then
color_w <= (X"00", X"00", X"FF");
proc_color <= (X"00", X"00", X"FF", X"00");
end if;
end process;