diff --git a/lib/radio/decimator/CIC/src/syn_cic_c_pipe.vhd b/lib/radio/decimator/CIC/src/syn_cic_c_pipe.vhd
index 7fb46c5..70e3007 100644
--- a/lib/radio/decimator/CIC/src/syn_cic_c_pipe.vhd
+++ b/lib/radio/decimator/CIC/src/syn_cic_c_pipe.vhd
@@ -17,8 +17,11 @@ use IEEE.MATH_REAL.ALL;
 USE ieee.numeric_std.ALL;
 use std.textio.all; --  Imports the standard textio package.
 
+library ieee_proposed;
+use ieee_proposed.math_utility_pkg.all;
+use ieee_proposed.fixed_pkg.all;
+
 library work;
-use work.fixed_pkg.all;
 use work.fixed_util_pkg.all;
 
 entity syn_cic_c_pipe is
@@ -26,11 +29,7 @@ Generic
 (
 	max_diff_delay	: integer := 2;
 	max_width		: integer := 32;
-	max_width_frac	: integer := 20;
-	in_width		: integer := 32;
-	in_width_frac	: integer := 20;
-	out_width		: integer := 32;
-	out_width_frac	: integer := 20
+	max_width_frac	: integer := 20
 );
 Port
 (
@@ -38,8 +37,8 @@ Port
 	rst			: in std_logic;
 	vld_in		: in std_logic;
 	diff_delay	: in natural range 1 to max_diff_delay;
-	din			: in signed(in_width-1 downto 0);
-	dout		: out signed(out_width-1 downto 0);
+	din			: in signed(max_width-1 downto 0);
+	dout		: out signed(max_width-1 downto 0);
 	vld_out 	: out std_logic
 );
 end syn_cic_c_pipe;
@@ -52,11 +51,7 @@ ARCHITECTURE behavior OF syn_cic_c_pipe IS
 	(
 		max_diff_delay	: integer;
 		max_width		: integer;
-		max_width_frac	: integer;
-		in_width		: integer;
-		in_width_frac	: integer;
-		out_width		: integer;
-		out_width_frac	: integer
+		max_width_frac	: integer
 	);
 	PORT
 	(
@@ -71,10 +66,10 @@ ARCHITECTURE behavior OF syn_cic_c_pipe IS
 	END COMPONENT;
 
 	--Inputs
-	SIGNAL sdin			: sfixed(shi(in_width, in_width_frac) downto slo(in_width, in_width_frac));
+	SIGNAL sdin			: sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
 	
 	--Outputs
-	SIGNAL sdout		: sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac));
+	SIGNAL sdout		: sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
 	
 BEGIN
 
@@ -84,11 +79,7 @@ BEGIN
 	(
 		max_diff_delay	=> max_diff_delay,
 		max_width		=> max_width,
-		max_width_frac	=> max_width_frac,
-		in_width		=> in_width,
-		in_width_frac	=> in_width_frac,
-		out_width		=> out_width,
-		out_width_frac	=> out_width_frac
+		max_width_frac	=> max_width_frac
 	)
 	PORT MAP
 	(
@@ -101,7 +92,7 @@ BEGIN
 		vld_out			=> vld_out
 	);
 
-	sdin	<= to_sfixed(din, shi(in_width, in_width_frac), slo(in_width, in_width_frac));
+	sdin	<= to_sfixed(din, shi(max_width, max_width_frac), slo(max_width, max_width_frac));
 	dout	<= signed(sdout);
 
 END;
diff --git a/lib/radio/decimator/CIC/src/syn_cic_i_pipe.vhd b/lib/radio/decimator/CIC/src/syn_cic_i_pipe.vhd
index 349134c..52428ed 100644
--- a/lib/radio/decimator/CIC/src/syn_cic_i_pipe.vhd
+++ b/lib/radio/decimator/CIC/src/syn_cic_i_pipe.vhd
@@ -17,28 +17,26 @@ use IEEE.MATH_REAL.ALL;
 USE ieee.numeric_std.ALL;
 use std.textio.all; --  Imports the standard textio package.
 
+library ieee_proposed;
+use ieee_proposed.math_utility_pkg.all;
+use ieee_proposed.fixed_pkg.all;
+
 library work;
-use work.fixed_pkg.all;
 use work.fixed_util_pkg.all;
 
 entity syn_cic_i_pipe is
 Generic
 (
 	max_width		: integer := 32;
-	max_width_frac	: integer := 20;
-	in_width		: integer := 32;
-	in_width_frac	: integer := 20;
-	out_width		: integer := 32;
-	out_width_frac	: integer := 20
+	max_width_frac	: integer := 20
 );
 Port
 (
 	clk			: in std_logic;
 	rst			: in std_logic;
 	vld_in		: in std_logic;
-	shamt		: in natural range 0 to max_width-1;
-	din			: in signed(in_width-1 downto 0);
-	dout		: out signed(out_width-1 downto 0);
+	din			: in signed(max_width-1 downto 0);
+	dout		: out signed(max_width-1 downto 0);
 	vld_out 	: out std_logic
 );
 end syn_cic_i_pipe;
@@ -50,18 +48,13 @@ ARCHITECTURE behavior OF syn_cic_i_pipe IS
 	GENERIC
 	(
 		max_width		: integer;
-		max_width_frac	: integer;
-		in_width		: integer;
-		in_width_frac	: integer;
-		out_width		: integer;
-		out_width_frac	: integer
+		max_width_frac	: integer
 	);
 	PORT
 	(
 		clk			: in std_logic;
 		rst			: in std_logic;
 		vld_in		: in std_logic;
-		shamt		: in natural range 0 to max_width-1;
 		din			: in sfixed;
 		dout		: out sfixed;
 		vld_out 	: out std_logic
@@ -69,10 +62,10 @@ ARCHITECTURE behavior OF syn_cic_i_pipe IS
 	END COMPONENT;
 
 	--Inputs
-	SIGNAL sdin			: sfixed(shi(in_width, in_width_frac) downto slo(in_width, in_width_frac));
+	SIGNAL sdin			: sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
 	
 	--Outputs
-	SIGNAL sdout		: sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac));
+	SIGNAL sdout		: sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
 	
 BEGIN
 
@@ -81,24 +74,19 @@ BEGIN
 	GENERIC MAP
 	(
 		max_width		=> max_width,
-		max_width_frac	=> max_width_frac,
-		in_width		=> in_width,
-		in_width_frac	=> in_width_frac,
-		out_width		=> out_width,
-		out_width_frac	=> out_width_frac
+		max_width_frac	=> max_width_frac
 	)
 	PORT MAP
 	(
 		clk				=> clk,
 		rst				=> rst,
 		vld_in			=> vld_in,
-		shamt			=> shamt,
 		din				=> sdin,
 		dout			=> sdout,
 		vld_out			=> vld_out
 	);
 
-	sdin	<= to_sfixed(din, shi(in_width, in_width_frac), slo(in_width, in_width_frac));
+	sdin	<= to_sfixed(din, shi(max_width, max_width_frac), slo(max_width, max_width_frac));
 	dout	<= signed(sdout);
 
 END;