- Intital revision

git-svn-id: http://moon:8086/svn/vhdl/trunk@133 cc03376c-175c-47c8-b038-4cd826a8556b

lib/ac97_ctrl/src/tb_ac97_wb.vhd

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+
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:33:47 06/05/2007
+-- Design Name:   eval_ac
+-- Module Name:   E:/work/VHDL/eval_ac/tb_eval_ac.vhd
+-- Project Name:  ac_out
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-- VHDL Test Bench Created by ISE for module: ac_out
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
+-- that these types always be used for the top-level I/O of a design in order 
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_ac97_wb IS
+END tb_ac97_wb;
+
+ARCHITECTURE behavior OF tb_ac97_wb IS 
+
+	constant SYS_CLK_PERIOD : time := 10 ns;
+	CONSTANT BIT_CLK_PERIOD : time := 100 ns;
+--	constant BIT_CLK_PERIOD : time := 81.38 ns;
+	
+	signal CLK_O	: std_logic := '1';
+	signal RST_O	: std_logic := '1';
+	signal CYC_O	: std_logic := '0';
+	signal STB_O	: std_logic := '0';
+	signal WE_O		: std_logic := '0';
+	signal ACK_I	: std_logic;
+	signal MRDY_O	: std_logic := '1';
+	signal SRDY_I	: std_logic;
+	signal INT_I	: std_logic;
+	signal ADDR_O	: unsigned(31 downto 0) := (others => '-');
+	signal DAT_I	: unsigned(31 downto 0);
+	signal DAT_O	: unsigned(31 downto 0) := (others => '-');
+
+	signal dout_rst			: std_logic := '0';
+	signal dout_reg			: unsigned(31 downto 0);
+	signal dout_cnt			: natural range 0 to 255;
+
+	SIGNAL ac97_bit_clk		:  std_logic := '0';
+	SIGNAL ac97_reset_n		:  std_logic;
+	SIGNAL ac97_sdata_out	:  std_logic;
+	SIGNAL ac97_ssync		:  std_logic;
+	SIGNAL ac97_sdata_in	:  std_logic;
+
+BEGIN
+
+	-- Instantiate the Unit Under Test (UUT)
+uut : entity work.ac97_wb
+	GENERIC MAP
+	(
+		fifo_depth		=> 4
+	)
+	PORT MAP
+	(
+		-- J-Bus domain
+		CLK_I			=> CLK_O,
+		RST_I			=> RST_O,
+		CYC_I			=> CYC_O,
+		STB_I			=> STB_O,
+		WE_I			=> WE_O,
+		ACK_O			=> ACK_I,
+		SRDY_O			=> SRDY_I,
+		MRDY_I			=> MRDY_O,
+		ADDR_I			=> ADDR_O,
+		DAT_I			=> DAT_O,
+		DAT_O			=> DAT_I,
+		INT_O			=> INT_I,
+
+		-- AC97 domain
+		ac97_sdata_in	=> ac97_sdata_in,
+		ac97_bit_clk	=> ac97_bit_clk,          
+		ac97_reset_n	=> ac97_reset_n,
+		ac97_sdata_out	=> ac97_sdata_out,
+		ac97_ssync		=> ac97_ssync		
+	);
+
+	
+	ac97_sdata_in <= ac97_sdata_out;
+	
+CLK_GEN: process
+	begin
+		wait for SYS_CLK_PERIOD/2;
+		CLK_O <= not CLK_O;
+	end process;
+
+	bit_clk_gen : PROCESS
+	begin
+		if (ac97_reset_n = '0') then
+			ac97_bit_clk <= '0';
+			wait until ac97_reset_n = '1';
+			wait for 150 us;
+		end if;	
+		wait for BIT_CLK_PERIOD/2;
+		ac97_bit_clk <= not ac97_bit_clk;
+	END PROCESS;
+
+STIMULUS: process
+
+	begin
+
+		wait for 3*SYS_CLK_PERIOD;
+		RST_O <= '0';
+
+		wait for 200 us;
+		wait until rising_edge(CLK_O);
+
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		DAT_O	<= X"0000_0000";
+		ADDR_O	<= X"0000_0000";
+		wait until rising_edge(CLK_O);
+		STB_O	<= '0';
+		wait until rising_edge(CLK_O) and ACK_I = '1';
+		CYC_O	<= '0';
+
+		wait until rising_edge(CLK_O);
+
+		CYC_O	<= '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		DAT_O	<= X"5555_1000";
+		ADDR_O	<= X"0000_0800";
+		wait until rising_edge(CLK_O);
+		DAT_O	<= X"5555_1001";
+		wait until rising_edge(CLK_O);
+		STB_O	<= '0';
+		CYC_O	<= '0';
+
+		WAIT;
+	END PROCESS;
+END;