From 4fe3a1c636f4a8521d5255b54794d1a97dfff24c Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Tue, 30 Dec 2008 04:32:07 +0000 Subject: [PATCH] - combine in/out_width to max_width - uses ieee_proposed.fixed_pkg git-svn-id: http://moon:8086/svn/vhdl/trunk@167 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/radio/decimator/CIC/src/cic_c_pipe.vhd | 13 ++++---- lib/radio/decimator/CIC/src/cic_i_pipe.vhd | 13 ++++---- lib/radio/decimator/CIC/src/tb_cic_c_pipe.vhd | 33 +++++++------------ lib/radio/decimator/CIC/src/tb_cic_i_pipe.vhd | 31 +++++++---------- 4 files changed, 35 insertions(+), 55 deletions(-) diff --git a/lib/radio/decimator/CIC/src/cic_c_pipe.vhd b/lib/radio/decimator/CIC/src/cic_c_pipe.vhd index ac06dd4..41063f0 100644 --- a/lib/radio/decimator/CIC/src/cic_c_pipe.vhd +++ b/lib/radio/decimator/CIC/src/cic_c_pipe.vhd @@ -21,8 +21,11 @@ LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; +library ieee_proposed; +use ieee_proposed.math_utility_pkg.all; +use ieee_proposed.fixed_pkg.all; + library work; -use work.fixed_pkg.all; use work.fixed_util_pkg.all; ---- Uncomment the following library declaration if instantiating @@ -35,11 +38,7 @@ Generic ( max_diff_delay : integer := 1; max_width : integer := 32; - max_width_frac : integer := 20; - in_width : integer := 32; - in_width_frac : integer := 20; - out_width : integer := 32; - out_width_frac : integer := 20 + max_width_frac : integer := 20 ); Port ( @@ -95,7 +94,7 @@ comb_proc: dout <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0'); elsif vld_in = '1' then vld_out <= '1'; - dout <= resize(x0 - x1, shi(out_width, out_width_frac), slo(out_width, out_width_frac)); + dout <= resize(x0 - x1, shi(max_width, max_width_frac), slo(max_width, max_width_frac)); end if; end if; end process; diff --git a/lib/radio/decimator/CIC/src/cic_i_pipe.vhd b/lib/radio/decimator/CIC/src/cic_i_pipe.vhd index 91db1bb..0880ca3 100644 --- a/lib/radio/decimator/CIC/src/cic_i_pipe.vhd +++ b/lib/radio/decimator/CIC/src/cic_i_pipe.vhd @@ -21,8 +21,11 @@ LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; +library ieee_proposed; +use ieee_proposed.math_utility_pkg.all; +use ieee_proposed.fixed_pkg.all; + library work; -use work.fixed_pkg.all; use work.fixed_util_pkg.all; ---- Uncomment the following library declaration if instantiating @@ -34,11 +37,7 @@ entity cic_i_pipe is Generic ( max_width : integer := 32; - max_width_frac : integer := 20; - in_width : integer := 32; - in_width_frac : integer := 20; - out_width : integer := 32; - out_width_frac : integer := 20 + max_width_frac : integer := 20 ); Port ( @@ -58,7 +57,7 @@ signal accu : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_ ------------------------------------------------------------ begin - dout <= resize(accu, shi(out_width, out_width_frac), slo(out_width, out_width_frac)); + dout <= resize(accu, shi(max_width, max_width_frac), slo(max_width, max_width_frac)); ------------------------------------------------------------ integ_proc: diff --git a/lib/radio/decimator/CIC/src/tb_cic_c_pipe.vhd b/lib/radio/decimator/CIC/src/tb_cic_c_pipe.vhd index 778bdb9..d36268d 100644 --- a/lib/radio/decimator/CIC/src/tb_cic_c_pipe.vhd +++ b/lib/radio/decimator/CIC/src/tb_cic_c_pipe.vhd @@ -17,20 +17,19 @@ use IEEE.MATH_REAL.ALL; USE ieee.numeric_std.ALL; use std.textio.all; -- Imports the standard textio package. +library ieee_proposed; +use ieee_proposed.math_utility_pkg.all; +use ieee_proposed.fixed_pkg.all; + library work; use work.PCK_FIO.all; -use work.fixed_pkg.all; use work.fixed_util_pkg.all; ENTITY tb_cic_c_pipe IS Generic ( max_width : integer := 32; - max_width_frac : integer := 20; - in_width : integer := 32; - in_width_frac : integer := 20; - out_width : integer := 32; - out_width_frac : integer := 20 + max_width_frac : integer := 20 ); END tb_cic_c_pipe; @@ -42,11 +41,7 @@ ARCHITECTURE behavior OF tb_cic_c_pipe IS ( max_diff_delay : integer; max_width : integer; - max_width_frac : integer; - in_width : integer; - in_width_frac : integer; - out_width : integer; - out_width_frac : integer + max_width_frac : integer ); PORT ( @@ -68,11 +63,11 @@ ARCHITECTURE behavior OF tb_cic_c_pipe IS SIGNAL clk : std_logic := '0'; SIGNAL srst : std_logic := '1'; SIGNAL vld_in : std_logic := '0'; - SIGNAL din : sfixed(shi(in_width, in_width_frac) downto slo(in_width, in_width_frac)); + SIGNAL din : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac)); SIGNAL diff_delay : natural := 1; --Outputs - SIGNAL dout : sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac)); + SIGNAL dout : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac)); SIGNAL vld_out : std_logic; SIGNAL fileout_enable : std_logic := '0'; @@ -85,11 +80,7 @@ BEGIN ( max_diff_delay => 2, max_width => max_width, - max_width_frac => max_width_frac, - in_width => in_width, - in_width_frac => in_width_frac, - out_width => out_width, - out_width_frac => out_width_frac + max_width_frac => max_width_frac ) PORT MAP ( @@ -119,18 +110,18 @@ BEGIN ------------------------------------------ wait for 2*PERIOD; wait until rising_edge(clk); - din <= to_sfixed(0.0, din, false, true); + din <= to_sfixed(0.0, din); vld_in <= '1'; wait for 9*PERIOD; wait until rising_edge(clk); - din <= to_sfixed(0.5, din, false, true); + din <= to_sfixed(0.5, din); wait for 9*PERIOD; wait until rising_edge(clk); - din <= to_sfixed(0.0, din, false, true); + din <= to_sfixed(0.0, din); wait for 9*PERIOD; wait until rising_edge(clk); diff --git a/lib/radio/decimator/CIC/src/tb_cic_i_pipe.vhd b/lib/radio/decimator/CIC/src/tb_cic_i_pipe.vhd index 4efba2a..b3ae7d5 100644 --- a/lib/radio/decimator/CIC/src/tb_cic_i_pipe.vhd +++ b/lib/radio/decimator/CIC/src/tb_cic_i_pipe.vhd @@ -17,20 +17,19 @@ use IEEE.MATH_REAL.ALL; USE ieee.numeric_std.ALL; use std.textio.all; -- Imports the standard textio package. +library ieee_proposed; +use ieee_proposed.math_utility_pkg.all; +use ieee_proposed.fixed_pkg.all; + library work; use work.PCK_FIO.all; -use work.fixed_pkg.all; use work.fixed_util_pkg.all; ENTITY tb_cic_i_pipe IS Generic ( max_width : integer := 32; - max_width_frac : integer := 20; - in_width : integer := 32; - in_width_frac : integer := 20; - out_width : integer := 32; - out_width_frac : integer := 20 + max_width_frac : integer := 20 ); END tb_cic_i_pipe; @@ -41,11 +40,7 @@ ARCHITECTURE behavior OF tb_cic_i_pipe IS GENERIC ( max_width : integer; - max_width_frac : integer; - in_width : integer; - in_width_frac : integer; - out_width : integer; - out_width_frac : integer + max_width_frac : integer ); PORT ( @@ -66,10 +61,10 @@ ARCHITECTURE behavior OF tb_cic_i_pipe IS SIGNAL clk : std_logic := '0'; SIGNAL srst : std_logic := '1'; SIGNAL vld_in : std_logic := '0'; - SIGNAL din : sfixed(shi(in_width, in_width_frac) downto slo(in_width, in_width_frac)); + SIGNAL din : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac)); --Outputs - SIGNAL dout : sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac)); + SIGNAL dout : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac)); SIGNAL vld_out : std_logic; SIGNAL fileout_enable : std_logic := '0'; @@ -81,11 +76,7 @@ BEGIN GENERIC MAP ( max_width => max_width, - max_width_frac => max_width_frac, - in_width => in_width, - in_width_frac => in_width_frac, - out_width => out_width, - out_width_frac => out_width_frac + max_width_frac => max_width_frac ) PORT MAP ( @@ -114,13 +105,13 @@ BEGIN ------------------------------------------ wait for 2*PERIOD; wait until rising_edge(clk); - din <= to_sfixed(0.0, din, false, true); + din <= to_sfixed(0.0, din); vld_in <= '1'; wait for 9*PERIOD; wait until rising_edge(clk); - din <= to_sfixed(0.5, din, false, true); + din <= to_sfixed(0.5, din); wait for 9*PERIOD; wait until rising_edge(clk);