From 4f193246058fd0811dab3ede568d3657bc4d9c92 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 15 Mar 2009 20:12:37 +0000 Subject: [PATCH] - added cop0 here - added cache line sizes to generic Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@390 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/MIPS/src/core/mips_top.vhd | 90 +++++++++++++++++++++++++++-- 1 file changed, 85 insertions(+), 5 deletions(-) diff --git a/lib/CPUs/MIPS/src/core/mips_top.vhd b/lib/CPUs/MIPS/src/core/mips_top.vhd index dd56ec5..a8af971 100644 --- a/lib/CPUs/MIPS/src/core/mips_top.vhd +++ b/lib/CPUs/MIPS/src/core/mips_top.vhd @@ -32,7 +32,9 @@ entity mips_top is Generic ( icache_size : natural := 4096; -- words - dcache_size : natural := 4096 -- words + icache_line : natural := 8; -- words + dcache_size : natural := 4096; -- words + dcache_line : natural := 8 -- words ); Port ( @@ -56,6 +58,9 @@ end mips_top; architecture rtl of mips_top is +-------------------------------------------------------------------------- +-- Pipeline +-------------------------------------------------------------------------- COMPONENT pipeline is Port ( @@ -75,7 +80,14 @@ architecture rtl of mips_top is dmem_be : out unsigned(3 downto 0); dmem_addr : out word_t; dmem_din : in word_t; - dmem_dout : out word_t + dmem_dout : out word_t; + cop_ir : out word_t; + cop_ir_en : out STD_LOGIC; + cop_reg_rd : in STD_LOGIC; + cop_din : in word_t; + cop_dout : out word_t; + c0_ctrl_out : out cop0_ctrl_in_t; + c0_ctrl_in : in cop0_ctrl_out_t ); END COMPONENT; signal imem_err : std_logic; @@ -95,11 +107,49 @@ architecture rtl of mips_top is signal cpu_rst : STD_LOGIC; signal cpu_run : STD_LOGIC; + signal pipe_cop_ir : word_t; + signal pipe_cop_ir_en : STD_LOGIC; + signal pipe_cop_reg_rd : STD_LOGIC; + signal pipe_cop_din : word_t; + signal pipe_cop_dout : word_t; + signal pipe_c0_ctrl_out : cop0_ctrl_in_t; + signal pipe_c0_ctrl_in : cop0_ctrl_out_t; + +-------------------------------------------------------------------------- +-- Coprocessor +-------------------------------------------------------------------------- + COMPONENT cop is + GENERIC + ( + icache_size : natural; + icache_line : natural; + dcache_size : natural; + dcache_line : natural + ); + Port + ( + rst : in STD_LOGIC; + clk : in STD_LOGIC; + ir_en : in STD_LOGIC; + ir : in word_t; + ctrl_in : in cop0_ctrl_in_t; + ctrl_out : out cop0_ctrl_out_t; + reg_rd : out STD_LOGIC; + din : in word_t; + dout : out word_t + ); + END COMPONENT; + +-------------------------------------------------------------------------- +-- Bus Interface Unit +-------------------------------------------------------------------------- COMPONENT biu GENERIC ( icache_size : natural; - dcache_size : natural + icache_line : natural; + dcache_size : natural; + dcache_line : natural ); PORT ( @@ -175,14 +225,44 @@ inst_pipeline: pipeline dmem_be => dmem_be, dmem_addr => dmem_addr, dmem_din => dmem_din, - dmem_dout => dmem_dout + dmem_dout => dmem_dout, + cop_ir => pipe_cop_ir, + cop_ir_en => pipe_cop_ir_en, + cop_reg_rd => pipe_cop_reg_rd, + cop_din => pipe_cop_din, + cop_dout => pipe_cop_dout, + c0_ctrl_out => pipe_c0_ctrl_out, + c0_ctrl_in => pipe_c0_ctrl_in ); +inst_cop: cop + GENERIC MAP + ( + icache_size => icache_size, -- words + icache_line => icache_line, -- words + dcache_size => dcache_size, -- words + dcache_line => dcache_line -- words + ) + PORT MAP + ( + rst => cpu_rst, + clk => CLK_I, + ir_en => pipe_cop_ir_en, + ir => pipe_cop_ir, + ctrl_in => pipe_c0_ctrl_out, + ctrl_out => pipe_c0_ctrl_in, + reg_rd => pipe_cop_reg_rd, + dout => pipe_cop_din, + din => pipe_cop_dout + ); + inst_biu: biu GENERIC MAP ( icache_size => icache_size, -- words - dcache_size => dcache_size -- words + icache_line => icache_line, -- words + dcache_size => dcache_size, -- words + dcache_line => dcache_line -- words ) PORT MAP (