From 4e2cb682371d3e8edbc33c35655a3954ef7b4903 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 11 Jan 2009 17:08:38 +0000 Subject: [PATCH] - Minor changes git-svn-id: http://moon:8086/svn/vhdl/trunk@228 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/filter/src/fir_stage_sys.vhd | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/lib/filter/src/fir_stage_sys.vhd b/lib/filter/src/fir_stage_sys.vhd index bf381a0..f180b19 100644 --- a/lib/filter/src/fir_stage_sys.vhd +++ b/lib/filter/src/fir_stage_sys.vhd @@ -94,7 +94,7 @@ begin x_out <= resize(xin, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac)); ------------------------------------------------------------ - proc_xin: process(clk, x_in) + proc_xin: process(clk, x_in, x_pipe(0)) begin x_pipe(0) <= resize(x_in, x_pipe(0)); if rising_edge(clk) then @@ -108,7 +108,7 @@ begin end process; ------------------------------------------------------------ - proc_hin: process(clk, h_in) + proc_hin: process(clk, h_in, h_pipe(0)) begin h_pipe(0) <= resize(h_in, h_pipe(0)); if rising_edge(clk) then @@ -122,7 +122,7 @@ begin end process; ------------------------------------------------------------ - proc_pipe_reg: process(clk, xin, hin) + proc_pipe_reg: process(clk, xin, hin, mult_pipe(0)) begin mult_pipe(0) <= resize(xin * hin, mult_pipe(0)); if rising_edge(clk) then