diff --git a/lib/filter/src/fir_stage_sys.vhd b/lib/filter/src/fir_stage_sys.vhd
index bf381a0..f180b19 100644
--- a/lib/filter/src/fir_stage_sys.vhd
+++ b/lib/filter/src/fir_stage_sys.vhd
@@ -94,7 +94,7 @@ begin
 	x_out	 	<= resize(xin, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac));
 
 ------------------------------------------------------------
-	proc_xin: process(clk, x_in)
+	proc_xin: process(clk, x_in, x_pipe(0))
 	begin
 		x_pipe(0)	<= resize(x_in, x_pipe(0));
 		if rising_edge(clk) then
@@ -108,7 +108,7 @@ begin
 	end process;
 
 ------------------------------------------------------------
-	proc_hin: process(clk, h_in)
+	proc_hin: process(clk, h_in, h_pipe(0))
 	begin
 		h_pipe(0)	<= resize(h_in, h_pipe(0));
 		if rising_edge(clk) then
@@ -122,7 +122,7 @@ begin
 	end process;
 
 ------------------------------------------------------------
-	proc_pipe_reg: process(clk, xin, hin)
+	proc_pipe_reg: process(clk, xin, hin, mult_pipe(0))
 	begin
 		mult_pipe(0)	<= resize(xin * hin, mult_pipe(0));
 		if rising_edge(clk) then