- added read enable for DPRAM. Inhibits dout to be altered if FIFO is already empty on reads

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git-svn-id: http://moon:8086/svn/vhdl/trunk@720 cc03376c-175c-47c8-b038-4cd826a8556b

lib/FIFO/src/async_fifo_ctrl.vhd

@@ -45,6 +45,8 @@ entity fifo_async_ctrl is
 		re					: in  STD_LOGIC;
 		ptr_w				: out unsigned (addr_width-1 downto 0);
 		ptr_r				: out unsigned (addr_width-1 downto 0);
+		fifo_pre_full		: out STD_LOGIC;
+		fifo_pre_empty		: out STD_LOGIC;
 		fifo_full			: out STD_LOGIC;
 		fifo_empty			: out STD_LOGIC;
 		fifo_afull			: out STD_LOGIC;
@@ -67,8 +69,8 @@ architecture Behavioral of fifo_async_ctrl is
 	signal gnxt_r		: unsigned (addr_width downto 0);
 	signal bnxt_r		: unsigned (addr_width downto 0);
 
-	signal empty, full : std_logic;
+	signal pre_empty, pre_full : std_logic;
-	signal write_inhibit, read_inhibit : std_logic;
+	signal full, empty : std_logic;
 	signal winc, rinc : std_logic;
 
 	-- synthesis translate_off
@@ -80,18 +82,20 @@ begin
 
 	ptr_w			<= bcnt_w(addr_width-1 downto 0);
 	ptr_r			<= bnxt_r(addr_width-1 downto 0);
-	winc		<= we and (not write_inhibit);
+	winc			<= we and (not full);
-	rinc		<= re and (not read_inhibit);
+	rinc			<= re and (not empty);
-	fifo_full	<= write_inhibit;
+	fifo_full		<= full;
-	fifo_empty	<= read_inhibit;
+	fifo_empty		<= empty;
+	fifo_pre_full	<= pre_full;
+	fifo_pre_empty	<= pre_empty;
 	
 proc_write_inhibit:
 	process(rst, clk_w)
 	begin
 		if rst = '1' then
-			write_inhibit	<= '0';
+			full	<= '0';
 		elsif rising_edge(clk_w) then
-			write_inhibit	<= full;
+			full	<= pre_full;
 		end if;
 	end process;
 	
@@ -99,9 +103,9 @@ proc_read_inhibit:
 	process(rst, clk_r)
 	begin
 		if rst = '1' then
-			read_inhibit	<= '1';
+			empty	<= '1';
 		elsif rising_edge(clk_r) then
-			read_inhibit	<= empty;
+			empty	<= pre_empty;
 		end if;
 	end process;
 
@@ -131,9 +135,9 @@ proc_status_full:
 	process(gnxt_w, gcnt2_r)
 	begin
 		if (gnxt_w = (not gcnt2_r(gcnt2_r'left downto gcnt2_r'left-1) & gcnt2_r(gcnt2_r'left-2 downto 0))) then
-			full <= '1';
+			pre_full <= '1';
 		else
-			full <= '0';
+			pre_full <= '0';
 		end if;
 	end process;
 
@@ -141,9 +145,9 @@ proc_status_empty:
 	process(gnxt_r, gcnt2_w)
 	begin
 		if (gnxt_r = gcnt2_w) then
-			empty <= '1';
+			pre_empty <= '1';
 		else
-			empty <= '0';
+			pre_empty <= '0';
 		end if;
 	end process;
 	

lib/FIFO/src/fifo_async.vhd

@@ -54,14 +54,18 @@ end fifo_async;
 
 architecture Behavioral of fifo_async is
 	
+	signal mem_wr_en	: STD_LOGIC;
+	signal mem_rd_en	: STD_LOGIC;
 	signal ptr_w		: unsigned (addr_width-1 downto 0);
 	signal ptr_r		: unsigned (addr_width-1 downto 0);
 	signal full			: std_logic;
-	signal mem_we		: std_logic;
+	signal pre_full		: STD_LOGIC;
+	signal pre_empty	: STD_LOGIC;
 	
 begin
 
-	mem_we		<= we and not full;
+	mem_wr_en	<= we and not full;
+	mem_rd_en	<= not pre_empty;
 	fifo_full	<= full;
 	
 	-- Instantiate the Unit Under Test (UUT)
@@ -83,6 +87,8 @@ begin
 		ptr_r			=>	ptr_r,
 		fifo_full		=>	full,
 		fifo_empty		=>	fifo_empty,
+		fifo_pre_full	=>	pre_full,
+		fifo_pre_empty	=>	pre_empty,
 		fifo_afull		=>	fifo_afull,
 		fifo_aempty		=>	fifo_aempty
 
@@ -98,8 +104,8 @@ inst_dpram_1w1r: entity work.dpram_1w1r
 		clka		=> clk_w,
 		clkb		=> clk_r,
 		en_a		=> '1',
-		en_b		=> '1',
+		en_b		=> mem_rd_en,
-		we_a		=> mem_we,
+		we_a		=> mem_wr_en,
 		addr_a		=> ptr_w,
 		addr_b		=> ptr_r,
 		din_a		=> data_w,