- added read enable for DPRAM. Inhibits dout to be altered if FIFO is already empty on reads

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git-svn-id: http://moon:8086/svn/vhdl/trunk@720 cc03376c-175c-47c8-b038-4cd826a8556b

lib/FIFO/src/fifo_async.vhd

@@ -54,15 +54,19 @@ end fifo_async;
 
 architecture Behavioral of fifo_async is
 	
+	signal mem_wr_en	: STD_LOGIC;
+	signal mem_rd_en	: STD_LOGIC;
 	signal ptr_w		: unsigned (addr_width-1 downto 0);
 	signal ptr_r		: unsigned (addr_width-1 downto 0);
 	signal full			: std_logic;
-	signal mem_we		: std_logic;
+	signal pre_full		: STD_LOGIC;
+	signal pre_empty	: STD_LOGIC;
 	
 begin
 
-	mem_we		<= we and not full;
-	fifo_full <= full;
+	mem_wr_en	<= we and not full;
+	mem_rd_en	<= not pre_empty;
+	fifo_full	<= full;
 	
 	-- Instantiate the Unit Under Test (UUT)
 	inst_fifo_async_ctrl: entity work.fifo_async_ctrl
@@ -74,17 +78,19 @@ begin
 	)
 	PORT MAP
 	(
-		rst			=>	rst,
-		clk_w		=>	clk_w,
-		clk_r		=>	clk_r,
-		we			=>	we,
-		re			=>	re,
-		ptr_w		=>	ptr_w,
-		ptr_r		=>	ptr_r,
-		fifo_full	=>	full,
-		fifo_empty	=>	fifo_empty,
-		fifo_afull	=>	fifo_afull,
-		fifo_aempty	=>	fifo_aempty
+		rst				=>	rst,
+		clk_w			=>	clk_w,
+		clk_r			=>	clk_r,
+		we				=>	we,
+		re				=>	re,
+		ptr_w			=>	ptr_w,
+		ptr_r			=>	ptr_r,
+		fifo_full		=>	full,
+		fifo_empty		=>	fifo_empty,
+		fifo_pre_full	=>	pre_full,
+		fifo_pre_empty	=>	pre_empty,
+		fifo_afull		=>	fifo_afull,
+		fifo_aempty		=>	fifo_aempty
 
 	);
 
@@ -98,8 +104,8 @@ inst_dpram_1w1r: entity work.dpram_1w1r
 		clka		=> clk_w,
 		clkb		=> clk_r,
 		en_a		=> '1',
-		en_b		=> '1',
-		we_a		=> mem_we,
+		en_b		=> mem_rd_en,
+		we_a		=> mem_wr_en,
 		addr_a		=> ptr_w,
 		addr_b		=> ptr_r,
 		din_a		=> data_w,