diff --git a/Common/sim/ModelSim SE .lnk b/Common/sim/ModelSim SE .lnk
deleted file mode 100644
index ecadd02..0000000
Binary files a/Common/sim/ModelSim SE .lnk and /dev/null differ
diff --git a/Common/sim/compile_simprim.do b/Common/sim/compile_simprim.do
deleted file mode 100644
index 0d97d06..0000000
--- a/Common/sim/compile_simprim.do
+++ /dev/null
@@ -1,8 +0,0 @@
-vlib simprim
-
-set XILINX C:/Programme/Xilinx101/ISE
-
-vcom -93 -work simprim  $XILINX/vhdl/src/simprims/simprim_Vcomponents_mti.vhd
-vcom -93 -work simprim  $XILINX/vhdl/src/simprims/simprim_Vpackage_mti.vhd
-vcom -93 -work simprim  $XILINX/vhdl/src/simprims/simprim_SMODEL_mti.vhd
-vcom -93 -work simprim  $XILINX/vhdl/src/simprims/simprim_VITAL_mti.vhd
diff --git a/Common/sim/compile_unisim.do b/Common/sim/compile_unisim.do
deleted file mode 100644
index 6e91db1..0000000
--- a/Common/sim/compile_unisim.do
+++ /dev/null
@@ -1,8 +0,0 @@
-vlib unisim
-
-set XILINX C:/Programme/Xilinx101/ISE
-
-vcom -93 -work unisim  $XILINX/vhdl/src/unisims/unisim_vpkg.vhd
-vcom -93 -work unisim  $XILINX/vhdl/src/unisims/unisim_vcomp.vhd
-vcom -93 -work unisim  $XILINX/vhdl/src/unisims/unisim_smodel.vhd
-vcom -93 -work unisim  $XILINX/vhdl/src/unisims/unisim_vital.vhd
diff --git a/Common/ucf/ml402.ucf b/Common/ucf/ml402.ucf
deleted file mode 100644
index 318e778..0000000
--- a/Common/ucf/ml402.ucf
+++ /dev/null
@@ -1,675 +0,0 @@
-#
-#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
-#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
-#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
-#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
-#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
-#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-#     FOR A PARTICULAR PURPOSE.
-#     
-#     (c) Copyright 2005 Xilinx, Inc.
-#     All rights reserved.
-#
-
-# Bus clock nets
-NET "sys_clk"  TNM_NET = "sys_clk";
-NET "tft_clk"  TNM_NET = "tft_clk";
-NET sys_clk_in TNM_NET = "sys_clk_in";
-TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %;
-
-NET sys_clk_in LOC = AE14;
-NET sys_clk_in IOSTANDARD = LVCMOS33;
-NET sys_rst_in LOC = D6;
-NET sys_rst_in PULLUP;
-NET sys_rst_in TIG;
-
-NET uart_RX LOC = W2;
-NET uart_RX IOSTANDARD = LVCMOS33;
-NET uart_RX TIG;
-NET uart_TX LOC = W1;
-NET uart_TX IOSTANDARD = LVCMOS33;
-NET uart_TX TIG;
-
-NET ext_irq TIG;
-
-# Reset timing ignore - treat as async paths
-NET sys_rst TIG;
-NET opb_v20_0_OPB_Rst TIG;
-NET lmb_v10_1_OPB_Rst TIG;
-NET lmb_v10_0_OPB_Rst TIG;
-NET opb_v20_0_Debug_SYS_Rst TIG;
-NET Debug_Rst TIG;
-NET plb_v34_0_PLB_Rst TIG;
-NET dcm_locked TIG;
-
-# Locate DCM/BUFG - Tools can probably figure them out automatically
-#                   but just LOC them down to be safe
-INST dcm_0/dcm_0/DCM_ADV_INST LOC = DCM_ADV_X0Y2;
-INST dcm_1/dcm_1/DCM_ADV_INST LOC = DCM_ADV_X0Y4;
-INST dcm_2/dcm_2/DCM_ADV_INST LOC = DCM_ADV_X0Y1;
-
-INST dcm_0/dcm_0/CLK0_BUFG_INST  LOC = BUFGCTRL_X0Y0;
-INST dcm_0/dcm_0/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y1;
-INST dcm_0/dcm_0/CLKDV_BUFG_INST LOC = BUFGCTRL_X0Y2;
-
-INST dcm_1/dcm_1/CLK0_BUFG_INST  LOC = BUFGCTRL_X0Y31;
-INST dcm_1/dcm_1/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y30;
-
-////////////////////////////////////////////////////////////////////////////
-// Buttons, LEDs, and DIP Switches 
-////////////////////////////////////////////////////////////////////////////
-
-# GPLED 0-3
-NET gpio<0>  LOC = G5;  #GPLED0
-NET gpio<1>  LOC = G6;  #GPLED1
-NET gpio<2>  LOC = A11; #GPLED2
-NET gpio<3>  LOC = A12; #GPLED3
-# North-East-South-West-Center LEDs
-NET gpio<4>  LOC = C6;  # C LED
-NET gpio<5>  LOC = F9;  # W LED
-NET gpio<6>  LOC = A5;  # S LED
-NET gpio<7>  LOC = E10; # E LED
-NET gpio<8>  LOC = E2;  # N LED
-# North-East-South-West-Center Buttons
-NET gpio<9>  LOC = B6;  # C Button
-NET gpio<10> LOC = E9;  # W Button
-NET gpio<11> LOC = A6;  # S Button
-NET gpio<12> LOC = F10; # E Button
-NET gpio<13> LOC = E7;  # N Button
-# Dip Switches 1-8
-NET gpio<14> LOC = U24; # DIP SW 8
-NET gpio<15> LOC = U25; # DIP SW 7
-NET gpio<16> LOC = V23; # DIP SW 6
-NET gpio<17> LOC = U23; # DIP SW 5
-NET gpio<18> LOC = U26; # DIP SW 4
-NET gpio<19> LOC = T26; # DIP SW 3
-NET gpio<20> LOC = R19; # DIP SW 2
-NET gpio<21> LOC = R20; # DIP SW 1
-NET gpio<14> IOSTANDARD = LVCMOS33;
-NET gpio<15> IOSTANDARD = LVCMOS33;
-NET gpio<16> IOSTANDARD = LVCMOS33;
-NET gpio<17> IOSTANDARD = LVCMOS33;
-NET gpio<18> IOSTANDARD = LVCMOS33;
-NET gpio<19> IOSTANDARD = LVCMOS33;
-NET gpio<20> IOSTANDARD = LVCMOS33;
-NET gpio<21> IOSTANDARD = LVCMOS33;
-#SMA Connectors
-NET gpio<22> LOC = C12; # SMA_IN_N
-NET gpio<23> LOC = C13; # SMA_IN_P
-NET gpio<24> LOC = D7;  # SMA_OUT_N
-NET gpio<25> LOC = D8;  # SMA_OUT_P
-NET gpio<26> LOC = AD12;# USERCLK
-NET gpio<26> IOSTANDARD = LVCMOS33;
-
-NET "gpio<*>" PULLDOWN;
-NET "gpio<*>" TIG;
-NET "gpio<*>" SLEW = SLOW;
-NET "gpio<*>" DRIVE = 2;
-
-NET "gpio<22>" SLEW = FAST;
-NET "gpio<22>" DRIVE = 12;
-NET "gpio<23>" SLEW = FAST;
-NET "gpio<23>" DRIVE = 12;
-NET "gpio<24>" SLEW = FAST;
-NET "gpio<24>" DRIVE = 12;
-NET "gpio<25>" SLEW = FAST;
-NET "gpio<25>" DRIVE = 12;
-
-NET  "gpio2_d_out<*>" TIG;
-NET  "gpio2_t_out<*>" TIG;
-NET  "gpio2_in<*>" TIG;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for PS/2 Ports
-#------------------------------------------------------------------------------
-
-#Keyboard
-NET ps2_keyb_clk  LOC = D2;
-NET ps2_keyb_clk  SLEW = SLOW;
-NET ps2_keyb_clk  DRIVE = 2;
-NET ps2_keyb_clk  TIG;
-NET ps2_keyb_data LOC = G9;
-NET ps2_keyb_data SLEW = SLOW;
-NET ps2_keyb_data DRIVE = 2;
-NET ps2_keyb_data TIG;
-
-#Mouse
-NET ps2_mouse_clk  LOC = B14;
-NET ps2_mouse_clk  SLEW = SLOW;
-NET ps2_mouse_clk  DRIVE = 2;
-NET ps2_mouse_clk  TIG;
-NET ps2_mouse_data LOC = C14;
-NET ps2_mouse_data SLEW = SLOW;
-NET ps2_mouse_data DRIVE = 2;
-NET ps2_mouse_data TIG;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for IIC Controller
-#------------------------------------------------------------------------------
-
-NET iic_scl    LOC = A17;
-NET iic_sda    LOC = B17;
-NET iic_scl    SLEW = SLOW;
-NET iic_scl    DRIVE = 6;
-NET iic_scl    TIG;
-NET iic_sda    SLEW = SLOW;
-NET iic_sda    DRIVE = 6;
-NET iic_sda    TIG;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for AC97 Sound Controller
-#------------------------------------------------------------------------------
-
-NET ac97_bit_clk   LOC = AE10;
-NET ac97_bit_clk   IOSTANDARD = LVCMOS33;
-NET ac97_bit_clk   PERIOD = 80;
-NET ac97_sdata_in  LOC = AD16;
-NET ac97_sdata_in  IOSTANDARD = LVCMOS33;
-NET ac97_reset_n   LOC = AD10;
-NET ac97_reset_n   IOSTANDARD = LVCMOS33;
-NET ac97_reset_n   TIG;
-NET ac97_sdata_out LOC = C8;
-NET ac97_sync      LOC = D9;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for System ACE MPU / USB
-#------------------------------------------------------------------------------
-
-NET sysace_clk_in   LOC        = AF11;
-NET sysace_clk_in   IOSTANDARD = LVCMOS33;
-NET sysace_clk_in   TNM_NET    = "sysace_clk_in";
-# Leave 1 ns margin
-TIMESPEC "TSSYSACE" = PERIOD "sysace_clk_in" 29 ns;
-
-NET sace_usb_a<0>   LOC        = U22;
-NET sace_usb_a<1>   LOC        = Y10;
-NET sace_usb_a<2>   LOC        = AA10;
-NET sace_usb_a<3>   LOC        = AC7;
-NET sace_usb_a<4>   LOC        = Y7;
-NET sace_usb_a<5>   LOC        = AA9;
-NET sace_usb_a<6>   LOC        = Y9;
-NET sace_usb_a<*>   IOSTANDARD = LVCMOS33;
-NET sace_usb_a<*>   SLEW       = FAST;
-NET sace_usb_a<*>   DRIVE      = 8;
-NET sace_mpce       LOC        = AD5;
-NET sace_mpce       IOSTANDARD = LVCMOS33;
-NET sace_mpce       SLEW       = FAST;
-NET sace_mpce       DRIVE      = 8;
-NET sace_usb_d<0>   LOC        = AB7;
-NET sace_usb_d<1>   LOC        = AC9;
-NET sace_usb_d<2>   LOC        = AB9;
-NET sace_usb_d<3>   LOC        = AE6;
-NET sace_usb_d<4>   LOC        = AD6;
-NET sace_usb_d<5>   LOC        = AF9;
-NET sace_usb_d<6>   LOC        = AE9;
-NET sace_usb_d<7>   LOC        = AD8;
-NET sace_usb_d<8>   LOC        = AC8;
-NET sace_usb_d<9>   LOC        = AF4;
-NET sace_usb_d<10>  LOC        = AE4;
-NET sace_usb_d<11>  LOC        = AD3;
-NET sace_usb_d<12>  LOC        = AC3;
-NET sace_usb_d<13>  LOC        = AF6;
-NET sace_usb_d<14>  LOC        = AF5;
-NET sace_usb_d<15>  LOC        = AA7;
-NET sace_usb_d<*>   IOSTANDARD = LVCMOS33;
-NET sace_usb_d<*>   SLEW       = FAST;
-NET sace_usb_d<*>   DRIVE      = 8;
-NET sace_usb_d<*>   PULLDOWN;
-NET sace_usb_oen    LOC        = AA8;
-NET sace_usb_oen    IOSTANDARD = LVCMOS33;
-NET sace_usb_oen    SLEW       = FAST;
-NET sace_usb_oen    DRIVE      = 8;
-NET sace_usb_wen    LOC        = Y8;
-NET sace_usb_wen    IOSTANDARD = LVCMOS33;
-NET sace_usb_wen    SLEW       = FAST;
-NET sace_usb_wen    DRIVE      = 8;
-NET sysace_mpirq    LOC        = AD4;
-NET sysace_mpirq    IOSTANDARD = LVCMOS33;
-NET sysace_mpirq    TIG;
-NET sysace_mpirq    PULLDOWN;
-
-NET usb_csn         LOC        = AF10;
-NET usb_csn         IOSTANDARD = LVCMOS33;
-NET usb_csn         SLEW       = FAST;
-NET usb_csn         DRIVE      = 8;
-NET usb_hpi_reset_n LOC        = A7;
-NET usb_hpi_reset_n IOSTANDARD = LVCMOS25;
-NET usb_hpi_reset_n TIG;
-NET usb_hpi_int     LOC        = V5;
-NET usb_hpi_int     IOSTANDARD = LVCMOS33;
-NET usb_hpi_int     TIG;
-NET usb_hpi_int     PULLDOWN;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for DDR Controllers
-#------------------------------------------------------------------------------
-
-NET ddr_ad<0>  LOC = C26; # DDR_A0
-NET ddr_ad<1>  LOC = E17; # DDR_A1
-NET ddr_ad<2>  LOC = D18; # DDR_A2
-NET ddr_ad<3>  LOC = C19; # DDR_A3
-NET ddr_ad<4>  LOC = F17; # DDR_A4
-NET ddr_ad<5>  LOC = B18; # DDR_A5
-NET ddr_ad<6>  LOC = B20; # DDR_A6
-NET ddr_ad<7>  LOC = C20; # DDR_A7
-NET ddr_ad<8>  LOC = D20; # DDR_A8
-NET ddr_ad<9>  LOC = C21; # DDR_A9
-NET ddr_ad<10> LOC = A18; # DDR_A10
-NET ddr_ad<11> LOC = B21; # DDR_A11
-NET ddr_ad<12> LOC = A24; # DDR_A12
-NET ddr_ba<0>  LOC = B12; # DDR_BA0
-NET ddr_ba<1>  LOC = A16; # DDR_BA1
-NET ddr_casb   LOC = F23; # DDR_CAS_N
-NET ddr_cke    LOC = G22; # DDR_CKE
-NET ddr_csb    LOC = G21; # DDR_CS_N
-NET ddr_rasb   LOC = F24; # DDR_RAS_N
-NET ddr_web    LOC = A23; # DDR_WE_N
-
-NET ddr_clk    LOC = A10; # DDR_CK1_P
-NET ddr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK)
-NET ddr_clkb   LOC = B10; # DDR_CK1_N
-
-NET ddr_dm<0>  LOC = G19; # DDR_DM0
-NET ddr_dm<1>  LOC = G24; # DDR_DM1
-NET ddr_dm<2>  LOC = G20; # DDR_DM2
-NET ddr_dm<3>  LOC = C22; # DDR_DM3
-
-NET ddr_dqs<0> LOC = D25; # DDR_DQS0
-NET ddr_dqs<1> LOC = G18; # DDR_DQS1
-NET ddr_dqs<2> LOC = G17; # DDR_DQS2
-NET ddr_dqs<3> LOC = D26; # DDR_DQS3
-
-NET ddr_dq<0> LOC = H20; # DDR_D0
-NET ddr_dq<1> LOC = E23; # DDR_D1
-NET ddr_dq<2> LOC = H26; # DDR_D2
-NET ddr_dq<3> LOC = H22; # DDR_D3
-NET ddr_dq<4> LOC = E25; # DDR_D4
-NET ddr_dq<5> LOC = E26; # DDR_D5
-NET ddr_dq<6> LOC = F26; # DDR_D6
-NET ddr_dq<7> LOC = E24; # DDR_D7
-NET ddr_dq<8> LOC = E20; # DDR_D8
-NET ddr_dq<9> LOC = A22; # DDR_D9
-NET ddr_dq<10> LOC = C23; # DDR_D10
-NET ddr_dq<11> LOC = C24; # DDR_D11
-NET ddr_dq<12> LOC = A20; # DDR_D12
-NET ddr_dq<13> LOC = A21; # DDR_D13
-NET ddr_dq<14> LOC = D24; # DDR_D14
-NET ddr_dq<15> LOC = E18; # DDR_D15
-NET ddr_dq<16> LOC = F18; # DDR_D16
-NET ddr_dq<17> LOC = A19; # DDR_D17
-NET ddr_dq<18> LOC = F19; # DDR_D18
-NET ddr_dq<19> LOC = B23; # DDR_D19
-NET ddr_dq<20> LOC = E21; # DDR_D20
-NET ddr_dq<21> LOC = D22; # DDR_D21
-NET ddr_dq<22> LOC = D23; # DDR_D22
-NET ddr_dq<23> LOC = B24; # DDR_D23
-NET ddr_dq<24> LOC = E22; # DDR_D24
-NET ddr_dq<25> LOC = F20; # DDR_D25
-NET ddr_dq<26> LOC = H23; # DDR_D26
-NET ddr_dq<27> LOC = G25; # DDR_D27
-NET ddr_dq<28> LOC = G26; # DDR_D28
-NET ddr_dq<29> LOC = H25; # DDR_D29
-NET ddr_dq<30> LOC = H24; # DDR_D30
-NET ddr_dq<31> LOC = H21; # DDR_D31
-
-NET ddr_ad<*>  IOSTANDARD = SSTL2_I;
-NET ddr_ba<*>  IOSTANDARD = SSTL2_I;
-NET ddr_casb   IOSTANDARD = SSTL2_I;
-NET ddr_cke    IOSTANDARD = SSTL2_I;
-NET ddr_clk    IOSTANDARD = SSTL2_I;
-NET ddr_clk_fb IOSTANDARD = LVCMOS25;
-NET ddr_clkb   IOSTANDARD = SSTL2_I;
-NET ddr_casb   IOSTANDARD = SSTL2_I;
-NET ddr_csb    IOSTANDARD = SSTL2_I;
-NET ddr_rasb   IOSTANDARD = SSTL2_I;
-NET ddr_web    IOSTANDARD = SSTL2_I;
-
-NET ddr_dqs<*> IOSTANDARD = SSTL2_II;
-NET ddr_dm<*>  IOSTANDARD = SSTL2_II;
-NET ddr_dq<*>  IOSTANDARD = SSTL2_II;
-
-// Timing Constraint for DDR Feedback Clock
-NET "ddr_clk_fb" TNM_NET = "ddr_clk_fb";
-TIMESPEC "TSDDR_FB" = PERIOD "ddr_clk_fb" 9.9 ns;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for TFT VGA LCD Controller
-#------------------------------------------------------------------------------
-
-NET tft_lcd_b<0> LOC = L26; # VGA_B2
-NET tft_lcd_b<0> IOSTANDARD = LVCMOS33;
-NET tft_lcd_b<1> LOC = C5;  # VGA_B3
-NET tft_lcd_b<2> LOC = C7;  # VGA_B4
-NET tft_lcd_b<3> LOC = B7;  # VGA_B5
-NET tft_lcd_b<4> LOC = G8;  # VGA_B6
-NET tft_lcd_b<5> LOC = F8;  # VGA_B7
-NET tft_lcd_b<*> SLEW = FAST;
-NET tft_lcd_b<*> DRIVE = 8;
-
-NET tft_lcd_clk  LOC = AF8;
-NET tft_lcd_clk  IOSTANDARD = LVDCI_33;
-NET tft_lcd_clk  SLEW = FAST;
-NET tft_lcd_clk  DRIVE = 8;
-
-NET tft_lcd_g<0> LOC = M20; # VGA_G2
-NET tft_lcd_g<0> IOSTANDARD = LVCMOS33;
-NET tft_lcd_g<1> LOC = E4;  # VGA_G3
-NET tft_lcd_g<2> LOC = D3;  # VGA_G4
-NET tft_lcd_g<3> LOC = H7;  # VGA_G5
-NET tft_lcd_g<4> LOC = H8;  # VGA_G6
-NET tft_lcd_g<5> LOC = C1;  # VGA_G7
-NET tft_lcd_g<*> SLEW = FAST;
-NET tft_lcd_g<*> DRIVE = 8;
-
-NET tft_lcd_hsync LOC = C10;
-NET tft_lcd_hsync SLEW = FAST;
-NET tft_lcd_hsync DRIVE = 8;
-
-NET tft_lcd_r<0> LOC = N25; #VGA_R2
-NET tft_lcd_r<0> IOSTANDARD = LVCMOS33;
-NET tft_lcd_r<1> LOC = C2; #VGA_R3
-NET tft_lcd_r<2> LOC = G7; #VGA_R4
-NET tft_lcd_r<3> LOC = F7; #VGA_R5
-NET tft_lcd_r<4> LOC = E5; #VGA_R6
-NET tft_lcd_r<5> LOC = E6; #VGA_R7
-NET tft_lcd_r<*> SLEW = FAST;
-NET tft_lcd_r<*> DRIVE = 8;
-
-NET tft_lcd_vsync LOC = A8;
-NET tft_lcd_vsync SLEW = FAST;
-NET tft_lcd_vsync DRIVE = 8;
-
-TIMESPEC "TSPLB_TFT" = FROM "sys_clk" TO "tft_clk" TIG;
-TIMESPEC "TSTFT_PLB" = FROM "tft_clk" TO "sys_clk" TIG;
-
-////////////////////////////////////////////////////////////////////////////
-// Misc Board Signals
-////////////////////////////////////////////////////////////////////////////
-
-NET plb_error LOC = L24;
-NET plb_error IOSTANDARD = LVCMOS33;
-NET plb_error TIG;
-NET opb_error LOC = V6;
-NET opb_error IOSTANDARD = LVCMOS33;
-NET opb_error TIG;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for Ethernet
-#------------------------------------------------------------------------------
-
-NET phy_col        LOC = E3;
-NET phy_crs        LOC = D5;
-NET phy_dv         LOC = A9;
-NET phy_rx_clk     LOC = B15;
-NET phy_rx_data<3> LOC = C4;
-NET phy_rx_data<2> LOC = D4;
-NET phy_rx_data<1> LOC = E1;
-NET phy_rx_data<0> LOC = F1;
-
-NET phy_rx_er      LOC = B9;
-NET phy_tx_clk     LOC = C15;
-NET phy_mii_clk    LOC = D1;
-NET phy_mii_int_n  LOC = H4;
-NET phy_rst_n      LOC = D10;
-NET phy_tx_data<3> LOC = G1;
-NET phy_tx_data<2> LOC = H3;
-NET phy_tx_data<1> LOC = H2;
-NET phy_tx_data<0> LOC = H1;
-NET phy_tx_en      LOC = F4;
-NET phy_tx_er      LOC = F3;
-NET phy_mii_data   LOC = G4;
-
-NET phy_mii_int_n  PULLUP;
-
-NET phy_mii_int_n  TIG;
-NET phy_rst_n      TIG;
-
-# Timing Constraints (these are recommended in documentation and
-# are unaltered except for the TIG)
-NET "phy_rx_clk" TNM_NET = "RXCLK_GRP";
-NET "phy_tx_clk" TNM_NET = "TXCLK_GRP";
-TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns;
-TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns;
-
-NET "phy_tx_clk" MAXSKEW= 1.0 ns;
-NET "phy_rx_clk" MAXSKEW= 1.0 ns;
-NET "phy_rx_clk" PERIOD = 40 ns HIGH 14 ns;
-NET "phy_tx_clk" PERIOD = 40 ns HIGH 14 ns;
-
-NET "phy_rx_data<3>" IOBDELAY=NONE;
-NET "phy_rx_data<2>" IOBDELAY=NONE;
-NET "phy_rx_data<1>" IOBDELAY=NONE;
-NET "phy_rx_data<0>" IOBDELAY=NONE;
-NET "phy_dv" IOBDELAY=NONE;
-NET "phy_rx_er" IOBDELAY=NONE;
-NET "phy_crs" IOBDELAY=NONE;
-NET "phy_col" IOBDELAY=NONE;
-
-# Workaround to help meet "phy_rx_clk MAXSKEW= 1.0 ns" constraint
-INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I0" IOB=FALSE;
-INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I1" IOB=FALSE;
-INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I2" IOB=FALSE;
-INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I3" IOB=FALSE;
-INST "opb_ethernet_0/opb_ethernet_0/DVD_FF"   IOB=FALSE;
-INST "opb_ethernet_0/opb_ethernet_0/RER_FF"   IOB=FALSE;
-
-# Timing ignores (to specify unconstrained paths)
-TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "sys_clk" TIG;
-TIMESPEC "TS_OPB_PHYTX" = FROM "sys_clk" TO "TXCLK_GRP" TIG;
-TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "sys_clk" TIG;
-TIMESPEC "TS_OPB_PHYRX" = FROM "sys_clk" TO "RXCLK_GRP" TIG;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for SRAM/FLASH
-#------------------------------------------------------------------------------
-
-NET sram_clk            LOC = AF7;
-NET sram_clk_fb         LOC = AD17;
-NET flash_a23           LOC = T21;
-NET sram_flash_addr<22> LOC = U20;
-NET sram_flash_addr<21> LOC = T19;
-NET sram_flash_addr<20> LOC = AC5;
-NET sram_flash_addr<19> LOC = AB5;
-NET sram_flash_addr<18> LOC = AC4;
-NET sram_flash_addr<17> LOC = AB4;
-
-NET sram_flash_addr<16> LOC = AB3;
-NET sram_flash_addr<15> LOC = AA4;
-NET sram_flash_addr<14> LOC = AA3;
-NET sram_flash_addr<13> LOC = W5;
-NET sram_flash_addr<12> LOC = W6;
-NET sram_flash_addr<11> LOC = W3;
-NET sram_flash_addr<10> LOC = AF3;
-NET sram_flash_addr<9>  LOC = AE3;
-NET sram_flash_addr<8>  LOC = AD2;
-NET sram_flash_addr<7>  LOC = AD1;
-NET sram_flash_addr<6>  LOC = AC2;
-NET sram_flash_addr<5>  LOC = AC1;
-NET sram_flash_addr<4>  LOC = AB2;
-NET sram_flash_addr<3>  LOC = AB1;
-NET sram_flash_addr<2>  LOC = AA1;
-NET sram_flash_addr<1>  LOC = Y2;
-NET sram_flash_addr<0>  LOC = Y1;
-NET sram_flash_data<31> LOC = F14;
-NET sram_flash_data<30> LOC = F13;
-NET sram_flash_data<29> LOC = F12;
-NET sram_flash_data<28> LOC = F11;
-NET sram_flash_data<27> LOC = F16;
-NET sram_flash_data<26> LOC = F15;
-NET sram_flash_data<25> LOC = D14;
-NET sram_flash_data<24> LOC = D13;
-NET sram_flash_data<23> LOC = D15;
-NET sram_flash_data<22> LOC = E14;
-NET sram_flash_data<21> LOC = C11;
-NET sram_flash_data<20> LOC = D11;
-NET sram_flash_data<19> LOC = D16;
-NET sram_flash_data<18> LOC = C16;
-NET sram_flash_data<17> LOC = E13;
-NET sram_flash_data<16> LOC = D12;
-NET sram_flash_data<15> LOC = AA14;
-NET sram_flash_data<14> LOC = AB14;
-NET sram_flash_data<13> LOC = AC12;
-NET sram_flash_data<12> LOC = AC11;
-NET sram_flash_data<11> LOC = AA16;
-NET sram_flash_data<10> LOC = AA15;
-NET sram_flash_data<9>  LOC = AB13;
-NET sram_flash_data<8>  LOC = AA13;
-NET sram_flash_data<7>  LOC = AC14;
-NET sram_flash_data<6>  LOC = AD14;
-NET sram_flash_data<5>  LOC = AA12;
-NET sram_flash_data<4>  LOC = AA11;
-NET sram_flash_data<3>  LOC = AC16;
-NET sram_flash_data<2>  LOC = AC15;
-NET sram_flash_data<1>  LOC = AC13;
-NET sram_flash_data<0>  LOC = AD13;
-NET sram_cen            LOC = V7;
-NET sram_flash_oe_n     LOC = AC6;
-NET sram_flash_we_n     LOC = AB6;
-NET sram_bw<3>          LOC = Y3; #Y4; 
-NET sram_bw<2>          LOC = Y4; #Y3;
-NET sram_bw<1>          LOC = Y5; #Y6;
-NET sram_bw<0>          LOC = Y6; #Y5;
-NET flash_ce            LOC = W7;
-NET sram_adv_ld_n       LOC = W4;
-NET sram_mode           LOC = V26;
-
-NET sram_clk           IOSTANDARD = LVCMOS33;
-NET sram_clk           DRIVE = 16;
-NET sram_clk           SLEW = FAST;
-NET sram_clk_fb        IOSTANDARD = LVCMOS33;
-
-NET flash_a23          IOSTANDARD = LVDCI_33;
-NET flash_a23  SLEW = FAST;
-NET flash_a23  DRIVE = 8;
-
-NET sram_mode          IOSTANDARD = LVDCI_33;
-NET sram_mode SLEW = FAST;
-NET sram_mode DRIVE = 8;
-
-NET sram_flash_addr<*> IOSTANDARD = LVDCI_33;
-NET sram_flash_addr<*>  SLEW = FAST;
-NET sram_flash_addr<*>  DRIVE = 8;
-
-NET sram_flash_data<*> IOSTANDARD = LVCMOS33;
-NET sram_flash_data<*> DRIVE = 12;
-NET sram_flash_data<*> SLEW = FAST;
-NET sram_flash_data<*> PULLDOWN;
-
-NET sram_flash_oe_n    IOSTANDARD = LVDCI_33;
-NET sram_flash_oe_n SLEW = FAST;
-NET sram_flash_oe_n DRIVE = 8;
-
-NET sram_flash_we_n    IOSTANDARD = LVDCI_33;
-NET sram_flash_we_n SLEW = FAST;
-NET sram_flash_we_n DRIVE = 8;
-
-NET sram_bw<*>         IOSTANDARD = LVDCI_33;
-NET sram_bw<*> SLEW = FAST;
-NET sram_bw<*> DRIVE = 8;
-
-NET flash_ce           IOSTANDARD = LVDCI_33;
-NET flash_ce SLEW = FAST;
-NET flash_ce DRIVE = 8;
-
-NET sram_cen           IOSTANDARD = LVDCI_33;
-NET sram_cen SLEW = FAST;
-NET sram_cen DRIVE = 8;
-
-NET sram_adv_ld_n      IOSTANDARD = LVDCI_33;
-NET sram_adv_ld_n SLEW = FAST;
-NET sram_adv_ld_n DRIVE = 8;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for Expansion Header GPIO
-#------------------------------------------------------------------------------
-
-NET gpio_exp_hdr1<31> LOC = AF24; # HDR1_64
-NET gpio_exp_hdr1<30> LOC = AE24; # HDR1_62
-NET gpio_exp_hdr1<29> LOC = AD22; # HDR1_8
-NET gpio_exp_hdr1<28> LOC = AB21; # HDR1_58
-NET gpio_exp_hdr1<27> LOC = W20;  # HDR1_44
-NET gpio_exp_hdr1<26> LOC = W21;  # HDR1_48
-NET gpio_exp_hdr1<25> LOC = AB22; # HDR1_14
-NET gpio_exp_hdr1<24> LOC = AD25; # HDR1_20
-NET gpio_exp_hdr1<23> LOC = W22;  # HDR1_46
-NET gpio_exp_hdr1<22> LOC = V21;  # HDR1_56
-NET gpio_exp_hdr1<21> LOC = V22;  # HDR1_54
-NET gpio_exp_hdr1<20> LOC = AC22; # HDR1_16
-NET gpio_exp_hdr1<19> LOC = AD26; # HDR1_18
-NET gpio_exp_hdr1<18> LOC = AC26; # HDR1_34
-NET gpio_exp_hdr1<17> LOC = AD23; # HDR1_6
-NET gpio_exp_hdr1<16> LOC = AB25; # HDR1_30
-NET gpio_exp_hdr1<15> LOC = AC23; # HDR1_4
-NET gpio_exp_hdr1<14> LOC = AB26; # HDR1_24
-NET gpio_exp_hdr1<13> LOC = AC21; # HDR1_60
-NET gpio_exp_hdr1<12> LOC = AA23; # HDR1_10
-NET gpio_exp_hdr1<11> LOC = AA26; # HDR1_22
-NET gpio_exp_hdr1<10> LOC = Y25;  # HDR1_40
-NET gpio_exp_hdr1<9>  LOC = Y26;  # HDR1_38
-NET gpio_exp_hdr1<8>  LOC = W26;  # HDR1_50
-NET gpio_exp_hdr1<7>  LOC = AB23; # HDR1_12
-NET gpio_exp_hdr1<6>  LOC = Y24;  # HDR1_26
-NET gpio_exp_hdr1<5>  LOC = AB24; # HDR1_32
-NET gpio_exp_hdr1<4>  LOC = W25;  # HDR1_52
-NET gpio_exp_hdr1<3>  LOC = AC24; # HDR1_2
-NET gpio_exp_hdr1<2>  LOC = AC25; # HDR1_36
-NET gpio_exp_hdr1<1>  LOC = V20;  # HDR1_42
-NET gpio_exp_hdr1<0>  LOC = AA24; # HDR1_28
-NET gpio_exp_hdr1<*> TIG;
-NET gpio_exp_hdr1<*> PULLDOWN;
-
-NET gpio_exp_hdr2<31> LOC = AF18; # HDR2_40
-NET gpio_exp_hdr2<30> LOC = AE18; # HDR2_38
-NET gpio_exp_hdr2<29> LOC = AF19; # HDR2_32
-NET gpio_exp_hdr2<28> LOC = AF20; # HDR2_30
-NET gpio_exp_hdr2<27> LOC = AF21; # HDR2_44
-NET gpio_exp_hdr2<26> LOC = AF22; # HDR2_42
-NET gpio_exp_hdr2<25> LOC = AF23; # HDR2_24
-NET gpio_exp_hdr2<24> LOC = AE23; # HDR2_22
-NET gpio_exp_hdr2<23> LOC = AC18; # HDR2_48
-NET gpio_exp_hdr2<22> LOC = AB18; # HDR2_46
-NET gpio_exp_hdr2<21> LOC = AD19; # HDR2_64
-NET gpio_exp_hdr2<20> LOC = AC19; # HDR2_62
-NET gpio_exp_hdr2<19> LOC = AE20; # HDR2_16
-NET gpio_exp_hdr2<18> LOC = AD20; # HDR2_14
-NET gpio_exp_hdr2<17> LOC = AE21; # HDR2_36
-NET gpio_exp_hdr2<16> LOC = AD21; # HDR2_34
-NET gpio_exp_hdr2<15> LOC = AB20; # HDR2_52
-NET gpio_exp_hdr2<14> LOC = AC20; # HDR2_50
-NET gpio_exp_hdr2<13> LOC = Y17;  # HDR2_56
-NET gpio_exp_hdr2<12> LOC = AA17; # HDR2_54
-NET gpio_exp_hdr2<11> LOC = AA19; # HDR2_60
-NET gpio_exp_hdr2<10> LOC = AA20; # HDR2_58
-NET gpio_exp_hdr2<9>  LOC = Y22;  # HDR2_8
-NET gpio_exp_hdr2<8>  LOC = Y23;  # HDR2_6
-NET gpio_exp_hdr2<7>  LOC = W23;  # HDR2_12
-NET gpio_exp_hdr2<6>  LOC = W24;  # HDR2_10
-NET gpio_exp_hdr2<5>  LOC = Y20;  # HDR2_20
-NET gpio_exp_hdr2<4>  LOC = Y21;  # HDR2_18
-NET gpio_exp_hdr2<3>  LOC = Y19;  # HDR2_28
-NET gpio_exp_hdr2<2>  LOC = W19;  # HDR2_26
-NET gpio_exp_hdr2<1>  LOC = AA18; # HDR2_4
-NET gpio_exp_hdr2<0>  LOC = Y18;  # HDR2_2
-NET gpio_exp_hdr2<*> TIG;
-NET gpio_exp_hdr2<*> PULLDOWN;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for Character LCD GPIO
-#------------------------------------------------------------------------------
-
-NET gpio_char_lcd<6> LOC = AE13; # LCD_E
-NET gpio_char_lcd<5> LOC = AC17; # LCD_RS
-NET gpio_char_lcd<4> LOC = AB17; # LCD_RW
-NET gpio_char_lcd<3> LOC = AF12; # LCD_DB7
-NET gpio_char_lcd<2> LOC = AE12; # LCD_DB6
-NET gpio_char_lcd<1> LOC = AC10; # LCD_DB5
-NET gpio_char_lcd<0> LOC = AB10; # LCD_DB4
-NET gpio_char_lcd<*> IOSTANDARD = LVCMOS33;
-NET gpio_char_lcd<*> TIG;
-NET gpio_char_lcd<*> PULLDOWN;
diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.prj b/projects/mips_sys/ise101/mips_sys/mips_sys.prj
deleted file mode 100644
index ce7b8ab..0000000
--- a/projects/mips_sys/ise101/mips_sys/mips_sys.prj
+++ /dev/null
@@ -1,45 +0,0 @@
-vhdl work "../../src/sdram_config.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/vga_types.vhd"
-vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/vga_sync.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
-vhdl work "../../../../lib/misc/utils_pkg.vhd"
-vhdl work "../../../../lib/misc/singleshot.vhd"
-vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
-vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
-vhdl work "../../../../lib/FIFO/src/fifo_sync_ctrl.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
-vhdl work "../../../../lib/uart/kcuart_tx.vhd"
-vhdl work "../../../../lib/uart/kcuart_rx.vhd"
-vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
-vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
-vhdl work "../../../../lib/FIFO/src/fifo_async_ctrl.vhd"
-vhdl work "../../../../lib/ac97_ctrl/src/core/ac_out.vhd"
-vhdl work "../../../../lib/ac97_ctrl/src/core/ac_in.vhd"
-vhdl work "../../src/bootloader.ROM_ld.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd"
-vhdl work "../../../../lib/uart/uart_tx.vhd"
-vhdl work "../../../../lib/uart/uart_rx.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
-vhdl work "../../../../lib/misc/async_types.vhd"
-vhdl work "../../../../lib/FIFO/src/fifo_async.vhd"
-vhdl work "../../../../lib/ac97_ctrl/src/core/ac_io.vhd"
-vhdl work "../../src/async_defs.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
-vhdl work "../../../../lib/uart/uart_wb.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
-vhdl work "../../../../lib/misc/rom_wb.vhd"
-vhdl work "../../../../lib/misc/lcd_port.vhd"
-vhdl work "../../../../lib/misc/gpio_wb.vhd"
-vhdl work "../../../../lib/misc/clockgen_virtex4.vhd"
-vhdl work "../../../../lib/misc/async_port_wb.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
-vhdl work "../../../../lib/ac97_ctrl/src/core/ac97_wb.vhd"
-vhdl work "../../src/mips_sys.vhd"
diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj b/projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj
deleted file mode 100644
index b62311a..0000000
--- a/projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj
+++ /dev/null
@@ -1,45 +0,0 @@
-vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_types.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_sync.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd"
-vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
-vhdl work "W:\vhdl\lib\misc\singleshot.vhd"
-vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_timing.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\fonts\char_rom_fixedsys_8x16.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\clkgen_virtex4.vhd"
-vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
-vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
-vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_async_ctrl.vhd"
-vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_out.vhd"
-vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_in.vhd"
-vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd"
-vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
-vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
-vhdl work "W:\vhdl\lib\misc\async_types.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
-vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_io.vhd"
-vhdl work "W:\vhdl\projects\mips_sys\src\async_defs.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend64.vhd"
-vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd"
-vhdl work "W:\vhdl\lib\misc\rom_wb.vhd"
-vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
-vhdl work "W:\vhdl\lib\misc\gpio_wb.vhd"
-vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd"
-vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
-vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac97_wb.vhd"
-vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd"
diff --git a/projects/mips_sys/ise101/mips_sys/ucf/systest.ssram.ucf b/projects/mips_sys/ise101/mips_sys/ucf/systest.ssram.ucf
deleted file mode 100644
index f8198e9..0000000
--- a/projects/mips_sys/ise101/mips_sys/ucf/systest.ssram.ucf
+++ /dev/null
@@ -1,503 +0,0 @@
-#
-#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
-#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
-#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
-#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
-#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
-#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-#     FOR A PARTICULAR PURPOSE.
-#
-#     (c) Copyright 2005 Xilinx, Inc.
-#     All rights reserved.
-#
-
-CONFIG STEPPING = "ES";
-
-# Bus clock nets
-NET "clk" TNM_NET = "clk";
-TIMESPEC "TS_clk" = PERIOD "clk" 9.95 ns HIGH 50 %;
-
-NET "inst_vga_frontend/inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk";
-#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
-TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG;
-
-NET "sys_clk_in" LOC = "AE14";
-NET sys_clk_in IOSTANDARD = LVCMOS33;
-NET "sys_rst_n_in" LOC = "D6";
-NET sys_rst_n_in PULLUP;
-NET "sys_rst_n_in" TIG;
-NET "rst" TIG;
-
-# Locate DCM/BUFG - Tools can probably figure them out automatically
-#                   but just LOC them down to be safe
-#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2;
-#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1;
-
-////////////////////////////////////////////////////////////////////////////
-// Misc Board Signals
-////////////////////////////////////////////////////////////////////////////
-
-NET sys_error<0> LOC = V6;
-NET sys_error<1> LOC = L24;
-NET sys_error<*> IOSTANDARD = LVCMOS33;
-NET sys_error<*> DRIVE = 2;
-NET sys_error<*> TIG;
-
-////////////////////////////////////////////////////////////////////////////
-// RS-232
-////////////////////////////////////////////////////////////////////////////
-NET sys_rx LOC = W2;
-NET sys_rx IOSTANDARD = LVCMOS33;
-NET sys_rx TIG;
-NET "sys_tx" LOC = "W1";
-NET sys_tx IOSTANDARD = LVCMOS33;
-NET "sys_tx" TIG;
-
-////////////////////////////////////////////////////////////////////////////
-// Buttons, LEDs, and DIP Switches
-////////////////////////////////////////////////////////////////////////////
-# GPLED 0-3
-NET "sys_led<0>" LOC = "G5"; #GPLED0
-NET "sys_led<1>" LOC = "G6"; #GPLED1
-NET "sys_led<2>" LOC = "A11"; #GPLED2
-NET "sys_led<3>" LOC = "A12"; #GPLED3
-# North-East-South-West-Center LEDs
-NET "sys_led<4>" LOC = "F9"; # W LED
-NET "sys_led<5>" LOC = "E2"; # N LED
-NET "sys_led<6>" LOC = "E10"; # E LED
-NET "sys_led<7>" LOC = "A5"; # S LED
-NET "sys_led<8>" LOC = "C6"; # C LED
-NET "sys_led<*>" TIG;
-NET "sys_led<*>" SLEW = SLOW;
-NET "sys_led<*>" DRIVE = 2;
-#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
-# North-East-South-West-Center Buttons
-NET "sys_btn<0>" LOC = "E9"; # W Button
-NET "sys_btn<1>" LOC = "E7"; # N Button
-NET "sys_btn<2>" LOC = "F10"; # E Button
-NET "sys_btn<3>" LOC = "A6"; # S Button
-NET "sys_btn<4>" LOC = "B6"; # C Button
-NET "sys_btn<*>" TIG;
-NET "sys_btn<*>" PULLDOWN;
-#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
-# Dip Switches 1-8
-NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
-NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
-NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
-NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
-NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
-NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
-NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
-NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
-NET "sys_dip<*>" PULLDOWN;
-NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
-NET "sys_dip<*>" TIG;
-////////////////////////////////////////////////////////////////////////////
-// LCD
-////////////////////////////////////////////////////////////////////////////
-NET sys_lcd_e LOC = AE13; # LCD_E
-NET sys_lcd_e IOSTANDARD = LVCMOS33;
-NET sys_lcd_e SLEW = SLOW;
-NET sys_lcd_e DRIVE = 2;
-NET sys_lcd_e TIG;
-NET sys_lcd_rs LOC = AC17; # LCD_RS
-NET sys_lcd_rs IOSTANDARD = LVCMOS33;
-NET sys_lcd_rs SLEW = SLOW;
-NET sys_lcd_rs DRIVE = 2;
-NET sys_lcd_rs TIG;
-NET sys_lcd_rw LOC = AB17; # LCD_RW
-NET sys_lcd_rw IOSTANDARD = LVCMOS33;
-NET sys_lcd_rw SLEW = SLOW;
-NET sys_lcd_rw DRIVE = 2;
-NET sys_lcd_rw TIG;
-NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
-NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
-NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
-NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
-NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
-NET sys_lcd_d<*> SLEW = SLOW;
-NET sys_lcd_d<*> DRIVE = 2;
-NET sys_lcd_d<*> PULLDOWN;
-NET sys_lcd_d<*> TIG;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for DDR Controllers
-#------------------------------------------------------------------------------
-
-NET sys_sdr_a_q<0>  	LOC = C26; # DDR_A0
-NET sys_sdr_a_q<1>  	LOC = E17; # DDR_A1
-NET sys_sdr_a_q<2>  	LOC = D18; # DDR_A2
-NET sys_sdr_a_q<3>  	LOC = C19; # DDR_A3
-NET sys_sdr_a_q<4>  	LOC = F17; # DDR_A4
-NET sys_sdr_a_q<5>  	LOC = B18; # DDR_A5
-NET sys_sdr_a_q<6>  	LOC = B20; # DDR_A6
-NET sys_sdr_a_q<7>  	LOC = C20; # DDR_A7
-NET sys_sdr_a_q<8>  	LOC = D20; # DDR_A8
-NET sys_sdr_a_q<9>  	LOC = C21; # DDR_A9
-NET sys_sdr_a_q<10> 	LOC = A18; # DDR_A10
-NET sys_sdr_a_q<11> 	LOC = B21; # DDR_A11
-NET sys_sdr_a_q<12> 	LOC = A24; # DDR_A12
-NET sys_sdr_ba_q<0>  	LOC = B12; # DDR_BA0
-NET sys_sdr_ba_q<1>  	LOC = A16; # DDR_BA1
-NET sys_sdr_cas_qn		LOC = F23; # DDR_CAS_N
-NET sys_sdr_cke_q		LOC = G22; # DDR_CKE
-NET sys_sdr_cs_qn		LOC = G21; # DDR_CS_N
-NET sys_sdr_ras_qn		LOC = F24; # DDR_RAS_N
-NET sys_sdr_we_qn		LOC = A23; # DDR_WE_N
-
-NET sys_sdr_clk_p		LOC = A10; # DDR_CK1_P
-NET sys_sdr_clk_fb	LOC = B13; # DDR_CK1_P (FEEDBACK)
-NET sys_sdr_clk_n		LOC = B10; # DDR_CK1_N
-
-NET sys_sdr_dm_q<0>  	LOC = G19; # DDR_DM0
-NET sys_sdr_dm_q<1>  	LOC = G24; # DDR_DM1
-NET sys_sdr_dm_q<2>  	LOC = G20; # DDR_DM2
-NET sys_sdr_dm_q<3>  	LOC = C22; # DDR_DM3
-
-NET sys_sdr_dqs_q<0> 	LOC = D25; # DDR_DQS0
-NET sys_sdr_dqs_q<1> 	LOC = G18; # DDR_DQS1
-NET sys_sdr_dqs_q<2> 	LOC = G17; # DDR_DQS2
-NET sys_sdr_dqs_q<3> 	LOC = D26; # DDR_DQS3
-
-NET sys_sdr_data<0> 	LOC = H20; # DDR_D0
-NET sys_sdr_data<1> 	LOC = E23; # DDR_D1
-NET sys_sdr_data<2> 	LOC = H26; # DDR_D2
-NET sys_sdr_data<3> 	LOC = H22; # DDR_D3
-NET sys_sdr_data<4> 	LOC = E25; # DDR_D4
-NET sys_sdr_data<5> 	LOC = E26; # DDR_D5
-NET sys_sdr_data<6> 	LOC = F26; # DDR_D6
-NET sys_sdr_data<7> 	LOC = E24; # DDR_D7
-NET sys_sdr_data<8> 	LOC = E20; # DDR_D8
-NET sys_sdr_data<9> 	LOC = A22; # DDR_D9
-NET sys_sdr_data<10>	LOC = C23; # DDR_D10
-NET sys_sdr_data<11>	LOC = C24; # DDR_D11
-NET sys_sdr_data<12>	LOC = A20; # DDR_D12
-NET sys_sdr_data<13>	LOC = A21; # DDR_D13
-NET sys_sdr_data<14>	LOC = D24; # DDR_D14
-NET sys_sdr_data<15>	LOC = E18; # DDR_D15
-NET sys_sdr_data<16>	LOC = F18; # DDR_D16
-NET sys_sdr_data<17>	LOC = A19; # DDR_D17
-NET sys_sdr_data<18>	LOC = F19; # DDR_D18
-NET sys_sdr_data<19>	LOC = B23; # DDR_D19
-NET sys_sdr_data<20>	LOC = E21; # DDR_D20
-NET sys_sdr_data<21>	LOC = D22; # DDR_D21
-NET sys_sdr_data<22>	LOC = D23; # DDR_D22
-NET sys_sdr_data<23>	LOC = B24; # DDR_D23
-NET sys_sdr_data<24>	LOC = E22; # DDR_D24
-NET sys_sdr_data<25>	LOC = F20; # DDR_D25
-NET sys_sdr_data<26>	LOC = H23; # DDR_D26
-NET sys_sdr_data<27>	LOC = G25; # DDR_D27
-NET sys_sdr_data<28>	LOC = G26; # DDR_D28
-NET sys_sdr_data<29>	LOC = H25; # DDR_D29
-NET sys_sdr_data<30>	LOC = H24; # DDR_D30
-NET sys_sdr_data<31>	LOC = H21; # DDR_D31
-
-NET sys_sdr_a_q<*>  	IOSTANDARD = SSTL2_I;
-NET sys_sdr_a_q<*>	FAST; 
-
-NET sys_sdr_ba_q<*> 	IOSTANDARD = SSTL2_I;
-NET sys_sdr_ba_q<*>	FAST; 
-
-NET sys_sdr_cas_qn  	IOSTANDARD = SSTL2_I;
-NET sys_sdr_cas_qn	FAST; 
-
-NET sys_sdr_cke_q   	IOSTANDARD = SSTL2_I;
-NET sys_sdr_cke_q		FAST; 
-
-NET sys_sdr_clk_p		IOSTANDARD = SSTL2_I;
-NET sys_sdr_clk_p		FAST; 
-NET sys_sdr_clk_fb	IOSTANDARD = LVCMOS25;
-NET sys_sdr_clk_fb	IOBDELAY = NONE; 
-NET sys_sdr_clk_n		IOSTANDARD = SSTL2_I;
-NET sys_sdr_clk_n		FAST; 
-
-NET sys_sdr_cas_qn	IOSTANDARD = SSTL2_I;
-NET sys_sdr_cas_qn	FAST; 
-
-NET sys_sdr_cs_qn		IOSTANDARD = SSTL2_I;
-NET sys_sdr_cs_qn		FAST; 
-
-NET sys_sdr_ras_qn	IOSTANDARD = SSTL2_I;
-NET sys_sdr_ras_qn	FAST; 
-
-NET sys_sdr_we_qn		IOSTANDARD = SSTL2_I;
-NET sys_sdr_we_qn		FAST; 
-
-NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
-NET sys_sdr_dqs_q<*>	IOBDELAY = NONE; 
-NET sys_sdr_dqs_q<*>	FAST; 
-
-NET sys_sdr_dm_q<*>  IOSTANDARD = SSTL2_II;
-NET sys_sdr_dm_q<*>	IOBDELAY = NONE; 
-NET sys_sdr_dm_q<*>	FAST; 
-
-NET sys_sdr_data<*>  IOSTANDARD = SSTL2_II;
-NET sys_sdr_data<*>	IOBDELAY = NONE; 
-NET sys_sdr_data<*>	FAST; 
-
-#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
-
-NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p";
-NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n";
-
-# Timing Constraint for DDR Feedback Clock
-NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
-
-# USB
-NET sys_usb_a<0>   LOC        = Y10;
-NET sys_usb_a<1>   LOC        = AA10;
-NET sys_usb_a<*>   IOSTANDARD = LVCMOS33;
-
-NET sys_usb_d<0>   LOC        = AB7;
-NET sys_usb_d<1>   LOC        = AC9;
-NET sys_usb_d<2>   LOC        = AB9;
-NET sys_usb_d<3>   LOC        = AE6;
-NET sys_usb_d<4>   LOC        = AD6;
-NET sys_usb_d<5>   LOC        = AF9;
-NET sys_usb_d<6>   LOC        = AE9;
-NET sys_usb_d<7>   LOC        = AD8;
-NET sys_usb_d<8>   LOC        = AC8;
-NET sys_usb_d<9>   LOC        = AF4;
-NET sys_usb_d<10>  LOC        = AE4;
-NET sys_usb_d<11>  LOC        = AD3;
-NET sys_usb_d<12>  LOC        = AC3;
-NET sys_usb_d<13>  LOC        = AF6;
-NET sys_usb_d<14>  LOC        = AF5;
-NET sys_usb_d<15>  LOC        = AA7;
-NET sys_usb_d<*>   IOSTANDARD = LVCMOS33;
-NET sys_usb_d<*>   SLEW       = FAST;
-NET sys_usb_d<*>   DRIVE      = 8;
-NET sys_usb_d<*>   PULLDOWN;
-
-NET sys_usb_rdn    LOC        = AA8;
-NET sys_usb_rdn    IOSTANDARD = LVCMOS33;
-NET sys_usb_rdn    SLEW       = FAST;
-NET sys_usb_rdn    DRIVE      = 8;
-
-NET sys_usb_wrn    LOC        = Y8;
-NET sys_usb_wrn    IOSTANDARD = LVCMOS33;
-NET sys_usb_wrn    SLEW       = FAST;
-NET sys_usb_wrn    DRIVE      = 8;
-
-NET sys_usb_csn    LOC        = AF10;
-NET sys_usb_csn    IOSTANDARD = LVCMOS33;
-NET sys_usb_csn    SLEW       = FAST;
-NET sys_usb_csn    DRIVE      = 8;
-
-NET sys_usb_rstn   LOC        = A7;
-NET sys_usb_rstn   IOSTANDARD = LVCMOS25;
-NET sys_usb_rstn   TIG;
-
-NET sys_usb_int    LOC        = V5;
-NET sys_usb_int    IOSTANDARD = LVCMOS33;
-NET sys_usb_int    PULLDOWN;
-NET sys_usb_int    TIG;
-
-# FLASH
-NET sys_flash_ssram_a<24> LOC = T21;
-NET sys_flash_ssram_a<23> LOC = U20;
-NET sys_flash_ssram_a<22> LOC = T19;
-NET sys_flash_ssram_a<21> LOC = AC5;
-NET sys_flash_ssram_a<20> LOC = AB5;
-NET sys_flash_ssram_a<19> LOC = AC4;
-NET sys_flash_ssram_a<18> LOC = AB4;
-NET sys_flash_ssram_a<17> LOC = AB3;
-NET sys_flash_ssram_a<16> LOC = AA4;
-NET sys_flash_ssram_a<15> LOC = AA3;
-NET sys_flash_ssram_a<14> LOC = W5;
-NET sys_flash_ssram_a<13> LOC = W6;
-NET sys_flash_ssram_a<12> LOC = W3;
-NET sys_flash_ssram_a<11> LOC = AF3;
-NET sys_flash_ssram_a<10>  LOC = AE3;
-NET sys_flash_ssram_a<9>  LOC = AD2;
-NET sys_flash_ssram_a<8>  LOC = AD1;
-NET sys_flash_ssram_a<7>  LOC = AC2;
-NET sys_flash_ssram_a<6>  LOC = AC1;
-NET sys_flash_ssram_a<5>  LOC = AB2;
-NET sys_flash_ssram_a<4>  LOC = AB1;
-NET sys_flash_ssram_a<3>  LOC = AA1;
-NET sys_flash_ssram_a<2>  LOC = Y2;
-NET sys_flash_ssram_a<1>  LOC = Y1;
-NET sys_flash_ssram_a<0>  LOC = T20;
-NET sys_flash_ssram_a<*> IOSTANDARD = LVDCI_33;
-NET sys_flash_ssram_a<*>  SLEW = FAST;
-NET sys_flash_ssram_a<*>  DRIVE = 8;
-
-
-NET sys_flash_ssram_d<31> LOC = F14;
-NET sys_flash_ssram_d<30> LOC = F13;
-NET sys_flash_ssram_d<29> LOC = F12;
-NET sys_flash_ssram_d<28> LOC = F11;
-NET sys_flash_ssram_d<27> LOC = F16;
-NET sys_flash_ssram_d<26> LOC = F15;
-NET sys_flash_ssram_d<25> LOC = D14;
-NET sys_flash_ssram_d<24> LOC = D13;
-NET sys_flash_ssram_d<23> LOC = D15;
-NET sys_flash_ssram_d<22> LOC = E14;
-NET sys_flash_ssram_d<21> LOC = C11;
-NET sys_flash_ssram_d<20> LOC = D11;
-NET sys_flash_ssram_d<19> LOC = D16;
-NET sys_flash_ssram_d<18> LOC = C16;
-NET sys_flash_ssram_d<17> LOC = E13;
-NET sys_flash_ssram_d<16> LOC = D12;
-NET sys_flash_ssram_d<15> LOC = AA14;
-NET sys_flash_ssram_d<14> LOC = AB14;
-NET sys_flash_ssram_d<13> LOC = AC12;
-NET sys_flash_ssram_d<12> LOC = AC11;
-NET sys_flash_ssram_d<11> LOC = AA16;
-NET sys_flash_ssram_d<10> LOC = AA15;
-NET sys_flash_ssram_d<9>  LOC = AB13;
-NET sys_flash_ssram_d<8>  LOC = AA13;
-NET sys_flash_ssram_d<7>  LOC = AC14;
-NET sys_flash_ssram_d<6>  LOC = AD14;
-NET sys_flash_ssram_d<5>  LOC = AA12;
-NET sys_flash_ssram_d<4>  LOC = AA11;
-NET sys_flash_ssram_d<3>  LOC = AC16;
-NET sys_flash_ssram_d<2>  LOC = AC15;
-NET sys_flash_ssram_d<1>  LOC = AC13;
-NET sys_flash_ssram_d<0>  LOC = AD13;
-NET sys_flash_ssram_d<*> IOSTANDARD = LVCMOS33;
-NET sys_flash_ssram_d<*> DRIVE = 12;
-NET sys_flash_ssram_d<*> SLEW = FAST;
-NET sys_flash_ssram_d<*> PULLDOWN;
-
-NET sys_flash_ssram_oe_n     LOC = AC6;
-NET sys_flash_ssram_oe_n    IOSTANDARD = LVDCI_33;
-NET sys_flash_ssram_oe_n SLEW = FAST;
-NET sys_flash_ssram_oe_n DRIVE = 8;
-
-NET sys_flash_ssram_we_n     LOC = AB6;
-NET sys_flash_ssram_we_n    IOSTANDARD = LVDCI_33;
-NET sys_flash_ssram_we_n SLEW = FAST;
-NET sys_flash_ssram_we_n DRIVE = 8;
-
-NET sys_flash_ce      LOC = W7;
-NET sys_flash_ce           IOSTANDARD = LVDCI_33;
-NET sys_flash_ce SLEW = FAST;
-NET sys_flash_ce DRIVE = 8;
-
-NET sys_flash_rstn    LOC = AD10;
-NET sys_flash_rstn    IOSTANDARD = LVCMOS33;
-NET sys_flash_rstn    DRIVE = 8;
-NET sys_flash_rstn    SLEW = FAST;
-NET sys_flash_rstn           TIG;
-
-NET sys_flash_byten   LOC = N22;
-NET sys_flash_byten          IOSTANDARD = LVCMOS33;
-NET sys_flash_byten          DRIVE = 8;
-NET sys_flash_byten          SLEW = FAST;
-NET sys_flash_byten          TIG;
-
-# SSRAM
-NET sys_ssram_clk            LOC = AF7;
-NET sys_ssram_clk            IOSTANDARD = LVCMOS33;
-NET sys_ssram_clk            DRIVE = 16;
-NET sys_ssram_clk            SLEW = FAST;
-
-NET "sys_ssram_clk" TNM_NET = "ssram_clk";
-#TIMESPEC "TS_ssram_clk" = PERIOD "ssram_clk" 9.95 ns HIGH 50 %;
-
-
-NET sys_ssram_clk_fb         LOC = AD17;
-NET sys_ssram_clk_fb         IOSTANDARD = LVCMOS33;
-
-# Timing Constraint for Feedback Clock
-NET sys_ssram_clk_fb FEEDBACK = 1 ns NET sys_ssram_clk;
-
-NET sys_ssram_ce_n           LOC = V7;
-NET sys_ssram_ce_n           IOSTANDARD = LVDCI_33;
-NET sys_ssram_ce_n           SLEW = FAST;
-NET sys_ssram_ce_n           DRIVE = 8;
-
-NET sys_ssram_bw_n<3>        LOC = Y3; #Y4; 
-NET sys_ssram_bw_n<2>        LOC = Y4; #Y3;
-NET sys_ssram_bw_n<1>        LOC = Y5; #Y6;
-NET sys_ssram_bw_n<0>        LOC = Y6; #Y5;
-NET sys_ssram_bw_n<*>        IOSTANDARD = LVDCI_33;
-NET sys_ssram_bw_n<*>        SLEW = FAST;
-NET sys_ssram_bw_n<*>        DRIVE = 8;
-
-NET sys_ssram_adv            LOC = W4;
-NET sys_ssram_adv            IOSTANDARD = LVDCI_33;
-NET sys_ssram_adv            SLEW = FAST;
-NET sys_ssram_adv            DRIVE = 8;
-
-NET sys_ssram_mode           LOC = V26;
-NET sys_ssram_mode           IOSTANDARD = LVDCI_33;
-NET sys_ssram_mode           SLEW = FAST;
-NET sys_ssram_mode           DRIVE = 8;
-
-
-# VGA
-NET sys_vga_blue<0> LOC = M21; # VGA_B0
-NET sys_vga_blue<1> LOC = M26; # VGA_B1
-NET sys_vga_blue<2> LOC = L26; # VGA_B2
-NET sys_vga_blue<3> LOC = C5;  # VGA_B3
-NET sys_vga_blue<4> LOC = C7;  # VGA_B4
-NET sys_vga_blue<5> LOC = B7;  # VGA_B5
-NET sys_vga_blue<6> LOC = G8;  # VGA_B6
-NET sys_vga_blue<7> LOC = F8;  # VGA_B7
-NET sys_vga_blue<0> IOSTANDARD = LVCMOS33;
-NET sys_vga_blue<1> IOSTANDARD = LVCMOS33;
-NET sys_vga_blue<2> IOSTANDARD = LVCMOS33;
-NET sys_vga_blue<*> SLEW = FAST;
-NET sys_vga_blue<*> DRIVE = 8;
-
-NET sys_vga_clk  LOC = AF8;
-NET sys_vga_clk  IOSTANDARD = LVDCI_33;
-NET sys_vga_clk  SLEW = FAST;
-NET sys_vga_clk  DRIVE = 8;
-
-NET sys_vga_green<0> LOC = M22; # VGA_G0
-NET sys_vga_green<1> LOC = M23; # VGA_G1
-NET sys_vga_green<2> LOC = M20; # VGA_G2
-NET sys_vga_green<3> LOC = E4;  # VGA_G3
-NET sys_vga_green<4> LOC = D3;  # VGA_G4
-NET sys_vga_green<5> LOC = H7;  # VGA_G5
-NET sys_vga_green<6> LOC = H8;  # VGA_G6
-NET sys_vga_green<7> LOC = C1;  # VGA_G7
-NET sys_vga_green<0> IOSTANDARD = LVCMOS33;
-NET sys_vga_green<1> IOSTANDARD = LVCMOS33;
-NET sys_vga_green<2> IOSTANDARD = LVCMOS33;
-NET sys_vga_green<*> SLEW = FAST;
-NET sys_vga_green<*> DRIVE = 8;
-
-NET sys_vga_hsync LOC = C10;
-NET sys_vga_hsync SLEW = FAST;
-NET sys_vga_hsync DRIVE = 8;
-#NET sys_vga_hsync IOSTANDARD = LVCMOS33;
-
-NET sys_vga_red<0> LOC = N23; #VGA_R0
-NET sys_vga_red<1> LOC = N24; #VGA_R1
-NET sys_vga_red<2> LOC = N25; #VGA_R2
-NET sys_vga_red<3> LOC = C2;  #VGA_R3
-NET sys_vga_red<4> LOC = G7;  #VGA_R4
-NET sys_vga_red<5> LOC = F7;  #VGA_R5
-NET sys_vga_red<6> LOC = E5;  #VGA_R6
-NET sys_vga_red<7> LOC = E6;  #VGA_R7
-NET sys_vga_red<0> IOSTANDARD = LVCMOS33;
-NET sys_vga_red<1> IOSTANDARD = LVCMOS33;
-NET sys_vga_red<2> IOSTANDARD = LVCMOS33;
-NET sys_vga_red<*> SLEW = FAST;
-NET sys_vga_red<*> DRIVE = 8;
-
-NET sys_vga_vsync LOC = A8;
-NET sys_vga_vsync SLEW = FAST;
-NET sys_vga_vsync DRIVE = 8;
-#NET sys_vga_vsync IOSTANDARD = LVCMOS33;
-
-NET sys_vga_blank_n LOC = M24;
-NET sys_vga_blank_n SLEW = FAST;
-NET sys_vga_blank_n DRIVE = 8;
-NET sys_vga_blank_n IOSTANDARD = LVCMOS33;
-
-NET sys_vga_sync_n LOC = L23;
-NET sys_vga_sync_n SLEW = FAST;
-NET sys_vga_sync_n DRIVE = 8;
-NET sys_vga_sync_n IOSTANDARD = LVCMOS33;
diff --git a/projects/mips_sys/ise101/mips_sys/ucf/systest.ucf b/projects/mips_sys/ise101/mips_sys/ucf/systest.ucf
deleted file mode 100644
index a6af4a5..0000000
--- a/projects/mips_sys/ise101/mips_sys/ucf/systest.ucf
+++ /dev/null
@@ -1,500 +0,0 @@
-#
-#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
-#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
-#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
-#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
-#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
-#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-#     FOR A PARTICULAR PURPOSE.
-#
-#     (c) Copyright 2005 Xilinx, Inc.
-#     All rights reserved.
-#
-
-CONFIG STEPPING = "ES";
-
-# Bus clock nets
-NET "clk" TNM_NET = "clk";
-TIMESPEC "TS_clk" = PERIOD "clk" 9.9 ns HIGH 50 %;
-
-NET "inst_vga_frontend/inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk";
-#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
-TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG;
-
-NET "sys_clk_in" LOC = "AE14";
-NET sys_clk_in IOSTANDARD = LVCMOS33;
-NET "sys_rst_n_in" LOC = "D6";
-NET sys_rst_n_in PULLUP;
-NET "sys_rst_n_in" TIG;
-NET "rst" TIG;
-
-NET "sys_clk_in" CLOCK_DEDICATED_ROUTE = FALSE;
-PIN "inst_clockgen/inst_DCM_BASE_0.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
-
-NET "sys_sdr_clk_fb" CLOCK_DEDICATED_ROUTE = FALSE;
-PIN "inst_clockgen/inst_DCM_BASE_0.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE;
-
-# Locate DCM/BUFG - Tools can probably figure them out automatically
-#                   but just LOC them down to be safe
-#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2;
-#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1;
-
-INST "inst_mips_top" AREA_GROUP = "AG_inst_mips_top" ;
-# GOOD 1
-#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y85:SLICE_X39Y0 ;
-#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y10, RAMB16_X1Y0:RAMB16_X1Y10, RAMB16_X2Y0:RAMB16_X2Y10, RAMB16_X3Y0:RAMB16_X3Y10 ;
-
-# GOOD 2 (smaller)
-#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y69:SLICE_X39Y0 ;
-#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y8, RAMB16_X1Y0:RAMB16_X1Y8, RAMB16_X2Y0:RAMB16_X2Y8, RAMB16_X3Y0:RAMB16_X3Y8 ;
-
-# GOOD 3 (even smaller)
-#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y61:SLICE_X39Y0 ;
-#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y7, RAMB16_X1Y0:RAMB16_X1Y7, RAMB16_X2Y0:RAMB16_X2Y7, RAMB16_X3Y0:RAMB16_X3Y7 ;
-
-# GOOD 4 (even more smaller)
-AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y53:SLICE_X39Y0 ;
-AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y6, RAMB16_X1Y0:RAMB16_X1Y6, RAMB16_X2Y0:RAMB16_X2Y6, RAMB16_X3Y0:RAMB16_X3Y6 ;
-
-////////////////////////////////////////////////////////////////////////////
-// Misc Board Signals
-////////////////////////////////////////////////////////////////////////////
-
-NET sys_error<0> LOC = V6;
-NET sys_error<1> LOC = L24;
-NET sys_error<*> IOSTANDARD = LVCMOS33;
-NET sys_error<*> DRIVE = 2;
-NET sys_error<*> TIG;
-
-////////////////////////////////////////////////////////////////////////////
-// RS-232
-////////////////////////////////////////////////////////////////////////////
-NET sys_rx LOC = W2;
-NET sys_rx IOSTANDARD = LVCMOS33;
-NET sys_rx TIG;
-NET "sys_tx" LOC = "W1";
-NET sys_tx IOSTANDARD = LVCMOS33;
-NET "sys_tx" TIG;
-
-////////////////////////////////////////////////////////////////////////////
-// Buttons, LEDs, and DIP Switches
-////////////////////////////////////////////////////////////////////////////
-# GPLED 0-3
-NET "sys_led<0>" LOC = "G5"; #GPLED0
-NET "sys_led<1>" LOC = "G6"; #GPLED1
-NET "sys_led<2>" LOC = "A11"; #GPLED2
-NET "sys_led<3>" LOC = "A12"; #GPLED3
-# North-East-South-West-Center LEDs
-NET "sys_led<4>" LOC = "F9"; # W LED
-NET "sys_led<5>" LOC = "E2"; # N LED
-NET "sys_led<6>" LOC = "E10"; # E LED
-NET "sys_led<7>" LOC = "A5"; # S LED
-NET "sys_led<8>" LOC = "C6"; # C LED
-NET "sys_led<*>" TIG;
-NET "sys_led<*>" SLEW = SLOW;
-NET "sys_led<*>" DRIVE = 2;
-#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
-# North-East-South-West-Center Buttons
-NET "sys_btn<0>" LOC = "E9"; # W Button
-NET "sys_btn<1>" LOC = "E7"; # N Button
-NET "sys_btn<2>" LOC = "F10"; # E Button
-NET "sys_btn<3>" LOC = "A6"; # S Button
-NET "sys_btn<4>" LOC = "B6"; # C Button
-NET "sys_btn<*>" TIG;
-NET "sys_btn<*>" PULLDOWN;
-#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
-# Dip Switches 1-8
-NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
-NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
-NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
-NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
-NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
-NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
-NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
-NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
-NET "sys_dip<*>" PULLDOWN;
-NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
-NET "sys_dip<*>" TIG;
-////////////////////////////////////////////////////////////////////////////
-// LCD
-////////////////////////////////////////////////////////////////////////////
-NET sys_lcd_e LOC = AE13; # LCD_E
-NET sys_lcd_e IOSTANDARD = LVCMOS33;
-NET sys_lcd_e SLEW = SLOW;
-NET sys_lcd_e DRIVE = 2;
-NET sys_lcd_e TIG;
-NET sys_lcd_rs LOC = AC17; # LCD_RS
-NET sys_lcd_rs IOSTANDARD = LVCMOS33;
-NET sys_lcd_rs SLEW = SLOW;
-NET sys_lcd_rs DRIVE = 2;
-NET sys_lcd_rs TIG;
-NET sys_lcd_rw LOC = AB17; # LCD_RW
-NET sys_lcd_rw IOSTANDARD = LVCMOS33;
-NET sys_lcd_rw SLEW = SLOW;
-NET sys_lcd_rw DRIVE = 2;
-NET sys_lcd_rw TIG;
-NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
-NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
-NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
-NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
-NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
-NET sys_lcd_d<*> SLEW = SLOW;
-NET sys_lcd_d<*> DRIVE = 2;
-NET sys_lcd_d<*> PULLDOWN;
-NET sys_lcd_d<*> TIG;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for DDR Controllers
-#------------------------------------------------------------------------------
-
-NET sys_sdr_a_q<0>  	LOC = C26; # DDR_A0
-NET sys_sdr_a_q<1>  	LOC = E17; # DDR_A1
-NET sys_sdr_a_q<2>  	LOC = D18; # DDR_A2
-NET sys_sdr_a_q<3>  	LOC = C19; # DDR_A3
-NET sys_sdr_a_q<4>  	LOC = F17; # DDR_A4
-NET sys_sdr_a_q<5>  	LOC = B18; # DDR_A5
-NET sys_sdr_a_q<6>  	LOC = B20; # DDR_A6
-NET sys_sdr_a_q<7>  	LOC = C20; # DDR_A7
-NET sys_sdr_a_q<8>  	LOC = D20; # DDR_A8
-NET sys_sdr_a_q<9>  	LOC = C21; # DDR_A9
-NET sys_sdr_a_q<10> 	LOC = A18; # DDR_A10
-NET sys_sdr_a_q<11> 	LOC = B21; # DDR_A11
-NET sys_sdr_a_q<12> 	LOC = A24; # DDR_A12
-NET sys_sdr_ba_q<0>  	LOC = B12; # DDR_BA0
-NET sys_sdr_ba_q<1>  	LOC = A16; # DDR_BA1
-NET sys_sdr_cas_qn		LOC = F23; # DDR_CAS_N
-NET sys_sdr_cke_q		LOC = G22; # DDR_CKE
-NET sys_sdr_cs_qn		LOC = G21; # DDR_CS_N
-NET sys_sdr_ras_qn		LOC = F24; # DDR_RAS_N
-NET sys_sdr_we_qn		LOC = A23; # DDR_WE_N
-
-NET sys_sdr_clk_p		LOC = A10; # DDR_CK1_P
-NET sys_sdr_clk_fb	LOC = B13; # DDR_CK1_P (FEEDBACK)
-NET sys_sdr_clk_n		LOC = B10; # DDR_CK1_N
-
-NET sys_sdr_dm_q<0>  	LOC = G19; # DDR_DM0
-NET sys_sdr_dm_q<1>  	LOC = G24; # DDR_DM1
-NET sys_sdr_dm_q<2>  	LOC = G20; # DDR_DM2
-NET sys_sdr_dm_q<3>  	LOC = C22; # DDR_DM3
-
-NET sys_sdr_dqs_q<0> 	LOC = D25; # DDR_DQS0
-NET sys_sdr_dqs_q<1> 	LOC = G18; # DDR_DQS1
-NET sys_sdr_dqs_q<2> 	LOC = G17; # DDR_DQS2
-NET sys_sdr_dqs_q<3> 	LOC = D26; # DDR_DQS3
-
-NET sys_sdr_data<0> 	LOC = H20; # DDR_D0
-NET sys_sdr_data<1> 	LOC = E23; # DDR_D1
-NET sys_sdr_data<2> 	LOC = H26; # DDR_D2
-NET sys_sdr_data<3> 	LOC = H22; # DDR_D3
-NET sys_sdr_data<4> 	LOC = E25; # DDR_D4
-NET sys_sdr_data<5> 	LOC = E26; # DDR_D5
-NET sys_sdr_data<6> 	LOC = F26; # DDR_D6
-NET sys_sdr_data<7> 	LOC = E24; # DDR_D7
-NET sys_sdr_data<8> 	LOC = E20; # DDR_D8
-NET sys_sdr_data<9> 	LOC = A22; # DDR_D9
-NET sys_sdr_data<10>	LOC = C23; # DDR_D10
-NET sys_sdr_data<11>	LOC = C24; # DDR_D11
-NET sys_sdr_data<12>	LOC = A20; # DDR_D12
-NET sys_sdr_data<13>	LOC = A21; # DDR_D13
-NET sys_sdr_data<14>	LOC = D24; # DDR_D14
-NET sys_sdr_data<15>	LOC = E18; # DDR_D15
-NET sys_sdr_data<16>	LOC = F18; # DDR_D16
-NET sys_sdr_data<17>	LOC = A19; # DDR_D17
-NET sys_sdr_data<18>	LOC = F19; # DDR_D18
-NET sys_sdr_data<19>	LOC = B23; # DDR_D19
-NET sys_sdr_data<20>	LOC = E21; # DDR_D20
-NET sys_sdr_data<21>	LOC = D22; # DDR_D21
-NET sys_sdr_data<22>	LOC = D23; # DDR_D22
-NET sys_sdr_data<23>	LOC = B24; # DDR_D23
-NET sys_sdr_data<24>	LOC = E22; # DDR_D24
-NET sys_sdr_data<25>	LOC = F20; # DDR_D25
-NET sys_sdr_data<26>	LOC = H23; # DDR_D26
-NET sys_sdr_data<27>	LOC = G25; # DDR_D27
-NET sys_sdr_data<28>	LOC = G26; # DDR_D28
-NET sys_sdr_data<29>	LOC = H25; # DDR_D29
-NET sys_sdr_data<30>	LOC = H24; # DDR_D30
-NET sys_sdr_data<31>	LOC = H21; # DDR_D31
-
-NET sys_sdr_a_q<*>  	IOSTANDARD = SSTL2_I;
-NET sys_sdr_a_q<*>	FAST; 
-
-NET sys_sdr_ba_q<*> 	IOSTANDARD = SSTL2_I;
-NET sys_sdr_ba_q<*>	FAST; 
-
-NET sys_sdr_cas_qn  	IOSTANDARD = SSTL2_I;
-NET sys_sdr_cas_qn	FAST; 
-
-NET sys_sdr_cke_q   	IOSTANDARD = SSTL2_I;
-NET sys_sdr_cke_q		FAST; 
-
-NET sys_sdr_clk_p		IOSTANDARD = SSTL2_I;
-NET sys_sdr_clk_p		FAST; 
-NET sys_sdr_clk_fb	IOSTANDARD = LVCMOS25;
-NET sys_sdr_clk_fb	IOBDELAY = NONE; 
-NET sys_sdr_clk_n		IOSTANDARD = SSTL2_I;
-NET sys_sdr_clk_n		FAST; 
-
-NET sys_sdr_cs_qn		IOSTANDARD = SSTL2_I;
-NET sys_sdr_cs_qn		FAST; 
-
-NET sys_sdr_ras_qn	IOSTANDARD = SSTL2_I;
-NET sys_sdr_ras_qn	FAST; 
-
-NET sys_sdr_we_qn		IOSTANDARD = SSTL2_I;
-NET sys_sdr_we_qn		FAST; 
-
-NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
-NET sys_sdr_dqs_q<*>	IOBDELAY = NONE; 
-NET sys_sdr_dqs_q<*>	FAST; 
-
-NET sys_sdr_dm_q<*>  IOSTANDARD = SSTL2_II;
-NET sys_sdr_dm_q<*>	IOBDELAY = NONE; 
-NET sys_sdr_dm_q<*>	FAST; 
-
-NET sys_sdr_data<*>  IOSTANDARD = SSTL2_II;
-NET sys_sdr_data<*>	IOBDELAY = NONE; 
-NET sys_sdr_data<*>	FAST; 
-
-#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
-
-NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p";
-NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n";
-
-# Timing Constraint for DDR Feedback Clock
-NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
-
-# USB
-NET sys_usb_a<0>   LOC        = Y10;
-NET sys_usb_a<1>   LOC        = AA10;
-NET sys_usb_a<*>   IOSTANDARD = LVCMOS33;
-
-NET sys_usb_d<0>   LOC        = AB7;
-NET sys_usb_d<1>   LOC        = AC9;
-NET sys_usb_d<2>   LOC        = AB9;
-NET sys_usb_d<3>   LOC        = AE6;
-NET sys_usb_d<4>   LOC        = AD6;
-NET sys_usb_d<5>   LOC        = AF9;
-NET sys_usb_d<6>   LOC        = AE9;
-NET sys_usb_d<7>   LOC        = AD8;
-NET sys_usb_d<8>   LOC        = AC8;
-NET sys_usb_d<9>   LOC        = AF4;
-NET sys_usb_d<10>  LOC        = AE4;
-NET sys_usb_d<11>  LOC        = AD3;
-NET sys_usb_d<12>  LOC        = AC3;
-NET sys_usb_d<13>  LOC        = AF6;
-NET sys_usb_d<14>  LOC        = AF5;
-NET sys_usb_d<15>  LOC        = AA7;
-NET sys_usb_d<*>   IOSTANDARD = LVCMOS33;
-NET sys_usb_d<*>   SLEW       = FAST;
-NET sys_usb_d<*>   DRIVE      = 8;
-NET sys_usb_d<*>   PULLDOWN;
-
-NET sys_usb_rdn    LOC        = AA8;
-NET sys_usb_rdn    IOSTANDARD = LVCMOS33;
-NET sys_usb_rdn    SLEW       = FAST;
-NET sys_usb_rdn    DRIVE      = 8;
-
-NET sys_usb_wrn    LOC        = Y8;
-NET sys_usb_wrn    IOSTANDARD = LVCMOS33;
-NET sys_usb_wrn    SLEW       = FAST;
-NET sys_usb_wrn    DRIVE      = 8;
-
-NET sys_usb_csn    LOC        = AF10;
-NET sys_usb_csn    IOSTANDARD = LVCMOS33;
-NET sys_usb_csn    SLEW       = FAST;
-NET sys_usb_csn    DRIVE      = 8;
-
-NET sys_usb_rstn   LOC        = A7;
-NET sys_usb_rstn   IOSTANDARD = LVCMOS25;
-NET sys_usb_rstn   TIG;
-
-NET sys_usb_int    LOC        = V5;
-NET sys_usb_int    IOSTANDARD = LVCMOS33;
-NET sys_usb_int    PULLDOWN;
-NET sys_usb_int    TIG;
-
-# FLASH
-NET sys_flash_a<24> LOC = T21;
-NET sys_flash_a<23> LOC = U20;
-NET sys_flash_a<22> LOC = T19;
-NET sys_flash_a<21> LOC = AC5;
-NET sys_flash_a<20> LOC = AB5;
-NET sys_flash_a<19> LOC = AC4;
-NET sys_flash_a<18> LOC = AB4;
-NET sys_flash_a<17> LOC = AB3;
-NET sys_flash_a<16> LOC = AA4;
-NET sys_flash_a<15> LOC = AA3;
-NET sys_flash_a<14> LOC = W5;
-NET sys_flash_a<13> LOC = W6;
-NET sys_flash_a<12> LOC = W3;
-NET sys_flash_a<11> LOC = AF3;
-NET sys_flash_a<10>  LOC = AE3;
-NET sys_flash_a<9>  LOC = AD2;
-NET sys_flash_a<8>  LOC = AD1;
-NET sys_flash_a<7>  LOC = AC2;
-NET sys_flash_a<6>  LOC = AC1;
-NET sys_flash_a<5>  LOC = AB2;
-NET sys_flash_a<4>  LOC = AB1;
-NET sys_flash_a<3>  LOC = AA1;
-NET sys_flash_a<2>  LOC = Y2;
-NET sys_flash_a<1>  LOC = Y1;
-NET sys_flash_a<0>  LOC = T20;
-
-NET sys_flash_d<31> LOC = F14;
-NET sys_flash_d<30> LOC = F13;
-NET sys_flash_d<29> LOC = F12;
-NET sys_flash_d<28> LOC = F11;
-NET sys_flash_d<27> LOC = F16;
-NET sys_flash_d<26> LOC = F15;
-NET sys_flash_d<25> LOC = D14;
-NET sys_flash_d<24> LOC = D13;
-NET sys_flash_d<23> LOC = D15;
-NET sys_flash_d<22> LOC = E14;
-NET sys_flash_d<21> LOC = C11;
-NET sys_flash_d<20> LOC = D11;
-NET sys_flash_d<19> LOC = D16;
-NET sys_flash_d<18> LOC = C16;
-NET sys_flash_d<17> LOC = E13;
-NET sys_flash_d<16> LOC = D12;
-NET sys_flash_d<15> LOC = AA14;
-NET sys_flash_d<14> LOC = AB14;
-NET sys_flash_d<13> LOC = AC12;
-NET sys_flash_d<12> LOC = AC11;
-NET sys_flash_d<11> LOC = AA16;
-NET sys_flash_d<10> LOC = AA15;
-NET sys_flash_d<9>  LOC = AB13;
-NET sys_flash_d<8>  LOC = AA13;
-NET sys_flash_d<7>  LOC = AC14;
-NET sys_flash_d<6>  LOC = AD14;
-NET sys_flash_d<5>  LOC = AA12;
-NET sys_flash_d<4>  LOC = AA11;
-NET sys_flash_d<3>  LOC = AC16;
-NET sys_flash_d<2>  LOC = AC15;
-NET sys_flash_d<1>  LOC = AC13;
-NET sys_flash_d<0>  LOC = AD13;
-NET sys_flash_rdn     LOC = AC6;
-NET sys_flash_wrn     LOC = AB6;
-NET sys_flash_ce      LOC = W7;
-NET sys_flash_ac97_rstn    LOC = AD10;
-NET sys_flash_byten   LOC = N22;
-
-NET sys_flash_a<*> IOSTANDARD = LVDCI_33;
-NET sys_flash_a<*>  SLEW = FAST;
-NET sys_flash_a<*>  DRIVE = 8;
-
-NET sys_flash_d<*> IOSTANDARD = LVCMOS33;
-NET sys_flash_d<*> DRIVE = 12;
-NET sys_flash_d<*> SLEW = FAST;
-NET sys_flash_d<*> PULLDOWN;
-
-NET sys_flash_rdn    IOSTANDARD = LVDCI_33;
-NET sys_flash_rdn SLEW = FAST;
-NET sys_flash_rdn DRIVE = 8;
-
-NET sys_flash_wrn    IOSTANDARD = LVDCI_33;
-NET sys_flash_wrn SLEW = FAST;
-NET sys_flash_wrn DRIVE = 8;
-
-NET sys_flash_ce           IOSTANDARD = LVDCI_33;
-NET sys_flash_ce SLEW = FAST;
-NET sys_flash_ce DRIVE = 8;
-
-NET sys_flash_ac97_rstn    IOSTANDARD = LVCMOS33;
-NET sys_flash_ac97_rstn    DRIVE = 8;
-NET sys_flash_ac97_rstn    SLEW = FAST;
-NET sys_flash_ac97_rstn    TIG;
-
-NET sys_flash_byten    IOSTANDARD = LVCMOS33;
-NET sys_flash_byten    DRIVE = 8;
-NET sys_flash_byten    SLEW = FAST;
-NET sys_flash_byten    TIG;
-
-# VGA
-NET sys_vga_blue<0> LOC = M21; # VGA_B0
-NET sys_vga_blue<1> LOC = M26; # VGA_B1
-NET sys_vga_blue<2> LOC = L26; # VGA_B2
-NET sys_vga_blue<3> LOC = C5;  # VGA_B3
-NET sys_vga_blue<4> LOC = C7;  # VGA_B4
-NET sys_vga_blue<5> LOC = B7;  # VGA_B5
-NET sys_vga_blue<6> LOC = G8;  # VGA_B6
-NET sys_vga_blue<7> LOC = F8;  # VGA_B7
-NET sys_vga_blue<0> IOSTANDARD = LVCMOS33;
-NET sys_vga_blue<1> IOSTANDARD = LVCMOS33;
-NET sys_vga_blue<2> IOSTANDARD = LVCMOS33;
-NET sys_vga_blue<*> SLEW = FAST;
-NET sys_vga_blue<*> DRIVE = 8;
-
-NET sys_vga_clk  LOC = AF8;
-NET sys_vga_clk  IOSTANDARD = LVDCI_33;
-NET sys_vga_clk  SLEW = FAST;
-NET sys_vga_clk  DRIVE = 8;
-
-NET sys_vga_green<0> LOC = M22; # VGA_G0
-NET sys_vga_green<1> LOC = M23; # VGA_G1
-NET sys_vga_green<2> LOC = M20; # VGA_G2
-NET sys_vga_green<3> LOC = E4;  # VGA_G3
-NET sys_vga_green<4> LOC = D3;  # VGA_G4
-NET sys_vga_green<5> LOC = H7;  # VGA_G5
-NET sys_vga_green<6> LOC = H8;  # VGA_G6
-NET sys_vga_green<7> LOC = C1;  # VGA_G7
-NET sys_vga_green<0> IOSTANDARD = LVCMOS33;
-NET sys_vga_green<1> IOSTANDARD = LVCMOS33;
-NET sys_vga_green<2> IOSTANDARD = LVCMOS33;
-NET sys_vga_green<*> SLEW = FAST;
-NET sys_vga_green<*> DRIVE = 8;
-
-NET sys_vga_hsync LOC = C10;
-NET sys_vga_hsync SLEW = FAST;
-NET sys_vga_hsync DRIVE = 8;
-#NET sys_vga_hsync IOSTANDARD = LVCMOS33;
-
-NET sys_vga_red<0> LOC = N23; #VGA_R0
-NET sys_vga_red<1> LOC = N24; #VGA_R1
-NET sys_vga_red<2> LOC = N25; #VGA_R2
-NET sys_vga_red<3> LOC = C2;  #VGA_R3
-NET sys_vga_red<4> LOC = G7;  #VGA_R4
-NET sys_vga_red<5> LOC = F7;  #VGA_R5
-NET sys_vga_red<6> LOC = E5;  #VGA_R6
-NET sys_vga_red<7> LOC = E6;  #VGA_R7
-NET sys_vga_red<0> IOSTANDARD = LVCMOS33;
-NET sys_vga_red<1> IOSTANDARD = LVCMOS33;
-NET sys_vga_red<2> IOSTANDARD = LVCMOS33;
-NET sys_vga_red<*> SLEW = FAST;
-NET sys_vga_red<*> DRIVE = 8;
-
-NET sys_vga_vsync LOC = A8;
-NET sys_vga_vsync SLEW = FAST;
-NET sys_vga_vsync DRIVE = 8;
-#NET sys_vga_vsync IOSTANDARD = LVCMOS33;
-
-NET sys_vga_blank_n LOC = M24;
-NET sys_vga_blank_n SLEW = FAST;
-NET sys_vga_blank_n DRIVE = 8;
-NET sys_vga_blank_n IOSTANDARD = LVCMOS33;
-
-NET sys_vga_sync_n LOC = L23;
-NET sys_vga_sync_n SLEW = FAST;
-NET sys_vga_sync_n DRIVE = 8;
-NET sys_vga_sync_n IOSTANDARD = LVCMOS33;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for AC97 Sound Controller
-#------------------------------------------------------------------------------
-NET "sys_ac97_bit_clk"  TNM_NET = "ac97_clk";
-TIMESPEC "TSACBITCLK" = PERIOD "ac97_clk" 80 ns HIGH 50 %;
-
-NET sys_ac97_bit_clk   LOC = AE10;
-NET sys_ac97_bit_clk   IOSTANDARD = LVCMOS33;
-NET sys_ac97_bit_clk   PERIOD = 80;
-NET sys_ac97_sdata_in  LOC = AD16;
-NET sys_ac97_sdata_in  IOSTANDARD = LVCMOS33;
-NET sys_ac97_sdata_out LOC = C8;
-NET sys_ac97_sdata_out SLEW = FAST;
-NET sys_ac97_ssync     LOC = D9;
-NET sys_ac97_ssync     SLEW = FAST;
diff --git a/projects/mips_sys/ise92/mips_sys/mips_sys.prj b/projects/mips_sys/ise92/mips_sys/mips_sys.prj
deleted file mode 100644
index 0916a32..0000000
--- a/projects/mips_sys/ise92/mips_sys/mips_sys.prj
+++ /dev/null
@@ -1,43 +0,0 @@
-vhdl work "../../../../lib/VGA_ctrl/src/vga_types.vhd"
-vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
-vhdl work "../../src/sdram_config.vhd"
-vhdl work "../../../../lib/misc/utils_pkg.vhd"
-vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/vga_sync.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
-vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
-vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
-vhdl work "../../../../lib/uart/kcuart_tx.vhd"
-vhdl work "../../../../lib/uart/kcuart_rx.vhd"
-vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
-vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/dpram.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
-vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
-vhdl work "../../../../lib/FIFO/src/async_fifo_ctrl.vhd"
-vhdl work "../../src/sys_types.vhd"
-vhdl work "../../src/ram_ld.vhd"
-vhdl work "../../src/bootloader.ROM_ld.vhd"
-vhdl work "../../../../lib/uart/uart_tx.vhd"
-vhdl work "../../../../lib/uart/uart_rx.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
-vhdl work "../../../../lib/FIFO/src/fifo_async.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
-vhdl work "../../../../lib/uart/uart_wb.vhd"
-vhdl work "../../../../lib/misc/rom_wb.vhd"
-vhdl work "../../../../lib/misc/ram_wb.vhd"
-vhdl work "../../../../lib/misc/lcd_port.vhd"
-vhdl work "../../../../lib/misc/gpio_wb.vhd"
-vhdl work "../../../../lib/misc/clockgen_virtex4.vhd"
-vhdl work "../../../../lib/misc/async_port_wb.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
-vhdl work "../../src/mips_sys.vhd"
diff --git a/projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj b/projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj
deleted file mode 100644
index 49db644..0000000
--- a/projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj
+++ /dev/null
@@ -1,43 +0,0 @@
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_types.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
-vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd"
-vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
-vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_sync.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
-vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
-vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
-vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
-vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_timing.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\fonts\char_rom_fixedsys_8x16.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\dpram.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\clkgen_virtex4.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\async_fifo_ctrl.vhd"
-vhdl work "W:\vhdl\projects\mips_sys\src\sys_types.vhd"
-vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd"
-vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
-vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
-vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
-vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
-vhdl work "W:\vhdl\lib\misc\rom_wb.vhd"
-vhdl work "W:\vhdl\lib\misc\ram_wb.vhd"
-vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
-vhdl work "W:\vhdl\lib\misc\gpio_wb.vhd"
-vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd"
-vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend64.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd"
-vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd"
diff --git a/projects/mips_sys/ise92/mips_sys/ucf/systest.ucf b/projects/mips_sys/ise92/mips_sys/ucf/systest.ucf
deleted file mode 100644
index 07b8d92..0000000
--- a/projects/mips_sys/ise92/mips_sys/ucf/systest.ucf
+++ /dev/null
@@ -1,469 +0,0 @@
-#
-#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
-#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
-#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
-#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
-#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
-#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-#     FOR A PARTICULAR PURPOSE.
-#
-#     (c) Copyright 2005 Xilinx, Inc.
-#     All rights reserved.
-#
-
-CONFIG STEPPING = "ES";
-
-# Bus clock nets
-NET "clk" TNM_NET = "clk";
-TIMESPEC "TS_clk" = PERIOD "clk" 9.95 ns HIGH 50 %;
-
-NET "inst_vga_frontend/inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk";
-#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
-TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG;
-
-NET "sys_clk_in" LOC = "AE14";
-NET sys_clk_in IOSTANDARD = LVCMOS33;
-NET "sys_rst_n_in" LOC = "D6";
-NET sys_rst_n_in PULLUP;
-NET "sys_rst_n_in" TIG;
-NET "rst" TIG;
-
-# Locate DCM/BUFG - Tools can probably figure them out automatically
-#                   but just LOC them down to be safe
-#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2;
-#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1;
-
-# GOOD
-INST "inst_mips_top" AREA_GROUP = "AG_inst_mips_top" ;
-AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y85:SLICE_X39Y0 ;
-AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y10, RAMB16_X1Y0:RAMB16_X1Y10, RAMB16_X2Y0:RAMB16_X2Y10, RAMB16_X3Y0:RAMB16_X3Y10 ;
-
-////////////////////////////////////////////////////////////////////////////
-// Misc Board Signals
-////////////////////////////////////////////////////////////////////////////
-
-NET sys_error<0> LOC = V6;
-NET sys_error<1> LOC = L24;
-NET sys_error<*> IOSTANDARD = LVCMOS33;
-NET sys_error<*> DRIVE = 2;
-NET sys_error<*> TIG;
-
-////////////////////////////////////////////////////////////////////////////
-// RS-232
-////////////////////////////////////////////////////////////////////////////
-NET sys_rx LOC = W2;
-NET sys_rx IOSTANDARD = LVCMOS33;
-NET sys_rx TIG;
-NET "sys_tx" LOC = "W1";
-NET sys_tx IOSTANDARD = LVCMOS33;
-NET "sys_tx" TIG;
-
-////////////////////////////////////////////////////////////////////////////
-// Buttons, LEDs, and DIP Switches
-////////////////////////////////////////////////////////////////////////////
-# GPLED 0-3
-NET "sys_led<0>" LOC = "G5"; #GPLED0
-NET "sys_led<1>" LOC = "G6"; #GPLED1
-NET "sys_led<2>" LOC = "A11"; #GPLED2
-NET "sys_led<3>" LOC = "A12"; #GPLED3
-# North-East-South-West-Center LEDs
-NET "sys_led<4>" LOC = "F9"; # W LED
-NET "sys_led<5>" LOC = "E2"; # N LED
-NET "sys_led<6>" LOC = "E10"; # E LED
-NET "sys_led<7>" LOC = "A5"; # S LED
-NET "sys_led<8>" LOC = "C6"; # C LED
-NET "sys_led<*>" TIG;
-NET "sys_led<*>" SLEW = SLOW;
-NET "sys_led<*>" DRIVE = 2;
-#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
-# North-East-South-West-Center Buttons
-NET "sys_btn<0>" LOC = "E9"; # W Button
-NET "sys_btn<1>" LOC = "E7"; # N Button
-NET "sys_btn<2>" LOC = "F10"; # E Button
-NET "sys_btn<3>" LOC = "A6"; # S Button
-NET "sys_btn<4>" LOC = "B6"; # C Button
-NET "sys_btn<*>" TIG;
-NET "sys_btn<*>" PULLDOWN;
-#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
-# Dip Switches 1-8
-NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
-NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
-NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
-NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
-NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
-NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
-NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
-NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
-NET "sys_dip<*>" PULLDOWN;
-NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
-NET "sys_dip<*>" TIG;
-////////////////////////////////////////////////////////////////////////////
-// LCD
-////////////////////////////////////////////////////////////////////////////
-NET sys_lcd_e LOC = AE13; # LCD_E
-NET sys_lcd_e IOSTANDARD = LVCMOS33;
-NET sys_lcd_e SLEW = SLOW;
-NET sys_lcd_e DRIVE = 2;
-NET sys_lcd_e TIG;
-NET sys_lcd_rs LOC = AC17; # LCD_RS
-NET sys_lcd_rs IOSTANDARD = LVCMOS33;
-NET sys_lcd_rs SLEW = SLOW;
-NET sys_lcd_rs DRIVE = 2;
-NET sys_lcd_rs TIG;
-NET sys_lcd_rw LOC = AB17; # LCD_RW
-NET sys_lcd_rw IOSTANDARD = LVCMOS33;
-NET sys_lcd_rw SLEW = SLOW;
-NET sys_lcd_rw DRIVE = 2;
-NET sys_lcd_rw TIG;
-NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
-NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
-NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
-NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
-NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
-NET sys_lcd_d<*> SLEW = SLOW;
-NET sys_lcd_d<*> DRIVE = 2;
-NET sys_lcd_d<*> PULLDOWN;
-NET sys_lcd_d<*> TIG;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for DDR Controllers
-#------------------------------------------------------------------------------
-
-NET sys_sdr_a_q<0>  	LOC = C26; # DDR_A0
-NET sys_sdr_a_q<1>  	LOC = E17; # DDR_A1
-NET sys_sdr_a_q<2>  	LOC = D18; # DDR_A2
-NET sys_sdr_a_q<3>  	LOC = C19; # DDR_A3
-NET sys_sdr_a_q<4>  	LOC = F17; # DDR_A4
-NET sys_sdr_a_q<5>  	LOC = B18; # DDR_A5
-NET sys_sdr_a_q<6>  	LOC = B20; # DDR_A6
-NET sys_sdr_a_q<7>  	LOC = C20; # DDR_A7
-NET sys_sdr_a_q<8>  	LOC = D20; # DDR_A8
-NET sys_sdr_a_q<9>  	LOC = C21; # DDR_A9
-NET sys_sdr_a_q<10> 	LOC = A18; # DDR_A10
-NET sys_sdr_a_q<11> 	LOC = B21; # DDR_A11
-NET sys_sdr_a_q<12> 	LOC = A24; # DDR_A12
-NET sys_sdr_ba_q<0>  	LOC = B12; # DDR_BA0
-NET sys_sdr_ba_q<1>  	LOC = A16; # DDR_BA1
-NET sys_sdr_cas_qn		LOC = F23; # DDR_CAS_N
-NET sys_sdr_cke_q		LOC = G22; # DDR_CKE
-NET sys_sdr_cs_qn		LOC = G21; # DDR_CS_N
-NET sys_sdr_ras_qn		LOC = F24; # DDR_RAS_N
-NET sys_sdr_we_qn		LOC = A23; # DDR_WE_N
-
-NET sys_sdr_clk_p		LOC = A10; # DDR_CK1_P
-NET sys_sdr_clk_fb	LOC = B13; # DDR_CK1_P (FEEDBACK)
-NET sys_sdr_clk_n		LOC = B10; # DDR_CK1_N
-
-NET sys_sdr_dm_q<0>  	LOC = G19; # DDR_DM0
-NET sys_sdr_dm_q<1>  	LOC = G24; # DDR_DM1
-NET sys_sdr_dm_q<2>  	LOC = G20; # DDR_DM2
-NET sys_sdr_dm_q<3>  	LOC = C22; # DDR_DM3
-
-NET sys_sdr_dqs_q<0> 	LOC = D25; # DDR_DQS0
-NET sys_sdr_dqs_q<1> 	LOC = G18; # DDR_DQS1
-NET sys_sdr_dqs_q<2> 	LOC = G17; # DDR_DQS2
-NET sys_sdr_dqs_q<3> 	LOC = D26; # DDR_DQS3
-
-NET sys_sdr_data<0> 	LOC = H20; # DDR_D0
-NET sys_sdr_data<1> 	LOC = E23; # DDR_D1
-NET sys_sdr_data<2> 	LOC = H26; # DDR_D2
-NET sys_sdr_data<3> 	LOC = H22; # DDR_D3
-NET sys_sdr_data<4> 	LOC = E25; # DDR_D4
-NET sys_sdr_data<5> 	LOC = E26; # DDR_D5
-NET sys_sdr_data<6> 	LOC = F26; # DDR_D6
-NET sys_sdr_data<7> 	LOC = E24; # DDR_D7
-NET sys_sdr_data<8> 	LOC = E20; # DDR_D8
-NET sys_sdr_data<9> 	LOC = A22; # DDR_D9
-NET sys_sdr_data<10>	LOC = C23; # DDR_D10
-NET sys_sdr_data<11>	LOC = C24; # DDR_D11
-NET sys_sdr_data<12>	LOC = A20; # DDR_D12
-NET sys_sdr_data<13>	LOC = A21; # DDR_D13
-NET sys_sdr_data<14>	LOC = D24; # DDR_D14
-NET sys_sdr_data<15>	LOC = E18; # DDR_D15
-NET sys_sdr_data<16>	LOC = F18; # DDR_D16
-NET sys_sdr_data<17>	LOC = A19; # DDR_D17
-NET sys_sdr_data<18>	LOC = F19; # DDR_D18
-NET sys_sdr_data<19>	LOC = B23; # DDR_D19
-NET sys_sdr_data<20>	LOC = E21; # DDR_D20
-NET sys_sdr_data<21>	LOC = D22; # DDR_D21
-NET sys_sdr_data<22>	LOC = D23; # DDR_D22
-NET sys_sdr_data<23>	LOC = B24; # DDR_D23
-NET sys_sdr_data<24>	LOC = E22; # DDR_D24
-NET sys_sdr_data<25>	LOC = F20; # DDR_D25
-NET sys_sdr_data<26>	LOC = H23; # DDR_D26
-NET sys_sdr_data<27>	LOC = G25; # DDR_D27
-NET sys_sdr_data<28>	LOC = G26; # DDR_D28
-NET sys_sdr_data<29>	LOC = H25; # DDR_D29
-NET sys_sdr_data<30>	LOC = H24; # DDR_D30
-NET sys_sdr_data<31>	LOC = H21; # DDR_D31
-
-NET sys_sdr_a_q<*>  	IOSTANDARD = SSTL2_I;
-NET sys_sdr_a_q<*>	FAST; 
-
-NET sys_sdr_ba_q<*> 	IOSTANDARD = SSTL2_I;
-NET sys_sdr_ba_q<*>	FAST; 
-
-NET sys_sdr_cas_qn  	IOSTANDARD = SSTL2_I;
-NET sys_sdr_cas_qn	FAST; 
-
-NET sys_sdr_cke_q   	IOSTANDARD = SSTL2_I;
-NET sys_sdr_cke_q		FAST; 
-
-NET sys_sdr_clk_p		IOSTANDARD = SSTL2_I;
-NET sys_sdr_clk_p		FAST; 
-NET sys_sdr_clk_fb	IOSTANDARD = LVCMOS25;
-NET sys_sdr_clk_fb	IOBDELAY = NONE; 
-NET sys_sdr_clk_n		IOSTANDARD = SSTL2_I;
-NET sys_sdr_clk_n		FAST; 
-
-NET sys_sdr_cas_qn	IOSTANDARD = SSTL2_I;
-NET sys_sdr_cas_qn	FAST; 
-
-NET sys_sdr_cs_qn		IOSTANDARD = SSTL2_I;
-NET sys_sdr_cs_qn		FAST; 
-
-NET sys_sdr_ras_qn	IOSTANDARD = SSTL2_I;
-NET sys_sdr_ras_qn	FAST; 
-
-NET sys_sdr_we_qn		IOSTANDARD = SSTL2_I;
-NET sys_sdr_we_qn		FAST; 
-
-NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
-NET sys_sdr_dqs_q<*>	IOBDELAY = NONE; 
-NET sys_sdr_dqs_q<*>	FAST; 
-
-NET sys_sdr_dm_q<*>  IOSTANDARD = SSTL2_II;
-NET sys_sdr_dm_q<*>	IOBDELAY = NONE; 
-NET sys_sdr_dm_q<*>	FAST; 
-
-NET sys_sdr_data<*>  IOSTANDARD = SSTL2_II;
-NET sys_sdr_data<*>	IOBDELAY = NONE; 
-NET sys_sdr_data<*>	FAST; 
-
-#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
-
-NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p";
-NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n";
-
-# Timing Constraint for DDR Feedback Clock
-NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
-
-# USB
-NET sys_usb_a<0>   LOC        = Y10;
-NET sys_usb_a<1>   LOC        = AA10;
-NET sys_usb_a<*>   IOSTANDARD = LVCMOS33;
-
-NET sys_usb_d<0>   LOC        = AB7;
-NET sys_usb_d<1>   LOC        = AC9;
-NET sys_usb_d<2>   LOC        = AB9;
-NET sys_usb_d<3>   LOC        = AE6;
-NET sys_usb_d<4>   LOC        = AD6;
-NET sys_usb_d<5>   LOC        = AF9;
-NET sys_usb_d<6>   LOC        = AE9;
-NET sys_usb_d<7>   LOC        = AD8;
-NET sys_usb_d<8>   LOC        = AC8;
-NET sys_usb_d<9>   LOC        = AF4;
-NET sys_usb_d<10>  LOC        = AE4;
-NET sys_usb_d<11>  LOC        = AD3;
-NET sys_usb_d<12>  LOC        = AC3;
-NET sys_usb_d<13>  LOC        = AF6;
-NET sys_usb_d<14>  LOC        = AF5;
-NET sys_usb_d<15>  LOC        = AA7;
-NET sys_usb_d<*>   IOSTANDARD = LVCMOS33;
-NET sys_usb_d<*>   SLEW       = FAST;
-NET sys_usb_d<*>   DRIVE      = 8;
-NET sys_usb_d<*>   PULLDOWN;
-
-NET sys_usb_rdn    LOC        = AA8;
-NET sys_usb_rdn    IOSTANDARD = LVCMOS33;
-NET sys_usb_rdn    SLEW       = FAST;
-NET sys_usb_rdn    DRIVE      = 8;
-
-NET sys_usb_wrn    LOC        = Y8;
-NET sys_usb_wrn    IOSTANDARD = LVCMOS33;
-NET sys_usb_wrn    SLEW       = FAST;
-NET sys_usb_wrn    DRIVE      = 8;
-
-NET sys_usb_csn    LOC        = AF10;
-NET sys_usb_csn    IOSTANDARD = LVCMOS33;
-NET sys_usb_csn    SLEW       = FAST;
-NET sys_usb_csn    DRIVE      = 8;
-
-NET sys_usb_rstn   LOC        = A7;
-NET sys_usb_rstn   IOSTANDARD = LVCMOS25;
-NET sys_usb_rstn   TIG;
-
-NET sys_usb_int    LOC        = V5;
-NET sys_usb_int    IOSTANDARD = LVCMOS33;
-NET sys_usb_int    PULLDOWN;
-NET sys_usb_int    TIG;
-
-# FLASH
-NET sys_flash_a<24> LOC = T21;
-NET sys_flash_a<23> LOC = U20;
-NET sys_flash_a<22> LOC = T19;
-NET sys_flash_a<21> LOC = AC5;
-NET sys_flash_a<20> LOC = AB5;
-NET sys_flash_a<19> LOC = AC4;
-NET sys_flash_a<18> LOC = AB4;
-NET sys_flash_a<17> LOC = AB3;
-NET sys_flash_a<16> LOC = AA4;
-NET sys_flash_a<15> LOC = AA3;
-NET sys_flash_a<14> LOC = W5;
-NET sys_flash_a<13> LOC = W6;
-NET sys_flash_a<12> LOC = W3;
-NET sys_flash_a<11> LOC = AF3;
-NET sys_flash_a<10>  LOC = AE3;
-NET sys_flash_a<9>  LOC = AD2;
-NET sys_flash_a<8>  LOC = AD1;
-NET sys_flash_a<7>  LOC = AC2;
-NET sys_flash_a<6>  LOC = AC1;
-NET sys_flash_a<5>  LOC = AB2;
-NET sys_flash_a<4>  LOC = AB1;
-NET sys_flash_a<3>  LOC = AA1;
-NET sys_flash_a<2>  LOC = Y2;
-NET sys_flash_a<1>  LOC = Y1;
-NET sys_flash_a<0>  LOC = T20;
-
-NET sys_flash_d<31> LOC = F14;
-NET sys_flash_d<30> LOC = F13;
-NET sys_flash_d<29> LOC = F12;
-NET sys_flash_d<28> LOC = F11;
-NET sys_flash_d<27> LOC = F16;
-NET sys_flash_d<26> LOC = F15;
-NET sys_flash_d<25> LOC = D14;
-NET sys_flash_d<24> LOC = D13;
-NET sys_flash_d<23> LOC = D15;
-NET sys_flash_d<22> LOC = E14;
-NET sys_flash_d<21> LOC = C11;
-NET sys_flash_d<20> LOC = D11;
-NET sys_flash_d<19> LOC = D16;
-NET sys_flash_d<18> LOC = C16;
-NET sys_flash_d<17> LOC = E13;
-NET sys_flash_d<16> LOC = D12;
-NET sys_flash_d<15> LOC = AA14;
-NET sys_flash_d<14> LOC = AB14;
-NET sys_flash_d<13> LOC = AC12;
-NET sys_flash_d<12> LOC = AC11;
-NET sys_flash_d<11> LOC = AA16;
-NET sys_flash_d<10> LOC = AA15;
-NET sys_flash_d<9>  LOC = AB13;
-NET sys_flash_d<8>  LOC = AA13;
-NET sys_flash_d<7>  LOC = AC14;
-NET sys_flash_d<6>  LOC = AD14;
-NET sys_flash_d<5>  LOC = AA12;
-NET sys_flash_d<4>  LOC = AA11;
-NET sys_flash_d<3>  LOC = AC16;
-NET sys_flash_d<2>  LOC = AC15;
-NET sys_flash_d<1>  LOC = AC13;
-NET sys_flash_d<0>  LOC = AD13;
-NET sys_flash_rdn     LOC = AC6;
-NET sys_flash_wrn     LOC = AB6;
-NET sys_flash_ce      LOC = W7;
-NET sys_flash_rstn    LOC = AD10;
-NET sys_flash_byten   LOC = N22;
-
-NET sys_flash_a<*> IOSTANDARD = LVDCI_33;
-NET sys_flash_a<*>  SLEW = FAST;
-NET sys_flash_a<*>  DRIVE = 8;
-
-NET sys_flash_d<*> IOSTANDARD = LVCMOS33;
-NET sys_flash_d<*> DRIVE = 12;
-NET sys_flash_d<*> SLEW = FAST;
-NET sys_flash_d<*> PULLDOWN;
-
-NET sys_flash_rdn    IOSTANDARD = LVDCI_33;
-NET sys_flash_rdn SLEW = FAST;
-NET sys_flash_rdn DRIVE = 8;
-
-NET sys_flash_wrn    IOSTANDARD = LVDCI_33;
-NET sys_flash_wrn SLEW = FAST;
-NET sys_flash_wrn DRIVE = 8;
-
-NET sys_flash_ce           IOSTANDARD = LVDCI_33;
-NET sys_flash_ce SLEW = FAST;
-NET sys_flash_ce DRIVE = 8;
-
-NET sys_flash_rstn    IOSTANDARD = LVCMOS33;
-NET sys_flash_rstn    DRIVE = 8;
-NET sys_flash_rstn    SLEW = FAST;
-NET sys_flash_rstn    TIG;
-
-NET sys_flash_byten    IOSTANDARD = LVCMOS33;
-NET sys_flash_byten    DRIVE = 8;
-NET sys_flash_byten    SLEW = FAST;
-NET sys_flash_byten    TIG;
-
-# VGA
-NET sys_vga_blue<0> LOC = M21; # VGA_B0
-NET sys_vga_blue<1> LOC = M26; # VGA_B1
-NET sys_vga_blue<2> LOC = L26; # VGA_B2
-NET sys_vga_blue<3> LOC = C5;  # VGA_B3
-NET sys_vga_blue<4> LOC = C7;  # VGA_B4
-NET sys_vga_blue<5> LOC = B7;  # VGA_B5
-NET sys_vga_blue<6> LOC = G8;  # VGA_B6
-NET sys_vga_blue<7> LOC = F8;  # VGA_B7
-NET sys_vga_blue<0> IOSTANDARD = LVCMOS33;
-NET sys_vga_blue<1> IOSTANDARD = LVCMOS33;
-NET sys_vga_blue<2> IOSTANDARD = LVCMOS33;
-NET sys_vga_blue<*> SLEW = FAST;
-NET sys_vga_blue<*> DRIVE = 8;
-
-NET sys_vga_clk  LOC = AF8;
-NET sys_vga_clk  IOSTANDARD = LVDCI_33;
-NET sys_vga_clk  SLEW = FAST;
-NET sys_vga_clk  DRIVE = 8;
-
-NET sys_vga_green<0> LOC = M22; # VGA_G0
-NET sys_vga_green<1> LOC = M23; # VGA_G1
-NET sys_vga_green<2> LOC = M20; # VGA_G2
-NET sys_vga_green<3> LOC = E4;  # VGA_G3
-NET sys_vga_green<4> LOC = D3;  # VGA_G4
-NET sys_vga_green<5> LOC = H7;  # VGA_G5
-NET sys_vga_green<6> LOC = H8;  # VGA_G6
-NET sys_vga_green<7> LOC = C1;  # VGA_G7
-NET sys_vga_green<0> IOSTANDARD = LVCMOS33;
-NET sys_vga_green<1> IOSTANDARD = LVCMOS33;
-NET sys_vga_green<2> IOSTANDARD = LVCMOS33;
-NET sys_vga_green<*> SLEW = FAST;
-NET sys_vga_green<*> DRIVE = 8;
-
-NET sys_vga_hsync LOC = C10;
-NET sys_vga_hsync SLEW = FAST;
-NET sys_vga_hsync DRIVE = 8;
-#NET sys_vga_hsync IOSTANDARD = LVCMOS33;
-
-NET sys_vga_red<0> LOC = N23; #VGA_R0
-NET sys_vga_red<1> LOC = N24; #VGA_R1
-NET sys_vga_red<2> LOC = N25; #VGA_R2
-NET sys_vga_red<3> LOC = C2;  #VGA_R3
-NET sys_vga_red<4> LOC = G7;  #VGA_R4
-NET sys_vga_red<5> LOC = F7;  #VGA_R5
-NET sys_vga_red<6> LOC = E5;  #VGA_R6
-NET sys_vga_red<7> LOC = E6;  #VGA_R7
-NET sys_vga_red<0> IOSTANDARD = LVCMOS33;
-NET sys_vga_red<1> IOSTANDARD = LVCMOS33;
-NET sys_vga_red<2> IOSTANDARD = LVCMOS33;
-NET sys_vga_red<*> SLEW = FAST;
-NET sys_vga_red<*> DRIVE = 8;
-
-NET sys_vga_vsync LOC = A8;
-NET sys_vga_vsync SLEW = FAST;
-NET sys_vga_vsync DRIVE = 8;
-#NET sys_vga_vsync IOSTANDARD = LVCMOS33;
-
-NET sys_vga_blank_n LOC = M24;
-NET sys_vga_blank_n SLEW = FAST;
-NET sys_vga_blank_n DRIVE = 8;
-NET sys_vga_blank_n IOSTANDARD = LVCMOS33;
-
-NET sys_vga_sync_n LOC = L23;
-NET sys_vga_sync_n SLEW = FAST;
-NET sys_vga_sync_n DRIVE = 8;
-NET sys_vga_sync_n IOSTANDARD = LVCMOS33;
diff --git a/projects/mips_sys/sim/tb_mips_sys.fdo b/projects/mips_sys/sim/tb_mips_sys.fdo
deleted file mode 100644
index 83b33c0..0000000
--- a/projects/mips_sys/sim/tb_mips_sys.fdo
+++ /dev/null
@@ -1,104 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-vlib work
-# Configs
-vcom -explicit  -93 "../src/sdram_config_sim.vhd"
-
-# Packages
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_instr.vhd"
-vcom -explicit  -93 "../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
-vcom -explicit  -93 "../../../lib/misc/utils_pkg.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd"
-
-# RAMs
-vcom -explicit  -93 "../../../lib/misc/dpram_2w2r.vhd"
-vcom -explicit  -93 "../../../lib/misc/dpram_1w1r.vhd"
-vcom -explicit  -93 "../../../lib/misc/dpram_1w1r_dist.vhd"
-
-# FIFOS
-vcom -explicit  -93 "../../../lib/FIFO/src/gray_counter.vhd"
-vcom -explicit  -93 "../../../lib/FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit  -93 "../../../lib/FIFO/src/fifo_sync.vhd"
-vcom -explicit  -93 "../../../lib/FIFO/src/fifo_sync_dist.vhd"
-vcom -explicit  -93 "../../../lib/FIFO/src/fifo_async_ctrl.vhd"
-vcom -explicit  -93 "../../../lib/FIFO/src/fifo_async.vhd"
-
-# CPU
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_idecode_rom.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_reg.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_alu.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_cop.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_dcache.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_icache.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_biu.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
-vcom -explicit  -93 "../src/bootloader.ROM.vhd"
-vcom -explicit  -93 "../../../lib/misc/rom_wb.vhd"
-
-# VGA
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/fonts/char_rom_c64.vhd"
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_types.vhd"
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/char_gen.vhd"
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_sync.vhd"
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_timing.vhd"
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_backend.vhd"
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
-
-# UART
-vcom -explicit  -93 "../../../lib/uart/bbfifo_16x8.vhd"
-vcom -explicit  -93 "../../../lib/uart/kcuart_rx.vhd"
-vcom -explicit  -93 "../../../lib/uart/kcuart_tx.vhd"
-vcom -explicit  -93 "../../../lib/uart/uart_rx.vhd"
-vcom -explicit  -93 "../../../lib/uart/uart_tx.vhd"
-vcom -explicit  -93 "../../../lib/uart/uart_wb.vhd"
-
-# GPIO
-vcom -explicit  -93 "../../../lib/misc/gpio_wb.vhd"
-
-# LCD
-vcom -explicit  -93 "../../../lib/misc/lcd_port.vhd"
-
-# Flash and USB
-vcom -explicit  -93 "../../../lib/misc/async_types.vhd"
-vcom -explicit  -93 "../../../lib/misc/async_port_wb.vhd"
-vcom -explicit  -93 "../../../lib/misc/flash_port_wb.vhd"
-vcom -explicit  -93 "../src/async_defs.vhd"
-
-# Sync SRAM
-vcom -explicit  -93 "../../../lib/SSRAM/src/package_utility.vhd"
-vcom -explicit  -93 "../../../lib/SSRAM/src/CY7C1354B.vhd"
-vcom -explicit  -93 "../../../lib/SSRAM/src/ssram_port_wb.vhd"
-
-# SDRAM
-vcom -explicit  -93 "../../../lib/misc/clockgen_virtex4.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
-
-# AC-97
-vcom -explicit  -93 "../../../lib/misc/singleshot.vhd"
-vcom -explicit  -93 "../../../lib/ac97_ctrl/src/core/ac_out.vhd"
-vcom -explicit  -93 "../../../lib/ac97_ctrl/src/core/ac_in.vhd"
-vcom -explicit  -93 "../../../lib/ac97_ctrl/src/core/ac_io.vhd"
-vcom -explicit  -93 "../../../lib/ac97_ctrl/src/core/ac97_wb.vhd"
-
-# Top and TB
-vcom -explicit  -93 "../src/mips_sys_sim.vhd"
-vcom -explicit  -93 "../src/tb_mips_sys.vhd"
-
-vsim -t 1ps   -lib work tb_mips_sys
-do {tb_mips_sys.wdo}
-view wave
-view structure
-view signals
-run 50ms
diff --git a/projects/mips_sys/sim/tb_mips_sys.wdo b/projects/mips_sys/sim/tb_mips_sys.wdo
deleted file mode 100644
index 606b2fc..0000000
--- a/projects/mips_sys/sim/tb_mips_sys.wdo
+++ /dev/null
@@ -1,248 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -divider UUT
-add wave -noupdate -format Logic /tb_mips_sys/sys_rst_n_in
-add wave -noupdate -format Logic /tb_mips_sys/sys_clk_in
-add wave -noupdate -format Literal /tb_mips_sys/dip
-add wave -noupdate -format Literal /tb_mips_sys/btn
-add wave -noupdate -format Literal /tb_mips_sys/led
-add wave -noupdate -format Logic /tb_mips_sys/sys_rx
-add wave -noupdate -format Logic /tb_mips_sys/sys_tx
-add wave -noupdate -format Literal /tb_mips_sys/sys_lcd_d
-add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_e
-add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rs
-add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rw
-add wave -noupdate -format Logic /tb_mips_sys/refresh
-add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_fb
-add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_p
-add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_n
-add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cke_q
-add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cs_qn
-add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_ras_qn
-add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cas_qn
-add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_we_qn
-add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dqs_q
-add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_ba_q
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_a_q
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_data
-add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dm_q
-add wave -noupdate -format Literal /tb_mips_sys/sys_error
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o
-add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/we_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o
-add wave -noupdate -format Literal /tb_mips_sys/uut/mem_area
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk
-add wave -noupdate -divider Arbiter
-add wave -noupdate -format Literal /tb_mips_sys/uut/arb_idx
-add wave -noupdate -format Literal /tb_mips_sys/uut/arb_req
-add wave -noupdate -format Literal /tb_mips_sys/uut/arb_gnt
-add wave -noupdate -divider AC97
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_sdata_in
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_bit_clk
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_sdata_out
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_ssync
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/cmd_reg_we
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/cmd_pending
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/stat_valid
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/stat_pending
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_frame_valid
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_frame
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_tx
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_status
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_ac97_wb/request
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_data_start
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/ac97_stat
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_frame_sync
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_rx
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_tx
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_re
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_we
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_full
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_empty
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_almost_full
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_almost_empty
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_dout
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/ac_frame_reg
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_ssync
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_bit_clk
-add wave -noupdate -format Logic /tb_mips_sys/ac_synced
-add wave -noupdate -divider {CPU Master}
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o_cpu
-add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o_cpu
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o_cpu
-add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o_cpu
-add wave -noupdate -format Logic /tb_mips_sys/uut/we_o_cpu
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_cpu
-add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_cpu
-add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_cpu
-add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_cpu
-add wave -noupdate -divider {VGA Master}
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o_vga
-add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o_vga
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o_vga
-add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o_vga
-add wave -noupdate -format Logic /tb_mips_sys/uut/we_o_vga
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_vga
-add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_vga
-add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_vga
-add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_vga
-add wave -noupdate -divider BUI
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk
-add wave -noupdate -format Literal -label .op -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.op
-add wave -noupdate -divider USB
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk
-add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rstn
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_d
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_a
-add wave -noupdate -format Logic /tb_mips_sys/sys_usb_csn
-add wave -noupdate -format Logic /tb_mips_sys/sys_usb_wrn
-add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rdn
-add wave -noupdate -format Logic /tb_mips_sys/sys_usb_int
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_usb_port/s
-add wave -noupdate -divider Flash
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ac97_rstn
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/as
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/s
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_we_n
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_oe_n
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a
-add wave -noupdate -format Logic /tb_mips_sys/sys_flash_ce
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_do
-add wave -noupdate -format Logic /tb_mips_sys/uut/flash_oe_n
-add wave -noupdate -format Logic /tb_mips_sys/uut/flash_we_n
-add wave -noupdate -format Logic /tb_mips_sys/uut/flash_d_drv
-add wave -noupdate -format Logic /tb_mips_sys/uut/flash_bsy
-add wave -noupdate -divider {Sync SRAM}
-add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_clk
-add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_cke_n
-add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_ce_n
-add wave -noupdate -format Literal /tb_mips_sys/sys_ssram_dp
-add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_adv
-add wave -noupdate -format Literal /tb_mips_sys/sys_ssram_bw_n
-add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_mode
-add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_zz
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_we_n
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_oe_n
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/ssram_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/ssram_do
-add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_oe_n
-add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_we_n
-add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_d_drv
-add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_bsy
-add wave -noupdate -divider {MIPS TOP}
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/hdu
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/events
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/epc
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/cause
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/badvaddr
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exc_code
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status_save
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status_rest
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exception
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/test_reg
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/test_reg_we
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ir
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ir_valid
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/din
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/dout
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/stat_reg_we
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_in
-add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exc_state
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/eflags_reg_we
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/eflags
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_run
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_reg_dual/reg_mem
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/id_stage
-add wave -noupdate -format Logic -label .exc_commit /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.exc_commit
-add wave -noupdate -format Logic -label .exc_pending /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.exc_pending
-add wave -noupdate -format Logic -label .exc_exit /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.exc_exit
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exc_state
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/epc
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/cause
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/run_en
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_rst
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/mem_stage
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/dout
-add wave -noupdate -format Logic -label .cop_read /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.cop_read
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/wb_stage
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exception
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/cause
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/epc
-add wave -noupdate -divider {CPU DMEM}
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk
-add wave -noupdate -divider {CPU IMEM}
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk
-add wave -noupdate -divider {User ROM}
-add wave -noupdate -divider UUT
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sys_sdr_a_q
-add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_ba_q
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cas_qn
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cke_q
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_fb
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_n
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_p
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cs_qn
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sys_sdr_data
-add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dm_q
-add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dqs_q
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_ras_qn
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_we_qn
-add wave -noupdate -divider I-Cache
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_rst
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/run_en
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc
-add wave -noupdate -format Logic -label .branch -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.ctrl.branch
-add wave -noupdate -divider D-Cache
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {23579127600 ps} 0} {{Cursor 100} {5544988254 ps} 0}
-configure wave -namecolwidth 187
-configure wave -valuecolwidth 64
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {381220785 ps} {2601775328 ps}
diff --git a/projects/mips_sys/src/.directory_history b/projects/mips_sys/src/.directory_history
deleted file mode 100644
index 2f56f3d..0000000
--- a/projects/mips_sys/src/.directory_history
+++ /dev/null
@@ -1,4 +0,0 @@
-VHDL/projects/mips_sys/src/async_defs.vhd
-
-VHDL/projects/mips_sys/src/sys_types.vhd
-VHDL/projects/mips_sys/src/async_defs.vhd
diff --git a/projects/mips_sys/src/bootloader.ROM.vhd b/projects/mips_sys/src/bootloader.ROM.vhd
deleted file mode 100644
index 03235fc..0000000
--- a/projects/mips_sys/src/bootloader.ROM.vhd
+++ /dev/null
@@ -1,2082 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-ENTITY rom IS
-	Port
-	(
-		clk		: in  STD_LOGIC;
-		ce		: in  STD_LOGIC;
-		addr		: in  unsigned(31 downto 0);
-		dout		: out unsigned(31 downto 0)
-	);
-END rom;
-
-ARCHITECTURE data OF rom IS
-
-	subtype word_t is unsigned(31 downto 0);
-	type word_array_t is array (0 to 2047) of word_t;
-	constant word_array : word_array_t :=
-	(
-
-		X"3C1A1040", -- 00000000
-		X"375A000C", -- 00000004
-		X"409A6000", -- 00000008
-		X"241A0000", -- 0000000C
-		X"409A6800", -- 00000010
-		X"401A7800", -- 00000014
-		X"00000000", -- 00000018
-		X"409AF800", -- 0000001C
-		X"3C1ABFC0", -- 00000020
-		X"275A01C4", -- 00000024
-		X"03400008", -- 00000028
-		X"00000000", -- 0000002C
-		X"00000000", -- 00000030
-		X"00000000", -- 00000034
-		X"00000000", -- 00000038
-		X"00000000", -- 0000003C
-		X"00000000", -- 00000040
-		X"00000000", -- 00000044
-		X"00000000", -- 00000048
-		X"00000000", -- 0000004C
-		X"00000000", -- 00000050
-		X"00000000", -- 00000054
-		X"00000000", -- 00000058
-		X"00000000", -- 0000005C
-		X"00000000", -- 00000060
-		X"00000000", -- 00000064
-		X"00000000", -- 00000068
-		X"00000000", -- 0000006C
-		X"00000000", -- 00000070
-		X"00000000", -- 00000074
-		X"00000000", -- 00000078
-		X"00000000", -- 0000007C
-		X"00000000", -- 00000080
-		X"00000000", -- 00000084
-		X"00000000", -- 00000088
-		X"00000000", -- 0000008C
-		X"00000000", -- 00000090
-		X"00000000", -- 00000094
-		X"00000000", -- 00000098
-		X"00000000", -- 0000009C
-		X"00000000", -- 000000A0
-		X"00000000", -- 000000A4
-		X"00000000", -- 000000A8
-		X"00000000", -- 000000AC
-		X"00000000", -- 000000B0
-		X"00000000", -- 000000B4
-		X"00000000", -- 000000B8
-		X"00000000", -- 000000BC
-		X"00000000", -- 000000C0
-		X"00000000", -- 000000C4
-		X"00000000", -- 000000C8
-		X"00000000", -- 000000CC
-		X"00000000", -- 000000D0
-		X"00000000", -- 000000D4
-		X"00000000", -- 000000D8
-		X"00000000", -- 000000DC
-		X"00000000", -- 000000E0
-		X"00000000", -- 000000E4
-		X"00000000", -- 000000E8
-		X"00000000", -- 000000EC
-		X"00000000", -- 000000F0
-		X"00000000", -- 000000F4
-		X"00000000", -- 000000F8
-		X"00000000", -- 000000FC
-		X"00000000", -- 00000100
-		X"00000000", -- 00000104
-		X"00000000", -- 00000108
-		X"00000000", -- 0000010C
-		X"00000000", -- 00000110
-		X"00000000", -- 00000114
-		X"00000000", -- 00000118
-		X"00000000", -- 0000011C
-		X"00000000", -- 00000120
-		X"00000000", -- 00000124
-		X"00000000", -- 00000128
-		X"00000000", -- 0000012C
-		X"00000000", -- 00000130
-		X"00000000", -- 00000134
-		X"00000000", -- 00000138
-		X"00000000", -- 0000013C
-		X"00000000", -- 00000140
-		X"00000000", -- 00000144
-		X"00000000", -- 00000148
-		X"00000000", -- 0000014C
-		X"00000000", -- 00000150
-		X"00000000", -- 00000154
-		X"00000000", -- 00000158
-		X"00000000", -- 0000015C
-		X"00000000", -- 00000160
-		X"00000000", -- 00000164
-		X"00000000", -- 00000168
-		X"00000000", -- 0000016C
-		X"00000000", -- 00000170
-		X"00000000", -- 00000174
-		X"00000000", -- 00000178
-		X"00000000", -- 0000017C
-		X"401A6800", -- 00000180
-		X"3C1BA000", -- 00000184
-		X"277B0000", -- 00000188
-		X"001AD082", -- 0000018C
-		X"335A000F", -- 00000190
-		X"035BD025", -- 00000194
-		X"AF7A0000", -- 00000198
-		X"401A6800", -- 0000019C
-		X"00000000", -- 000001A0
-		X"001AD202", -- 000001A4
-		X"335A00FF", -- 000001A8
-		X"1740FFFB", -- 000001AC
-		X"00000000", -- 000001B0
-		X"401A7000", -- 000001B4
-		X"00000000", -- 000001B8
-		X"03400008", -- 000001BC
-		X"42000010", -- 000001C0
-		X"3C1AA001", -- 000001C4
-		X"275A0008", -- 000001C8
-		X"241B000D", -- 000001CC
-		X"A35B0000", -- 000001D0
-		X"3C1D8000", -- 000001D4
-		X"27BDFFF0", -- 000001D8
-		X"241A0005", -- 000001DC
-		X"1340009F", -- 000001E0
-		X"241AFFFB", -- 000001E4
-		X"1340009D", -- 000001E8
-		X"241A0000", -- 000001EC
-		X"13400003", -- 000001F0
-		X"00000000", -- 000001F4
-		X"0BF00118", -- 000001F8
-		X"00000000", -- 000001FC
-		X"241A0005", -- 00000200
-		X"241B0006", -- 00000204
-		X"135B0095", -- 00000208
-		X"241AFFFB", -- 0000020C
-		X"135B0093", -- 00000210
-		X"241A0000", -- 00000214
-		X"135B0091", -- 00000218
-		X"241A0006", -- 0000021C
-		X"135B0003", -- 00000220
-		X"00000000", -- 00000224
-		X"0BF00118", -- 00000228
-		X"00000000", -- 0000022C
-		X"241AFFFB", -- 00000230
-		X"0741008A", -- 00000234
-		X"241A0005", -- 00000238
-		X"07410002", -- 0000023C
-		X"00000000", -- 00000240
-		X"0BF00118", -- 00000244
-		X"241A0000", -- 00000248
-		X"07410002", -- 0000024C
-		X"00000000", -- 00000250
-		X"0BF00118", -- 00000254
-		X"241AFFFB", -- 00000258
-		X"1F400080", -- 0000025C
-		X"241A0000", -- 00000260
-		X"1F40007E", -- 00000264
-		X"241A0005", -- 00000268
-		X"1F400002", -- 0000026C
-		X"00000000", -- 00000270
-		X"0BF00118", -- 00000274
-		X"241A0005", -- 00000278
-		X"1B400078", -- 0000027C
-		X"241A0000", -- 00000280
-		X"1B400002", -- 00000284
-		X"00000000", -- 00000288
-		X"0BF00118", -- 0000028C
-		X"241AFFFB", -- 00000290
-		X"1B400002", -- 00000294
-		X"00000000", -- 00000298
-		X"0BF00118", -- 0000029C
-		X"241A0005", -- 000002A0
-		X"0740006E", -- 000002A4
-		X"241A0000", -- 000002A8
-		X"0740006C", -- 000002AC
-		X"241AFFFB", -- 000002B0
-		X"07400002", -- 000002B4
-		X"00000000", -- 000002B8
-		X"0BF00118", -- 000002BC
-		X"241A0005", -- 000002C0
-		X"241B0006", -- 000002C4
-		X"175B0002", -- 000002C8
-		X"00000000", -- 000002CC
-		X"0BF00118", -- 000002D0
-		X"241AFFFB", -- 000002D4
-		X"175B0002", -- 000002D8
-		X"00000000", -- 000002DC
-		X"0BF00118", -- 000002E0
-		X"241AFFFA", -- 000002E4
-		X"175B0002", -- 000002E8
-		X"00000000", -- 000002EC
-		X"0BF00118", -- 000002F0
-		X"241A0000", -- 000002F4
-		X"175B0002", -- 000002F8
-		X"00000000", -- 000002FC
-		X"0BF00118", -- 00000300
-		X"241A0006", -- 00000304
-		X"175B0055", -- 00000308
-		X"241A0005", -- 0000030C
-		X"17400002", -- 00000310
-		X"00000000", -- 00000314
-		X"0BF00118", -- 00000318
-		X"241AFFFB", -- 0000031C
-		X"17400002", -- 00000320
-		X"00000000", -- 00000324
-		X"0BF00118", -- 00000328
-		X"241A0000", -- 0000032C
-		X"1740004B", -- 00000330
-		X"241B0005", -- 00000334
-		X"2F7A0006", -- 00000338
-		X"2F7AFFFA", -- 0000033C
-		X"241BFFFB", -- 00000340
-		X"2F7A0006", -- 00000344
-		X"2F7AFFFA", -- 00000348
-		X"241B0006", -- 0000034C
-		X"2F7A0005", -- 00000350
-		X"2F7AFFFB", -- 00000354
-		X"241BFFFA", -- 00000358
-		X"2F7A0005", -- 0000035C
-		X"2F7AFFFB", -- 00000360
-		X"241B0005", -- 00000364
-		X"2B7A0006", -- 00000368
-		X"2B7AFFFA", -- 0000036C
-		X"241BFFFB", -- 00000370
-		X"2B7A0006", -- 00000374
-		X"2B7AFFFA", -- 00000378
-		X"241B0006", -- 0000037C
-		X"2B7A0005", -- 00000380
-		X"2B7AFFFB", -- 00000384
-		X"241BFFFA", -- 00000388
-		X"2B7A0005", -- 0000038C
-		X"2B7AFFFB", -- 00000390
-		X"241A0005", -- 00000394
-		X"241B0006", -- 00000398
-		X"035BD02B", -- 0000039C
-		X"241A0005", -- 000003A0
-		X"241BFFFA", -- 000003A4
-		X"035BD02B", -- 000003A8
-		X"241AFFFB", -- 000003AC
-		X"241B0006", -- 000003B0
-		X"035BD02B", -- 000003B4
-		X"241AFFFB", -- 000003B8
-		X"241BFFFA", -- 000003BC
-		X"035BD02B", -- 000003C0
-		X"241A0006", -- 000003C4
-		X"241B0005", -- 000003C8
-		X"035BD02B", -- 000003CC
-		X"241A0006", -- 000003D0
-		X"241BFFFB", -- 000003D4
-		X"035BD02B", -- 000003D8
-		X"241AFFFA", -- 000003DC
-		X"241B0005", -- 000003E0
-		X"035BD02B", -- 000003E4
-		X"241AFFFA", -- 000003E8
-		X"241BFFFB", -- 000003EC
-		X"035BD02B", -- 000003F0
-		X"241A0005", -- 000003F4
-		X"241B0006", -- 000003F8
-		X"035BD02A", -- 000003FC
-		X"241A0005", -- 00000400
-		X"241BFFFA", -- 00000404
-		X"035BD02A", -- 00000408
-		X"241AFFFB", -- 0000040C
-		X"241B0006", -- 00000410
-		X"035BD02A", -- 00000414
-		X"241AFFFB", -- 00000418
-		X"241BFFFA", -- 0000041C
-		X"035BD02A", -- 00000420
-		X"241A0006", -- 00000424
-		X"241B0005", -- 00000428
-		X"035BD02A", -- 0000042C
-		X"241A0006", -- 00000430
-		X"241BFFFB", -- 00000434
-		X"035BD02A", -- 00000438
-		X"241AFFFA", -- 0000043C
-		X"241B0005", -- 00000440
-		X"035BD02A", -- 00000444
-		X"241AFFFA", -- 00000448
-		X"241BFFFB", -- 0000044C
-		X"035BD02A", -- 00000450
-		X"3C1ABFC0", -- 00000454
-		X"275A0FC8", -- 00000458
-		X"0340F809", -- 0000045C
-		X"00000000", -- 00000460
-		X"0BF00118", -- 00000464
-		X"00000000", -- 00000468
-		X"40026000", -- 0000046C
-		X"03E00008", -- 00000470
-		X"00000000", -- 00000474
-		X"40846000", -- 00000478
-		X"03E00008", -- 0000047C
-		X"00000000", -- 00000480
-		X"40026800", -- 00000484
-		X"03E00008", -- 00000488
-		X"00000000", -- 0000048C
-		X"40846800", -- 00000490
-		X"03E00008", -- 00000494
-		X"00000000", -- 00000498
-		X"40027800", -- 0000049C
-		X"03E00008", -- 000004A0
-		X"00000000", -- 000004A4
-		X"3C02A001", -- 000004A8
-		X"34430004", -- 000004AC
-		X"8C620000", -- 000004B0
-		X"00000000", -- 000004B4
-		X"30420010", -- 000004B8
-		X"1040FFFC", -- 000004BC
-		X"3C02A001", -- 000004C0
-		X"8C420000", -- 000004C4
-		X"00000000", -- 000004C8
-		X"00021600", -- 000004CC
-		X"03E00008", -- 000004D0
-		X"00021603", -- 000004D4
-		X"00042600", -- 000004D8
-		X"3C02A001", -- 000004DC
-		X"00042603", -- 000004E0
-		X"34430004", -- 000004E4
-		X"8C620000", -- 000004E8
-		X"00000000", -- 000004EC
-		X"30420002", -- 000004F0
-		X"1440FFFC", -- 000004F4
-		X"3C02A001", -- 000004F8
-		X"AC440000", -- 000004FC
-		X"03E00008", -- 00000500
-		X"00000000", -- 00000504
-		X"00042600", -- 00000508
-		X"00042603", -- 0000050C
-		X"2402000A", -- 00000510
-		X"1482000A", -- 00000514
-		X"3C02A001", -- 00000518
-		X"34430004", -- 0000051C
-		X"8C620000", -- 00000520
-		X"00000000", -- 00000524
-		X"30420002", -- 00000528
-		X"1440FFFC", -- 0000052C
-		X"3C02A001", -- 00000530
-		X"2403000D", -- 00000534
-		X"AC430000", -- 00000538
-		X"3C02A001", -- 0000053C
-		X"34430004", -- 00000540
-		X"8C620000", -- 00000544
-		X"00000000", -- 00000548
-		X"30420002", -- 0000054C
-		X"1440FFFC", -- 00000550
-		X"3C02A001", -- 00000554
-		X"AC440000", -- 00000558
-		X"03E00008", -- 0000055C
-		X"00000000", -- 00000560
-		X"3C02A001", -- 00000564
-		X"34470004", -- 00000568
-		X"00802821", -- 0000056C
-		X"2409000A", -- 00000570
-		X"3C06A001", -- 00000574
-		X"0BF0016F", -- 00000578
-		X"2408000D", -- 0000057C
-		X"14690007", -- 00000580
-		X"00000000", -- 00000584
-		X"8CE20000", -- 00000588
-		X"00000000", -- 0000058C
-		X"30420002", -- 00000590
-		X"1440FFFC", -- 00000594
-		X"00000000", -- 00000598
-		X"ACC80000", -- 0000059C
-		X"8CE20000", -- 000005A0
-		X"00000000", -- 000005A4
-		X"30420002", -- 000005A8
-		X"1440FFFC", -- 000005AC
-		X"00000000", -- 000005B0
-		X"ACC30000", -- 000005B4
-		X"24A50001", -- 000005B8
-		X"80A30000", -- 000005BC
-		X"00000000", -- 000005C0
-		X"1460FFEE", -- 000005C4
-		X"00A41023", -- 000005C8
-		X"03E00008", -- 000005CC
-		X"00000000", -- 000005D0
-		X"00042600", -- 000005D4
-		X"3C02A001", -- 000005D8
-		X"00042603", -- 000005DC
-		X"344A0004", -- 000005E0
-		X"00003821", -- 000005E4
-		X"3C09A001", -- 000005E8
-		X"24080002", -- 000005EC
-		X"308200FF", -- 000005F0
-		X"00022902", -- 000005F4
-		X"00041100", -- 000005F8
-		X"00022600", -- 000005FC
-		X"2CA3000A", -- 00000600
-		X"00042603", -- 00000604
-		X"14600002", -- 00000608
-		X"24A60030", -- 0000060C
-		X"24A60037", -- 00000610
-		X"8D420000", -- 00000614
-		X"00000000", -- 00000618
-		X"30420002", -- 0000061C
-		X"1440FFFC", -- 00000620
-		X"00061600", -- 00000624
-		X"00021603", -- 00000628
-		X"24E70001", -- 0000062C
-		X"AD220000", -- 00000630
-		X"14E8FFEF", -- 00000634
-		X"308200FF", -- 00000638
-		X"03E00008", -- 0000063C
-		X"00000000", -- 00000640
-		X"27BDFFE0", -- 00000644
-		X"AFB20018", -- 00000648
-		X"AFB10014", -- 0000064C
-		X"AFB00010", -- 00000650
-		X"AFBF001C", -- 00000654
-		X"00808821", -- 00000658
-		X"00008021", -- 0000065C
-		X"24120004", -- 00000660
-		X"00112603", -- 00000664
-		X"0FF00175", -- 00000668
-		X"26100001", -- 0000066C
-		X"1612FFFC", -- 00000670
-		X"00118A00", -- 00000674
-		X"8FBF001C", -- 00000678
-		X"8FB20018", -- 0000067C
-		X"8FB10014", -- 00000680
-		X"8FB00010", -- 00000684
-		X"03E00008", -- 00000688
-		X"27BD0020", -- 0000068C
-		X"8C840000", -- 00000690
-		X"3C020070", -- 00000694
-		X"34420070", -- 00000698
-		X"3C0300FF", -- 0000069C
-		X"AC820000", -- 000006A0
-		X"346300FF", -- 000006A4
-		X"8C820000", -- 000006A8
-		X"AC830000", -- 000006AC
-		X"03E00008", -- 000006B0
-		X"00000000", -- 000006B4
-		X"AC850000", -- 000006B8
-		X"2482001C", -- 000006BC
-		X"0BF001B4", -- 000006C0
-		X"24840004", -- 000006C4
-		X"A0800000", -- 000006C8
-		X"24840001", -- 000006CC
-		X"1482FFFD", -- 000006D0
-		X"00000000", -- 000006D4
-		X"03E00008", -- 000006D8
-		X"00000000", -- 000006DC
-		X"3C02BFC0", -- 000006E0
-		X"24431580", -- 000006E4
-		X"8C421580", -- 000006E8
-		X"27BDFFF0", -- 000006EC
-		X"00804021", -- 000006F0
-		X"8D070000", -- 000006F4
-		X"8C640008", -- 000006F8
-		X"AFA20000", -- 000006FC
-		X"8C630004", -- 00000700
-		X"3C020098", -- 00000704
-		X"34420098", -- 00000708
-		X"AFA30004", -- 0000070C
-		X"AFA40008", -- 00000710
-		X"00002821", -- 00000714
-		X"ACE20000", -- 00000718
-		X"2406000C", -- 0000071C
-		X"00E51021", -- 00000720
-		X"03A51821", -- 00000724
-		X"90440040", -- 00000728
-		X"90620000", -- 0000072C
-		X"00000000", -- 00000730
-		X"10820003", -- 00000734
-		X"24A50001", -- 00000738
-		X"0BF00213", -- 0000073C
-		X"2405FFFF", -- 00000740
-		X"14A6FFF7", -- 00000744
-		X"00E51021", -- 00000748
-		X"3C0200FF", -- 0000074C
-		X"344200FF", -- 00000750
-		X"ACE20000", -- 00000754
-		X"3C020090", -- 00000758
-		X"34420090", -- 0000075C
-		X"ACE20000", -- 00000760
-		X"94E4009C", -- 00000764
-		X"24030002", -- 00000768
-		X"24020020", -- 0000076C
-		X"AD030004", -- 00000770
-		X"AD030018", -- 00000774
-		X"AD020014", -- 00000778
-		X"3084FFFF", -- 0000077C
-		X"0BF001E6", -- 00000780
-		X"00001821", -- 00000784
-		X"8D020004", -- 00000788
-		X"00000000", -- 0000078C
-		X"00021040", -- 00000790
-		X"AD020004", -- 00000794
-		X"0064102B", -- 00000798
-		X"1440FFFA", -- 0000079C
-		X"24630001", -- 000007A0
-		X"94E200AC", -- 000007A4
-		X"94E300A8", -- 000007A8
-		X"3042FFFF", -- 000007AC
-		X"8D040018", -- 000007B0
-		X"3063FFFF", -- 000007B4
-		X"00021200", -- 000007B8
-		X"00432825", -- 000007BC
-		X"AD040010", -- 000007C0
-		X"0BF001F7", -- 000007C4
-		X"00001821", -- 000007C8
-		X"8D020010", -- 000007CC
-		X"00000000", -- 000007D0
-		X"00021040", -- 000007D4
-		X"AD020010", -- 000007D8
-		X"0065102B", -- 000007DC
-		X"1440FFFA", -- 000007E0
-		X"24630001", -- 000007E4
-		X"94E200B8", -- 000007E8
-		X"94E400B4", -- 000007EC
-		X"3042FFFF", -- 000007F0
-		X"3084FFFF", -- 000007F4
-		X"00021200", -- 000007F8
-		X"8D060018", -- 000007FC
-		X"00441025", -- 00000800
-		X"24420001", -- 00000804
-		X"00460018", -- 00000808
-		X"94E300C0", -- 0000080C
-		X"94E500BC", -- 00000810
-		X"3063FFFF", -- 00000814
-		X"30A5FFFF", -- 00000818
-		X"00031A00", -- 0000081C
-		X"00651825", -- 00000820
-		X"00062200", -- 00000824
-		X"00002821", -- 00000828
-		X"00001012", -- 0000082C
-		X"AD02000C", -- 00000830
-		X"3C0200FF", -- 00000834
-		X"00830018", -- 00000838
-		X"344200FF", -- 0000083C
-		X"00002012", -- 00000840
-		X"AD040008", -- 00000844
-		X"ACE20000", -- 00000848
-		X"00A01021", -- 0000084C
-		X"03E00008", -- 00000850
-		X"27BD0010", -- 00000854
-		X"8C820004", -- 00000858
-		X"00A03021", -- 0000085C
-		X"00021082", -- 00000860
-		X"00A2102B", -- 00000864
-		X"8C850000", -- 00000868
-		X"10400018", -- 0000086C
-		X"2403FFFF", -- 00000870
-		X"8C82000C", -- 00000874
-		X"00000000", -- 00000878
-		X"2442FFFF", -- 0000087C
-		X"00021400", -- 00000880
-		X"00C21024", -- 00000884
-		X"00021080", -- 00000888
-		X"00A22021", -- 0000088C
-		X"3C020020", -- 00000890
-		X"34420020", -- 00000894
-		X"AC820000", -- 00000898
-		X"3C0200D0", -- 0000089C
-		X"344200D0", -- 000008A0
-		X"AC820000", -- 000008A4
-		X"3C020080", -- 000008A8
-		X"34430080", -- 000008AC
-		X"8C820000", -- 000008B0
-		X"00000000", -- 000008B4
-		X"00431024", -- 000008B8
-		X"1443FFFC", -- 000008BC
-		X"3C0200FF", -- 000008C0
-		X"344200FF", -- 000008C4
-		X"AC820000", -- 000008C8
-		X"00001821", -- 000008CC
-		X"03E00008", -- 000008D0
-		X"00601021", -- 000008D4
-		X"8C820004", -- 000008D8
-		X"00000000", -- 000008DC
-		X"00021082", -- 000008E0
-		X"00A2102B", -- 000008E4
-		X"8C840000", -- 000008E8
-		X"10400011", -- 000008EC
-		X"2403FFFF", -- 000008F0
-		X"00051080", -- 000008F4
-		X"00822021", -- 000008F8
-		X"3C020040", -- 000008FC
-		X"34420040", -- 00000900
-		X"AC820000", -- 00000904
-		X"3C020080", -- 00000908
-		X"AC860000", -- 0000090C
-		X"34430080", -- 00000910
-		X"8C820000", -- 00000914
-		X"00000000", -- 00000918
-		X"00431024", -- 0000091C
-		X"1443FFFC", -- 00000920
-		X"3C0200FF", -- 00000924
-		X"344200FF", -- 00000928
-		X"AC820000", -- 0000092C
-		X"00001821", -- 00000930
-		X"03E00008", -- 00000934
-		X"00601021", -- 00000938
-		X"8C820004", -- 0000093C
-		X"27BDFFF0", -- 00000940
-		X"00021082", -- 00000944
-		X"00A2102B", -- 00000948
-		X"AFB2000C", -- 0000094C
-		X"AFB10008", -- 00000950
-		X"AFB00004", -- 00000954
-		X"00807021", -- 00000958
-		X"00C09021", -- 0000095C
-		X"8C8F0000", -- 00000960
-		X"10400045", -- 00000964
-		X"2403FFFF", -- 00000968
-		X"8C82000C", -- 0000096C
-		X"00006021", -- 00000970
-		X"2442FFFF", -- 00000974
-		X"0002C400", -- 00000978
-		X"3C0200E8", -- 0000097C
-		X"345100E8", -- 00000980
-		X"3C020080", -- 00000984
-		X"344D0080", -- 00000988
-		X"3C0200D0", -- 0000098C
-		X"345000D0", -- 00000990
-		X"3C0200FF", -- 00000994
-		X"344600FF", -- 00000998
-		X"0BF0029C", -- 0000099C
-		X"3C190001", -- 000009A0
-		X"00651023", -- 000009A4
-		X"00595021", -- 000009A8
-		X"00EA102B", -- 000009AC
-		X"10400002", -- 000009B0
-		X"00031080", -- 000009B4
-		X"00E05021", -- 000009B8
-		X"0BF0029A", -- 000009BC
-		X"01E25821", -- 000009C0
-		X"AD710000", -- 000009C4
-		X"8D620000", -- 000009C8
-		X"00000000", -- 000009CC
-		X"004D1024", -- 000009D0
-		X"144DFFFC", -- 000009D4
-		X"00000000", -- 000009D8
-		X"8DC20010", -- 000009DC
-		X"00000000", -- 000009E0
-		X"00021882", -- 000009E4
-		X"006A102B", -- 000009E8
-		X"10400002", -- 000009EC
-		X"01404021", -- 000009F0
-		X"00604021", -- 000009F4
-		X"2503FFFF", -- 000009F8
-		X"00031400", -- 000009FC
-		X"00431025", -- 00000A00
-		X"00052080", -- 00000A04
-		X"000C1880", -- 00000A08
-		X"02434821", -- 00000A0C
-		X"AD620000", -- 00000A10
-		X"01E42021", -- 00000A14
-		X"0BF0028C", -- 00000A18
-		X"00001821", -- 00000A1C
-		X"8D220000", -- 00000A20
-		X"25290004", -- 00000A24
-		X"AC820000", -- 00000A28
-		X"24840004", -- 00000A2C
-		X"0068102B", -- 00000A30
-		X"1440FFFA", -- 00000A34
-		X"24630001", -- 00000A38
-		X"01886021", -- 00000A3C
-		X"AD700000", -- 00000A40
-		X"8D620000", -- 00000A44
-		X"00000000", -- 00000A48
-		X"004D1024", -- 00000A4C
-		X"144DFFFC", -- 00000A50
-		X"00000000", -- 00000A54
-		X"00E83823", -- 00000A58
-		X"00A82821", -- 00000A5C
-		X"01485023", -- 00000A60
-		X"AD660000", -- 00000A64
-		X"1540FFD6", -- 00000A68
-		X"00000000", -- 00000A6C
-		X"14E0FFCC", -- 00000A70
-		X"00B81824", -- 00000A74
-		X"00001821", -- 00000A78
-		X"00601021", -- 00000A7C
-		X"8FB2000C", -- 00000A80
-		X"8FB10008", -- 00000A84
-		X"8FB00004", -- 00000A88
-		X"03E00008", -- 00000A8C
-		X"27BD0010", -- 00000A90
-		X"AC850000", -- 00000A94
-		X"24820004", -- 00000A98
-		X"0BF002AB", -- 00000A9C
-		X"2483001C", -- 00000AA0
-		X"A0400000", -- 00000AA4
-		X"24420001", -- 00000AA8
-		X"1443FFFD", -- 00000AAC
-		X"00000000", -- 00000AB0
-		X"0BF001B8", -- 00000AB4
-		X"00000000", -- 00000AB8
-		X"27BDFFE0", -- 00000ABC
-		X"AFB20018", -- 00000AC0
-		X"AFB10014", -- 00000AC4
-		X"AFB00010", -- 00000AC8
-		X"AFBF001C", -- 00000ACC
-		X"00809021", -- 00000AD0
-		X"00C58821", -- 00000AD4
-		X"0BF002BD", -- 00000AD8
-		X"00A08021", -- 00000ADC
-		X"0FF00216", -- 00000AE0
-		X"00000000", -- 00000AE4
-		X"8E420008", -- 00000AE8
-		X"00000000", -- 00000AEC
-		X"02028021", -- 00000AF0
-		X"00102FC3", -- 00000AF4
-		X"00052F82", -- 00000AF8
-		X"00B02821", -- 00000AFC
-		X"0211102B", -- 00000B00
-		X"00052883", -- 00000B04
-		X"1440FFF5", -- 00000B08
-		X"02402021", -- 00000B0C
-		X"8FBF001C", -- 00000B10
-		X"00001021", -- 00000B14
-		X"8FB20018", -- 00000B18
-		X"8FB10014", -- 00000B1C
-		X"8FB00010", -- 00000B20
-		X"03E00008", -- 00000B24
-		X"27BD0020", -- 00000B28
-		X"00052882", -- 00000B2C
-		X"0BF0024F", -- 00000B30
-		X"00073882", -- 00000B34
-		X"8C820000", -- 00000B38
-		X"00002021", -- 00000B3C
-		X"0BF002D7", -- 00000B40
-		X"00454021", -- 00000B44
-		X"90630000", -- 00000B48
-		X"90A20000", -- 00000B4C
-		X"00000000", -- 00000B50
-		X"14620006", -- 00000B54
-		X"2402FFFF", -- 00000B58
-		X"0087102B", -- 00000B5C
-		X"01041821", -- 00000B60
-		X"00C42821", -- 00000B64
-		X"1440FFF7", -- 00000B68
-		X"24840001", -- 00000B6C
-		X"03E00008", -- 00000B70
-		X"00000000", -- 00000B74
-		X"90830000", -- 00000B78
-		X"00000000", -- 00000B7C
-		X"2C620041", -- 00000B80
-		X"14400002", -- 00000B84
-		X"2462FFD0", -- 00000B88
-		X"2462FFC9", -- 00000B8C
-		X"90840001", -- 00000B90
-		X"304200FF", -- 00000B94
-		X"304300FF", -- 00000B98
-		X"2C820041", -- 00000B9C
-		X"14400003", -- 00000BA0
-		X"00000000", -- 00000BA4
-		X"0BF002ED", -- 00000BA8
-		X"2482FFC9", -- 00000BAC
-		X"2482FFD0", -- 00000BB0
-		X"304400FF", -- 00000BB4
-		X"00031100", -- 00000BB8
-		X"00821025", -- 00000BBC
-		X"03E00008", -- 00000BC0
-		X"304200FF", -- 00000BC4
-		X"10C00094", -- 00000BC8
-		X"00805021", -- 00000BCC
-		X"24020003", -- 00000BD0
-		X"AC820008", -- 00000BD4
-		X"90A40001", -- 00000BD8
-		X"00000000", -- 00000BDC
-		X"2482FFCF", -- 00000BE0
-		X"304200FF", -- 00000BE4
-		X"2C420003", -- 00000BE8
-		X"10400005", -- 00000BEC
-		X"2482FFC9", -- 00000BF0
-		X"24020002", -- 00000BF4
-		X"AD420008", -- 00000BF8
-		X"0BF0030F", -- 00000BFC
-		X"2489FFD1", -- 00000C00
-		X"304200FF", -- 00000C04
-		X"2C420003", -- 00000C08
-		X"10400006", -- 00000C0C
-		X"24020030", -- 00000C10
-		X"2402003B", -- 00000C14
-		X"00444823", -- 00000C18
-		X"24020004", -- 00000C1C
-		X"0BF0030F", -- 00000C20
-		X"AD420008", -- 00000C24
-		X"14820004", -- 00000C28
-		X"00004821", -- 00000C2C
-		X"24020001", -- 00000C30
-		X"AD420008", -- 00000C34
-		X"24090002", -- 00000C38
-		X"90A30002", -- 00000C3C
-		X"00000000", -- 00000C40
-		X"2C620041", -- 00000C44
-		X"10400003", -- 00000C48
-		X"24A40002", -- 00000C4C
-		X"0BF00317", -- 00000C50
-		X"2462FFD0", -- 00000C54
-		X"2462FFC9", -- 00000C58
-		X"90830001", -- 00000C5C
-		X"304200FF", -- 00000C60
-		X"304400FF", -- 00000C64
-		X"2C620041", -- 00000C68
-		X"10400002", -- 00000C6C
-		X"2462FFC9", -- 00000C70
-		X"2462FFD0", -- 00000C74
-		X"304300FF", -- 00000C78
-		X"00041100", -- 00000C7C
-		X"00621025", -- 00000C80
-		X"304200FF", -- 00000C84
-		X"AD420004", -- 00000C88
-		X"AD400000", -- 00000C8C
-		X"00405821", -- 00000C90
-		X"00A03021", -- 00000C94
-		X"0BF00343", -- 00000C98
-		X"00003821", -- 00000C9C
-		X"90C20004", -- 00000CA0
-		X"00000000", -- 00000CA4
-		X"2443FFC9", -- 00000CA8
-		X"2444FFD0", -- 00000CAC
-		X"2C420041", -- 00000CB0
-		X"10400002", -- 00000CB4
-		X"306300FF", -- 00000CB8
-		X"308300FF", -- 00000CBC
-		X"90C20005", -- 00000CC0
-		X"306800FF", -- 00000CC4
-		X"2444FFC9", -- 00000CC8
-		X"2443FFD0", -- 00000CCC
-		X"2C420041", -- 00000CD0
-		X"10400002", -- 00000CD4
-		X"308400FF", -- 00000CD8
-		X"306400FF", -- 00000CDC
-		X"8D430000", -- 00000CE0
-		X"00081100", -- 00000CE4
-		X"00821025", -- 00000CE8
-		X"304200FF", -- 00000CEC
-		X"00031A00", -- 00000CF0
-		X"004B2021", -- 00000CF4
-		X"00431025", -- 00000CF8
-		X"AD420000", -- 00000CFC
-		X"308B00FF", -- 00000D00
-		X"24E70001", -- 00000D04
-		X"24C60002", -- 00000D08
-		X"00E9102A", -- 00000D0C
-		X"1440FFE3", -- 00000D10
-		X"25220002", -- 00000D14
-		X"8D440004", -- 00000D18
-		X"00021040", -- 00000D1C
-		X"00091827", -- 00000D20
-		X"00832021", -- 00000D24
-		X"00A21021", -- 00000D28
-		X"AD440004", -- 00000D2C
-		X"AD42000C", -- 00000D30
-		X"0BF00367", -- 00000D34
-		X"00003021", -- 00000D38
-		X"90E20000", -- 00000D3C
-		X"00000000", -- 00000D40
-		X"2444FFC9", -- 00000D44
-		X"2445FFD0", -- 00000D48
-		X"2C420041", -- 00000D4C
-		X"10400002", -- 00000D50
-		X"308400FF", -- 00000D54
-		X"30A400FF", -- 00000D58
-		X"90E20001", -- 00000D5C
-		X"308700FF", -- 00000D60
-		X"2445FFC9", -- 00000D64
-		X"2444FFD0", -- 00000D68
-		X"2C420041", -- 00000D6C
-		X"14400002", -- 00000D70
-		X"308400FF", -- 00000D74
-		X"30A400FF", -- 00000D78
-		X"00071100", -- 00000D7C
-		X"00821025", -- 00000D80
-		X"304200FF", -- 00000D84
-		X"00661821", -- 00000D88
-		X"004B2021", -- 00000D8C
-		X"A0620000", -- 00000D90
-		X"308B00FF", -- 00000D94
-		X"24C60001", -- 00000D98
-		X"8D420004", -- 00000D9C
-		X"8D43000C", -- 00000DA0
-		X"00062040", -- 00000DA4
-		X"00C2102A", -- 00000DA8
-		X"1440FFE3", -- 00000DAC
-		X"00643821", -- 00000DB0
-		X"90E40000", -- 00000DB4
-		X"00000000", -- 00000DB8
-		X"2C820041", -- 00000DBC
-		X"10400003", -- 00000DC0
-		X"00E01821", -- 00000DC4
-		X"0BF00375", -- 00000DC8
-		X"2482FFD0", -- 00000DCC
-		X"2482FFC9", -- 00000DD0
-		X"90630001", -- 00000DD4
-		X"304200FF", -- 00000DD8
-		X"304400FF", -- 00000DDC
-		X"2C620041", -- 00000DE0
-		X"10400002", -- 00000DE4
-		X"2462FFC9", -- 00000DE8
-		X"2462FFD0", -- 00000DEC
-		X"304200FF", -- 00000DF0
-		X"00041900", -- 00000DF4
-		X"00431825", -- 00000DF8
-		X"000B1027", -- 00000DFC
-		X"304200FF", -- 00000E00
-		X"306300FF", -- 00000E04
-		X"14430004", -- 00000E08
-		X"00000000", -- 00000E0C
-		X"8D420008", -- 00000E10
-		X"03E00008", -- 00000E14
-		X"00000000", -- 00000E18
-		X"03E00008", -- 00000E1C
-		X"00001021", -- 00000E20
-		X"00800008", -- 00000E24
-		X"00000000", -- 00000E28
-		X"03E00008", -- 00000E2C
-		X"00000000", -- 00000E30
-		X"401A6000", -- 00000E34
-		X"3C1BFFBF", -- 00000E38
-		X"377BFFFF", -- 00000E3C
-		X"035BD024", -- 00000E40
-		X"409A6000", -- 00000E44
-		X"00800008", -- 00000E48
-		X"42000010", -- 00000E4C
-		X"03E00008", -- 00000E50
-		X"00000000", -- 00000E54
-		X"27BDFFC0", -- 00000E58
-		X"AFB20038", -- 00000E5C
-		X"3C05BFC0", -- 00000E60
-		X"27B20010", -- 00000E64
-		X"24A51670", -- 00000E68
-		X"2406001C", -- 00000E6C
-		X"02402021", -- 00000E70
-		X"AFBF003C", -- 00000E74
-		X"AFB10034", -- 00000E78
-		X"0FF004BF", -- 00000E7C
-		X"AFB00030", -- 00000E80
-		X"0FF0011B", -- 00000E84
-		X"00000000", -- 00000E88
-		X"3C04BFC0", -- 00000E8C
-		X"00408021", -- 00000E90
-		X"0FF00159", -- 00000E94
-		X"2484158C", -- 00000E98
-		X"0FF00191", -- 00000E9C
-		X"02002021", -- 00000EA0
-		X"3C04BFC0", -- 00000EA4
-		X"0FF00159", -- 00000EA8
-		X"24841608", -- 00000EAC
-		X"0FF00127", -- 00000EB0
-		X"00000000", -- 00000EB4
-		X"00408821", -- 00000EB8
-		X"3C04BFC0", -- 00000EBC
-		X"00021203", -- 00000EC0
-		X"305000FF", -- 00000EC4
-		X"0FF00159", -- 00000EC8
-		X"24841598", -- 00000ECC
-		X"2602FFFF", -- 00000ED0
-		X"2C420006", -- 00000ED4
-		X"1040000D", -- 00000ED8
-		X"00101080", -- 00000EDC
-		X"02421021", -- 00000EE0
-		X"8C440000", -- 00000EE4
-		X"0FF00159", -- 00000EE8
-		X"00000000", -- 00000EEC
-		X"3C04BFC0", -- 00000EF0
-		X"0FF00159", -- 00000EF4
-		X"248415A4", -- 00000EF8
-		X"00112600", -- 00000EFC
-		X"0FF00175", -- 00000F00
-		X"00042603", -- 00000F04
-		X"0BF003C8", -- 00000F08
-		X"3C04BFC0", -- 00000F0C
-		X"3C04BFC0", -- 00000F10
-		X"0FF00159", -- 00000F14
-		X"248415AC", -- 00000F18
-		X"3C04BFC0", -- 00000F1C
-		X"8FBF003C", -- 00000F20
-		X"8FB20038", -- 00000F24
-		X"8FB10034", -- 00000F28
-		X"8FB00030", -- 00000F2C
-		X"24841608", -- 00000F30
-		X"0BF00159", -- 00000F34
-		X"27BD0040", -- 00000F38
-		X"27BDFFD8", -- 00000F3C
-		X"AFB30020", -- 00000F40
-		X"AFB10018", -- 00000F44
-		X"AFB00014", -- 00000F48
-		X"AFBF0024", -- 00000F4C
-		X"AFB2001C", -- 00000F50
-		X"00809821", -- 00000F54
-		X"24110073", -- 00000F58
-		X"24100053", -- 00000F5C
-		X"0FF0012A", -- 00000F60
-		X"00000000", -- 00000F64
-		X"14510005", -- 00000F68
-		X"00000000", -- 00000F6C
-		X"00008021", -- 00000F70
-		X"2412000A", -- 00000F74
-		X"0BF003E8", -- 00000F78
-		X"2411000D", -- 00000F7C
-		X"1450FFF7", -- 00000F80
-		X"00000000", -- 00000F84
-		X"0BF003DD", -- 00000F88
-		X"00008021", -- 00000F8C
-		X"0FF0012A", -- 00000F90
-		X"A0620000", -- 00000F94
-		X"10510003", -- 00000F98
-		X"26100001", -- 00000F9C
-		X"1452FFFB", -- 00000FA0
-		X"02701821", -- 00000FA4
-		X"8FBF0024", -- 00000FA8
-		X"02001021", -- 00000FAC
-		X"8FB30020", -- 00000FB0
-		X"8FB2001C", -- 00000FB4
-		X"8FB10018", -- 00000FB8
-		X"8FB00014", -- 00000FBC
-		X"03E00008", -- 00000FC0
-		X"27BD0028", -- 00000FC4
-		X"27BDFD98", -- 00000FC8
-		X"27A4013C", -- 00000FCC
-		X"00002821", -- 00000FD0
-		X"24060100", -- 00000FD4
-		X"AFBF0264", -- 00000FD8
-		X"AFBE0260", -- 00000FDC
-		X"AFB7025C", -- 00000FE0
-		X"AFB60258", -- 00000FE4
-		X"AFB50254", -- 00000FE8
-		X"AFB40250", -- 00000FEC
-		X"AFB3024C", -- 00000FF0
-		X"AFB20248", -- 00000FF4
-		X"AFB10244", -- 00000FF8
-		X"0FF00524", -- 00000FFC
-		X"AFB00240", -- 00001000
-		X"3C02A000", -- 00001004
-		X"AC400000", -- 00001008
-		X"8C420000", -- 0000100C
-		X"00000000", -- 00001010
-		X"1440002D", -- 00001014
-		X"3C04BFC0", -- 00001018
-		X"0FF00159", -- 0000101C
-		X"248415D0", -- 00001020
-		X"3C04BFC0", -- 00001024
-		X"0FF00159", -- 00001028
-		X"248415B4", -- 0000102C
-		X"3C02A400", -- 00001030
-		X"8C44000C", -- 00001034
-		X"8C460004", -- 00001038
-		X"8C430008", -- 0000103C
-		X"00042082", -- 00001040
-		X"00621821", -- 00001044
-		X"00C08021", -- 00001048
-		X"0BF00419", -- 0000104C
-		X"00002821", -- 00001050
-		X"8C620000", -- 00001054
-		X"24630004", -- 00001058
-		X"ACC20000", -- 0000105C
-		X"24C60004", -- 00001060
-		X"00A4102B", -- 00001064
-		X"1440FFFA", -- 00001068
-		X"24A50001", -- 0000106C
-		X"3C04BFC0", -- 00001070
-		X"0FF00159", -- 00001074
-		X"248415CC", -- 00001078
-		X"401A6000", -- 0000107C
-		X"3C1BFFBF", -- 00001080
-		X"377BFFFF", -- 00001084
-		X"035BD024", -- 00001088
-		X"409A6000", -- 0000108C
-		X"02000008", -- 00001090
-		X"42000010", -- 00001094
-		X"8FBF0264", -- 00001098
-		X"00001021", -- 0000109C
-		X"8FBE0260", -- 000010A0
-		X"8FB7025C", -- 000010A4
-		X"8FB60258", -- 000010A8
-		X"8FB50254", -- 000010AC
-		X"8FB40250", -- 000010B0
-		X"8FB3024C", -- 000010B4
-		X"8FB20248", -- 000010B8
-		X"8FB10244", -- 000010BC
-		X"8FB00240", -- 000010C0
-		X"03E00008", -- 000010C4
-		X"27BD0268", -- 000010C8
-		X"27A40020", -- 000010CC
-		X"0FF002A5", -- 000010D0
-		X"3C05A400", -- 000010D4
-		X"3C024000", -- 000010D8
-		X"3C034010", -- 000010DC
-		X"AC400000", -- 000010E0
-		X"24420004", -- 000010E4
-		X"1443FFFD", -- 000010E8
-		X"3C04BFC0", -- 000010EC
-		X"0FF00159", -- 000010F0
-		X"248415D0", -- 000010F4
-		X"3C04BFC0", -- 000010F8
-		X"0FF00159", -- 000010FC
-		X"248415D4", -- 00001100
-		X"3C02BFC0", -- 00001104
-		X"24551604", -- 00001108
-		X"3C02BFC0", -- 0000110C
-		X"245315F8", -- 00001110
-		X"00008821", -- 00001114
-		X"27B4003C", -- 00001118
-		X"27B20020", -- 0000111C
-		X"3C04BFC0", -- 00001120
-		X"0FF00159", -- 00001124
-		X"248415C8", -- 00001128
-		X"241E004A", -- 0000112C
-		X"24170046", -- 00001130
-		X"27B6013C", -- 00001134
-		X"0FF003CF", -- 00001138
-		X"02802021", -- 0000113C
-		X"00403021", -- 00001140
-		X"27A40010", -- 00001144
-		X"02802821", -- 00001148
-		X"0FF002F2", -- 0000114C
-		X"00408021", -- 00001150
-		X"3C03A000", -- 00001154
-		X"AC600000", -- 00001158
-		X"24030002", -- 0000115C
-		X"10430005", -- 00001160
-		X"24030004", -- 00001164
-		X"14430060", -- 00001168
-		X"3C034000", -- 0000116C
-		X"0BF00475", -- 00001170
-		X"3C04BFC0", -- 00001174
-		X"8FA20014", -- 00001178
-		X"8FA50010", -- 0000117C
-		X"00000000", -- 00001180
-		X"00A21821", -- 00001184
-		X"0223102B", -- 00001188
-		X"10400002", -- 0000118C
-		X"00000000", -- 00001190
-		X"00608821", -- 00001194
-		X"0BF0046E", -- 00001198
-		X"00001821", -- 0000119C
-		X"8FA2001C", -- 000011A0
-		X"00000000", -- 000011A4
-		X"00431021", -- 000011A8
-		X"90420000", -- 000011AC
-		X"24630001", -- 000011B0
-		X"A0820000", -- 000011B4
-		X"8FA20014", -- 000011B8
-		X"00000000", -- 000011BC
-		X"0062102B", -- 000011C0
-		X"1440FFF6", -- 000011C4
-		X"00652021", -- 000011C8
-		X"0BF004B9", -- 000011CC
-		X"00000000", -- 000011D0
-		X"0FF00159", -- 000011D4
-		X"248415CC", -- 000011D8
-		X"8FA50010", -- 000011DC
-		X"24020049", -- 000011E0
-		X"A3A2013E", -- 000011E4
-		X"3C04BFC0", -- 000011E8
-		X"24020031", -- 000011EC
-		X"02251823", -- 000011F0
-		X"248415E8", -- 000011F4
-		X"A3A2013F", -- 000011F8
-		X"24020100", -- 000011FC
-		X"AFA50140", -- 00001200
-		X"AFA30148", -- 00001204
-		X"AFA20144", -- 00001208
-		X"A3BE013C", -- 0000120C
-		X"A3B7013D", -- 00001210
-		X"0FF00159", -- 00001214
-		X"AFA0014C", -- 00001218
-		X"8FA60148", -- 0000121C
-		X"02402021", -- 00001220
-		X"24C60100", -- 00001224
-		X"0FF002AF", -- 00001228
-		X"00002821", -- 0000122C
-		X"04400020", -- 00001230
-		X"00000000", -- 00001234
-		X"0FF00159", -- 00001238
-		X"02A02021", -- 0000123C
-		X"3C04BFC0", -- 00001240
-		X"0FF00159", -- 00001244
-		X"2484160C", -- 00001248
-		X"02402021", -- 0000124C
-		X"00002821", -- 00001250
-		X"02C03021", -- 00001254
-		X"0FF002CB", -- 00001258
-		X"24070100", -- 0000125C
-		X"04400014", -- 00001260
-		X"00000000", -- 00001264
-		X"8FA50144", -- 00001268
-		X"8FA70148", -- 0000126C
-		X"02402021", -- 00001270
-		X"0FF002CB", -- 00001274
-		X"3C064000", -- 00001278
-		X"0440000D", -- 0000127C
-		X"00000000", -- 00001280
-		X"0FF00159", -- 00001284
-		X"02A02021", -- 00001288
-		X"3C04BFC0", -- 0000128C
-		X"0FF00159", -- 00001290
-		X"2484161C", -- 00001294
-		X"8FA50144", -- 00001298
-		X"8FA70148", -- 0000129C
-		X"02402021", -- 000012A0
-		X"0FF002CE", -- 000012A4
-		X"3C064000", -- 000012A8
-		X"04410005", -- 000012AC
-		X"00000000", -- 000012B0
-		X"0FF00159", -- 000012B4
-		X"02602021", -- 000012B8
-		X"0BF004BB", -- 000012BC
-		X"3C034000", -- 000012C0
-		X"3C04BFC0", -- 000012C4
-		X"0FF00159", -- 000012C8
-		X"2484162C", -- 000012CC
-		X"3C02BFC0", -- 000012D0
-		X"00400008", -- 000012D4
-		X"00000000", -- 000012D8
-		X"0BF0044E", -- 000012DC
-		X"00000000", -- 000012E0
-		X"0601FF94", -- 000012E4
-		X"3C034000", -- 000012E8
-		X"3C02A000", -- 000012EC
-		X"AC430000", -- 000012F0
-		X"0BF00449", -- 000012F4
-		X"3C04BFC0", -- 000012F8
-		X"00A41025", -- 000012FC
-		X"30420003", -- 00001300
-		X"00806021", -- 00001304
-		X"1440002F", -- 00001308
-		X"00A05821", -- 0000130C
-		X"00065102", -- 00001310
-		X"00804021", -- 00001314
-		X"30C6000F", -- 00001318
-		X"11400011", -- 0000131C
-		X"00A03821", -- 00001320
-		X"01404821", -- 00001324
-		X"8CE30004", -- 00001328
-		X"8CE40008", -- 0000132C
-		X"8CE5000C", -- 00001330
-		X"8CE20000", -- 00001334
-		X"2529FFFF", -- 00001338
-		X"AD020000", -- 0000133C
-		X"AD030004", -- 00001340
-		X"AD040008", -- 00001344
-		X"AD05000C", -- 00001348
-		X"24E70010", -- 0000134C
-		X"1520FFF5", -- 00001350
-		X"25080010", -- 00001354
-		X"000A1100", -- 00001358
-		X"01623821", -- 0000135C
-		X"01824021", -- 00001360
-		X"00064882", -- 00001364
-		X"1120000D", -- 00001368
-		X"30C60003", -- 0000136C
-		X"01002821", -- 00001370
-		X"00E02021", -- 00001374
-		X"01201821", -- 00001378
-		X"8C820000", -- 0000137C
-		X"2463FFFF", -- 00001380
-		X"ACA20000", -- 00001384
-		X"24840004", -- 00001388
-		X"1460FFFB", -- 0000138C
-		X"24A50004", -- 00001390
-		X"00091080", -- 00001394
-		X"01024021", -- 00001398
-		X"00E23821", -- 0000139C
-		X"10C00007", -- 000013A0
-		X"00002821", -- 000013A4
-		X"00E51021", -- 000013A8
-		X"90440000", -- 000013AC
-		X"01051821", -- 000013B0
-		X"24A50001", -- 000013B4
-		X"14A6FFFB", -- 000013B8
-		X"A0640000", -- 000013BC
-		X"03E00008", -- 000013C0
-		X"01801021", -- 000013C4
-		X"00A04021", -- 000013C8
-		X"00803821", -- 000013CC
-		X"04C00027", -- 000013D0
-		X"00C01821", -- 000013D4
-		X"3C028000", -- 000013D8
-		X"34420003", -- 000013DC
-		X"00C23024", -- 000013E0
-		X"04C0001B", -- 000013E4
-		X"00034883", -- 000013E8
-		X"1120000F", -- 000013EC
-		X"00000000", -- 000013F0
-		X"01602821", -- 000013F4
-		X"01802021", -- 000013F8
-		X"01201821", -- 000013FC
-		X"2463FFFF", -- 00001400
-		X"88A20003", -- 00001404
-		X"98A20000", -- 00001408
-		X"24A50004", -- 0000140C
-		X"A8820003", -- 00001410
-		X"B8820000", -- 00001414
-		X"1460FFF9", -- 00001418
-		X"24840004", -- 0000141C
-		X"00091080", -- 00001420
-		X"01624021", -- 00001424
-		X"01823821", -- 00001428
-		X"18C0FFE4", -- 0000142C
-		X"00002821", -- 00001430
-		X"01051021", -- 00001434
-		X"90440000", -- 00001438
-		X"00E51821", -- 0000143C
-		X"24A50001", -- 00001440
-		X"14A6FFFB", -- 00001444
-		X"A0640000", -- 00001448
-		X"03E00008", -- 0000144C
-		X"01801021", -- 00001450
-		X"24C6FFFF", -- 00001454
-		X"2402FFFC", -- 00001458
-		X"00C23025", -- 0000145C
-		X"1520FFE4", -- 00001460
-		X"24C60001", -- 00001464
-		X"0BF0050B", -- 00001468
-		X"00000000", -- 0000146C
-		X"3C028000", -- 00001470
-		X"34420003", -- 00001474
-		X"24C30003", -- 00001478
-		X"00C23024", -- 0000147C
-		X"04C1FFDA", -- 00001480
-		X"00034883", -- 00001484
-		X"0BF00516", -- 00001488
-		X"24C6FFFF", -- 0000148C
-		X"2CC20010", -- 00001490
-		X"00804821", -- 00001494
-		X"1440002D", -- 00001498
-		X"00804021", -- 0000149C
-		X"30870003", -- 000014A0
-		X"10E0000E", -- 000014A4
-		X"24820004", -- 000014A8
-		X"00052600", -- 000014AC
-		X"00471023", -- 000014B0
-		X"00042603", -- 000014B4
-		X"01201821", -- 000014B8
-		X"A0640000", -- 000014BC
-		X"24630001", -- 000014C0
-		X"1462FFFD", -- 000014C4
-		X"00000000", -- 000014C8
-		X"00071027", -- 000014CC
-		X"24C3FFFB", -- 000014D0
-		X"24440005", -- 000014D4
-		X"00623023", -- 000014D8
-		X"01244021", -- 000014DC
-		X"30A500FF", -- 000014E0
-		X"01003821", -- 000014E4
-		X"10A00005", -- 000014E8
-		X"00A01821", -- 000014EC
-		X"00051200", -- 000014F0
-		X"00451025", -- 000014F4
-		X"00021C00", -- 000014F8
-		X"00621825", -- 000014FC
-		X"000610C2", -- 00001500
-		X"1040001C", -- 00001504
-		X"30C60007", -- 00001508
-		X"01002021", -- 0000150C
-		X"00403821", -- 00001510
-		X"24E7FFFF", -- 00001514
-		X"AC830000", -- 00001518
-		X"AC830004", -- 0000151C
-		X"14E0FFFC", -- 00001520
-		X"24840008", -- 00001524
-		X"000210C0", -- 00001528
-		X"01023821", -- 0000152C
-		X"00E02021", -- 00001530
-		X"2CC20004", -- 00001534
-		X"14400005", -- 00001538
-		X"00804021", -- 0000153C
-		X"ACE30000", -- 00001540
-		X"24E40004", -- 00001544
-		X"24C6FFFC", -- 00001548
-		X"00804021", -- 0000154C
-		X"10C00007", -- 00001550
-		X"00000000", -- 00001554
-		X"00051600", -- 00001558
-		X"00021603", -- 0000155C
-		X"24C6FFFF", -- 00001560
-		X"A1020000", -- 00001564
-		X"14C0FFFD", -- 00001568
-		X"25080001", -- 0000156C
-		X"03E00008", -- 00001570
-		X"01201021", -- 00001574
-		X"0BF0054D", -- 00001578
-		X"01002021", -- 0000157C
-		X"00510051", -- 00001580
-		X"00520052", -- 00001584
-		X"00590059", -- 00001588
-		X"74617453", -- 0000158C
-		X"20207375", -- 00001590
-		X"0000203A", -- 00001594
-		X"20555043", -- 00001598
-		X"65707974", -- 0000159C
-		X"0000203A", -- 000015A0
-		X"76655220", -- 000015A4
-		X"0000002E", -- 000015A8
-		X"6E6B6E55", -- 000015AC
-		X"006E776F", -- 000015B0
-		X"746F6F42", -- 000015B4
-		X"20676E69", -- 000015B8
-		X"6D6F7266", -- 000015BC
-		X"616C6620", -- 000015C0
-		X"2E2E6873", -- 000015C4
-		X"0000002E", -- 000015C8
-		X"656E6F64", -- 000015CC
-		X"00000A0A", -- 000015D0
-		X"746F6F42", -- 000015D4
-		X"20676E69", -- 000015D8
-		X"6D6F7266", -- 000015DC
-		X"52415520", -- 000015E0
-		X"002E2E54", -- 000015E4
-		X"73616C46", -- 000015E8
-		X"72652068", -- 000015EC
-		X"2E657361", -- 000015F0
-		X"00002E2E", -- 000015F4
-		X"6C696166", -- 000015F8
-		X"0A216465", -- 000015FC
-		X"00000000", -- 00001600
-		X"656E6F64", -- 00001604
-		X"0000000A", -- 00001608
-		X"73616C46", -- 0000160C
-		X"72772068", -- 00001610
-		X"2E657469", -- 00001614
-		X"00002E2E", -- 00001618
-		X"73616C46", -- 0000161C
-		X"65762068", -- 00001620
-		X"79666972", -- 00001624
-		X"002E2E2E", -- 00001628
-		X"73736170", -- 0000162C
-		X"000A6465", -- 00001630
-		X"61766E69", -- 00001634
-		X"0064696C", -- 00001638
-		X"30303252", -- 0000163C
-		X"00000030", -- 00001640
-		X"30303352", -- 00001644
-		X"00000030", -- 00001648
-		X"30303652", -- 0000164C
-		X"00000030", -- 00001650
-		X"30303452", -- 00001654
-		X"00000030", -- 00001658
-		X"65736572", -- 0000165C
-		X"64657672", -- 00001660
-		X"00000000", -- 00001664
-		X"30303652", -- 00001668
-		X"00004130", -- 0000166C
-		X"BFC01634", -- 00001670
-		X"BFC0163C", -- 00001674
-		X"BFC01644", -- 00001678
-		X"BFC0164C", -- 0000167C
-		X"BFC01654", -- 00001680
-		X"BFC0165C", -- 00001684
-		X"BFC01668", -- 00001688
-		X"00000000", -- 0000168C
-		X"00000000", -- 00001690
-		X"00000000", -- 00001694
-		X"00000000", -- 00001698
-		X"00000000", -- 0000169C
-		X"00000000", -- 000016A0
-		X"00000000", -- 000016A4
-		X"00000000", -- 000016A8
-		X"00000000", -- 000016AC
-		X"00000000", -- 000016B0
-		X"00000000", -- 000016B4
-		X"00000000", -- 000016B8
-		X"00000000", -- 000016BC
-		X"00000000", -- 000016C0
-		X"00000000", -- 000016C4
-		X"00000000", -- 000016C8
-		X"00000000", -- 000016CC
-		X"00000000", -- 000016D0
-		X"00000000", -- 000016D4
-		X"00000000", -- 000016D8
-		X"00000000", -- 000016DC
-		X"00000000", -- 000016E0
-		X"00000000", -- 000016E4
-		X"00000000", -- 000016E8
-		X"00000000", -- 000016EC
-		X"00000000", -- 000016F0
-		X"00000000", -- 000016F4
-		X"00000000", -- 000016F8
-		X"00000000", -- 000016FC
-		X"00000000", -- 00001700
-		X"00000000", -- 00001704
-		X"00000000", -- 00001708
-		X"00000000", -- 0000170C
-		X"00000000", -- 00001710
-		X"00000000", -- 00001714
-		X"00000000", -- 00001718
-		X"00000000", -- 0000171C
-		X"00000000", -- 00001720
-		X"00000000", -- 00001724
-		X"00000000", -- 00001728
-		X"00000000", -- 0000172C
-		X"00000000", -- 00001730
-		X"00000000", -- 00001734
-		X"00000000", -- 00001738
-		X"00000000", -- 0000173C
-		X"00000000", -- 00001740
-		X"00000000", -- 00001744
-		X"00000000", -- 00001748
-		X"00000000", -- 0000174C
-		X"00000000", -- 00001750
-		X"00000000", -- 00001754
-		X"00000000", -- 00001758
-		X"00000000", -- 0000175C
-		X"00000000", -- 00001760
-		X"00000000", -- 00001764
-		X"00000000", -- 00001768
-		X"00000000", -- 0000176C
-		X"00000000", -- 00001770
-		X"00000000", -- 00001774
-		X"00000000", -- 00001778
-		X"00000000", -- 0000177C
-		X"00000000", -- 00001780
-		X"00000000", -- 00001784
-		X"00000000", -- 00001788
-		X"00000000", -- 0000178C
-		X"00000000", -- 00001790
-		X"00000000", -- 00001794
-		X"00000000", -- 00001798
-		X"00000000", -- 0000179C
-		X"00000000", -- 000017A0
-		X"00000000", -- 000017A4
-		X"00000000", -- 000017A8
-		X"00000000", -- 000017AC
-		X"00000000", -- 000017B0
-		X"00000000", -- 000017B4
-		X"00000000", -- 000017B8
-		X"00000000", -- 000017BC
-		X"00000000", -- 000017C0
-		X"00000000", -- 000017C4
-		X"00000000", -- 000017C8
-		X"00000000", -- 000017CC
-		X"00000000", -- 000017D0
-		X"00000000", -- 000017D4
-		X"00000000", -- 000017D8
-		X"00000000", -- 000017DC
-		X"00000000", -- 000017E0
-		X"00000000", -- 000017E4
-		X"00000000", -- 000017E8
-		X"00000000", -- 000017EC
-		X"00000000", -- 000017F0
-		X"00000000", -- 000017F4
-		X"00000000", -- 000017F8
-		X"00000000", -- 000017FC
-		X"00000000", -- 00001800
-		X"00000000", -- 00001804
-		X"00000000", -- 00001808
-		X"00000000", -- 0000180C
-		X"00000000", -- 00001810
-		X"00000000", -- 00001814
-		X"00000000", -- 00001818
-		X"00000000", -- 0000181C
-		X"00000000", -- 00001820
-		X"00000000", -- 00001824
-		X"00000000", -- 00001828
-		X"00000000", -- 0000182C
-		X"00000000", -- 00001830
-		X"00000000", -- 00001834
-		X"00000000", -- 00001838
-		X"00000000", -- 0000183C
-		X"00000000", -- 00001840
-		X"00000000", -- 00001844
-		X"00000000", -- 00001848
-		X"00000000", -- 0000184C
-		X"00000000", -- 00001850
-		X"00000000", -- 00001854
-		X"00000000", -- 00001858
-		X"00000000", -- 0000185C
-		X"00000000", -- 00001860
-		X"00000000", -- 00001864
-		X"00000000", -- 00001868
-		X"00000000", -- 0000186C
-		X"00000000", -- 00001870
-		X"00000000", -- 00001874
-		X"00000000", -- 00001878
-		X"00000000", -- 0000187C
-		X"00000000", -- 00001880
-		X"00000000", -- 00001884
-		X"00000000", -- 00001888
-		X"00000000", -- 0000188C
-		X"00000000", -- 00001890
-		X"00000000", -- 00001894
-		X"00000000", -- 00001898
-		X"00000000", -- 0000189C
-		X"00000000", -- 000018A0
-		X"00000000", -- 000018A4
-		X"00000000", -- 000018A8
-		X"00000000", -- 000018AC
-		X"00000000", -- 000018B0
-		X"00000000", -- 000018B4
-		X"00000000", -- 000018B8
-		X"00000000", -- 000018BC
-		X"00000000", -- 000018C0
-		X"00000000", -- 000018C4
-		X"00000000", -- 000018C8
-		X"00000000", -- 000018CC
-		X"00000000", -- 000018D0
-		X"00000000", -- 000018D4
-		X"00000000", -- 000018D8
-		X"00000000", -- 000018DC
-		X"00000000", -- 000018E0
-		X"00000000", -- 000018E4
-		X"00000000", -- 000018E8
-		X"00000000", -- 000018EC
-		X"00000000", -- 000018F0
-		X"00000000", -- 000018F4
-		X"00000000", -- 000018F8
-		X"00000000", -- 000018FC
-		X"00000000", -- 00001900
-		X"00000000", -- 00001904
-		X"00000000", -- 00001908
-		X"00000000", -- 0000190C
-		X"00000000", -- 00001910
-		X"00000000", -- 00001914
-		X"00000000", -- 00001918
-		X"00000000", -- 0000191C
-		X"00000000", -- 00001920
-		X"00000000", -- 00001924
-		X"00000000", -- 00001928
-		X"00000000", -- 0000192C
-		X"00000000", -- 00001930
-		X"00000000", -- 00001934
-		X"00000000", -- 00001938
-		X"00000000", -- 0000193C
-		X"00000000", -- 00001940
-		X"00000000", -- 00001944
-		X"00000000", -- 00001948
-		X"00000000", -- 0000194C
-		X"00000000", -- 00001950
-		X"00000000", -- 00001954
-		X"00000000", -- 00001958
-		X"00000000", -- 0000195C
-		X"00000000", -- 00001960
-		X"00000000", -- 00001964
-		X"00000000", -- 00001968
-		X"00000000", -- 0000196C
-		X"00000000", -- 00001970
-		X"00000000", -- 00001974
-		X"00000000", -- 00001978
-		X"00000000", -- 0000197C
-		X"00000000", -- 00001980
-		X"00000000", -- 00001984
-		X"00000000", -- 00001988
-		X"00000000", -- 0000198C
-		X"00000000", -- 00001990
-		X"00000000", -- 00001994
-		X"00000000", -- 00001998
-		X"00000000", -- 0000199C
-		X"00000000", -- 000019A0
-		X"00000000", -- 000019A4
-		X"00000000", -- 000019A8
-		X"00000000", -- 000019AC
-		X"00000000", -- 000019B0
-		X"00000000", -- 000019B4
-		X"00000000", -- 000019B8
-		X"00000000", -- 000019BC
-		X"00000000", -- 000019C0
-		X"00000000", -- 000019C4
-		X"00000000", -- 000019C8
-		X"00000000", -- 000019CC
-		X"00000000", -- 000019D0
-		X"00000000", -- 000019D4
-		X"00000000", -- 000019D8
-		X"00000000", -- 000019DC
-		X"00000000", -- 000019E0
-		X"00000000", -- 000019E4
-		X"00000000", -- 000019E8
-		X"00000000", -- 000019EC
-		X"00000000", -- 000019F0
-		X"00000000", -- 000019F4
-		X"00000000", -- 000019F8
-		X"00000000", -- 000019FC
-		X"00000000", -- 00001A00
-		X"00000000", -- 00001A04
-		X"00000000", -- 00001A08
-		X"00000000", -- 00001A0C
-		X"00000000", -- 00001A10
-		X"00000000", -- 00001A14
-		X"00000000", -- 00001A18
-		X"00000000", -- 00001A1C
-		X"00000000", -- 00001A20
-		X"00000000", -- 00001A24
-		X"00000000", -- 00001A28
-		X"00000000", -- 00001A2C
-		X"00000000", -- 00001A30
-		X"00000000", -- 00001A34
-		X"00000000", -- 00001A38
-		X"00000000", -- 00001A3C
-		X"00000000", -- 00001A40
-		X"00000000", -- 00001A44
-		X"00000000", -- 00001A48
-		X"00000000", -- 00001A4C
-		X"00000000", -- 00001A50
-		X"00000000", -- 00001A54
-		X"00000000", -- 00001A58
-		X"00000000", -- 00001A5C
-		X"00000000", -- 00001A60
-		X"00000000", -- 00001A64
-		X"00000000", -- 00001A68
-		X"00000000", -- 00001A6C
-		X"00000000", -- 00001A70
-		X"00000000", -- 00001A74
-		X"00000000", -- 00001A78
-		X"00000000", -- 00001A7C
-		X"00000000", -- 00001A80
-		X"00000000", -- 00001A84
-		X"00000000", -- 00001A88
-		X"00000000", -- 00001A8C
-		X"00000000", -- 00001A90
-		X"00000000", -- 00001A94
-		X"00000000", -- 00001A98
-		X"00000000", -- 00001A9C
-		X"00000000", -- 00001AA0
-		X"00000000", -- 00001AA4
-		X"00000000", -- 00001AA8
-		X"00000000", -- 00001AAC
-		X"00000000", -- 00001AB0
-		X"00000000", -- 00001AB4
-		X"00000000", -- 00001AB8
-		X"00000000", -- 00001ABC
-		X"00000000", -- 00001AC0
-		X"00000000", -- 00001AC4
-		X"00000000", -- 00001AC8
-		X"00000000", -- 00001ACC
-		X"00000000", -- 00001AD0
-		X"00000000", -- 00001AD4
-		X"00000000", -- 00001AD8
-		X"00000000", -- 00001ADC
-		X"00000000", -- 00001AE0
-		X"00000000", -- 00001AE4
-		X"00000000", -- 00001AE8
-		X"00000000", -- 00001AEC
-		X"00000000", -- 00001AF0
-		X"00000000", -- 00001AF4
-		X"00000000", -- 00001AF8
-		X"00000000", -- 00001AFC
-		X"00000000", -- 00001B00
-		X"00000000", -- 00001B04
-		X"00000000", -- 00001B08
-		X"00000000", -- 00001B0C
-		X"00000000", -- 00001B10
-		X"00000000", -- 00001B14
-		X"00000000", -- 00001B18
-		X"00000000", -- 00001B1C
-		X"00000000", -- 00001B20
-		X"00000000", -- 00001B24
-		X"00000000", -- 00001B28
-		X"00000000", -- 00001B2C
-		X"00000000", -- 00001B30
-		X"00000000", -- 00001B34
-		X"00000000", -- 00001B38
-		X"00000000", -- 00001B3C
-		X"00000000", -- 00001B40
-		X"00000000", -- 00001B44
-		X"00000000", -- 00001B48
-		X"00000000", -- 00001B4C
-		X"00000000", -- 00001B50
-		X"00000000", -- 00001B54
-		X"00000000", -- 00001B58
-		X"00000000", -- 00001B5C
-		X"00000000", -- 00001B60
-		X"00000000", -- 00001B64
-		X"00000000", -- 00001B68
-		X"00000000", -- 00001B6C
-		X"00000000", -- 00001B70
-		X"00000000", -- 00001B74
-		X"00000000", -- 00001B78
-		X"00000000", -- 00001B7C
-		X"00000000", -- 00001B80
-		X"00000000", -- 00001B84
-		X"00000000", -- 00001B88
-		X"00000000", -- 00001B8C
-		X"00000000", -- 00001B90
-		X"00000000", -- 00001B94
-		X"00000000", -- 00001B98
-		X"00000000", -- 00001B9C
-		X"00000000", -- 00001BA0
-		X"00000000", -- 00001BA4
-		X"00000000", -- 00001BA8
-		X"00000000", -- 00001BAC
-		X"00000000", -- 00001BB0
-		X"00000000", -- 00001BB4
-		X"00000000", -- 00001BB8
-		X"00000000", -- 00001BBC
-		X"00000000", -- 00001BC0
-		X"00000000", -- 00001BC4
-		X"00000000", -- 00001BC8
-		X"00000000", -- 00001BCC
-		X"00000000", -- 00001BD0
-		X"00000000", -- 00001BD4
-		X"00000000", -- 00001BD8
-		X"00000000", -- 00001BDC
-		X"00000000", -- 00001BE0
-		X"00000000", -- 00001BE4
-		X"00000000", -- 00001BE8
-		X"00000000", -- 00001BEC
-		X"00000000", -- 00001BF0
-		X"00000000", -- 00001BF4
-		X"00000000", -- 00001BF8
-		X"00000000", -- 00001BFC
-		X"00000000", -- 00001C00
-		X"00000000", -- 00001C04
-		X"00000000", -- 00001C08
-		X"00000000", -- 00001C0C
-		X"00000000", -- 00001C10
-		X"00000000", -- 00001C14
-		X"00000000", -- 00001C18
-		X"00000000", -- 00001C1C
-		X"00000000", -- 00001C20
-		X"00000000", -- 00001C24
-		X"00000000", -- 00001C28
-		X"00000000", -- 00001C2C
-		X"00000000", -- 00001C30
-		X"00000000", -- 00001C34
-		X"00000000", -- 00001C38
-		X"00000000", -- 00001C3C
-		X"00000000", -- 00001C40
-		X"00000000", -- 00001C44
-		X"00000000", -- 00001C48
-		X"00000000", -- 00001C4C
-		X"00000000", -- 00001C50
-		X"00000000", -- 00001C54
-		X"00000000", -- 00001C58
-		X"00000000", -- 00001C5C
-		X"00000000", -- 00001C60
-		X"00000000", -- 00001C64
-		X"00000000", -- 00001C68
-		X"00000000", -- 00001C6C
-		X"00000000", -- 00001C70
-		X"00000000", -- 00001C74
-		X"00000000", -- 00001C78
-		X"00000000", -- 00001C7C
-		X"00000000", -- 00001C80
-		X"00000000", -- 00001C84
-		X"00000000", -- 00001C88
-		X"00000000", -- 00001C8C
-		X"00000000", -- 00001C90
-		X"00000000", -- 00001C94
-		X"00000000", -- 00001C98
-		X"00000000", -- 00001C9C
-		X"00000000", -- 00001CA0
-		X"00000000", -- 00001CA4
-		X"00000000", -- 00001CA8
-		X"00000000", -- 00001CAC
-		X"00000000", -- 00001CB0
-		X"00000000", -- 00001CB4
-		X"00000000", -- 00001CB8
-		X"00000000", -- 00001CBC
-		X"00000000", -- 00001CC0
-		X"00000000", -- 00001CC4
-		X"00000000", -- 00001CC8
-		X"00000000", -- 00001CCC
-		X"00000000", -- 00001CD0
-		X"00000000", -- 00001CD4
-		X"00000000", -- 00001CD8
-		X"00000000", -- 00001CDC
-		X"00000000", -- 00001CE0
-		X"00000000", -- 00001CE4
-		X"00000000", -- 00001CE8
-		X"00000000", -- 00001CEC
-		X"00000000", -- 00001CF0
-		X"00000000", -- 00001CF4
-		X"00000000", -- 00001CF8
-		X"00000000", -- 00001CFC
-		X"00000000", -- 00001D00
-		X"00000000", -- 00001D04
-		X"00000000", -- 00001D08
-		X"00000000", -- 00001D0C
-		X"00000000", -- 00001D10
-		X"00000000", -- 00001D14
-		X"00000000", -- 00001D18
-		X"00000000", -- 00001D1C
-		X"00000000", -- 00001D20
-		X"00000000", -- 00001D24
-		X"00000000", -- 00001D28
-		X"00000000", -- 00001D2C
-		X"00000000", -- 00001D30
-		X"00000000", -- 00001D34
-		X"00000000", -- 00001D38
-		X"00000000", -- 00001D3C
-		X"00000000", -- 00001D40
-		X"00000000", -- 00001D44
-		X"00000000", -- 00001D48
-		X"00000000", -- 00001D4C
-		X"00000000", -- 00001D50
-		X"00000000", -- 00001D54
-		X"00000000", -- 00001D58
-		X"00000000", -- 00001D5C
-		X"00000000", -- 00001D60
-		X"00000000", -- 00001D64
-		X"00000000", -- 00001D68
-		X"00000000", -- 00001D6C
-		X"00000000", -- 00001D70
-		X"00000000", -- 00001D74
-		X"00000000", -- 00001D78
-		X"00000000", -- 00001D7C
-		X"00000000", -- 00001D80
-		X"00000000", -- 00001D84
-		X"00000000", -- 00001D88
-		X"00000000", -- 00001D8C
-		X"00000000", -- 00001D90
-		X"00000000", -- 00001D94
-		X"00000000", -- 00001D98
-		X"00000000", -- 00001D9C
-		X"00000000", -- 00001DA0
-		X"00000000", -- 00001DA4
-		X"00000000", -- 00001DA8
-		X"00000000", -- 00001DAC
-		X"00000000", -- 00001DB0
-		X"00000000", -- 00001DB4
-		X"00000000", -- 00001DB8
-		X"00000000", -- 00001DBC
-		X"00000000", -- 00001DC0
-		X"00000000", -- 00001DC4
-		X"00000000", -- 00001DC8
-		X"00000000", -- 00001DCC
-		X"00000000", -- 00001DD0
-		X"00000000", -- 00001DD4
-		X"00000000", -- 00001DD8
-		X"00000000", -- 00001DDC
-		X"00000000", -- 00001DE0
-		X"00000000", -- 00001DE4
-		X"00000000", -- 00001DE8
-		X"00000000", -- 00001DEC
-		X"00000000", -- 00001DF0
-		X"00000000", -- 00001DF4
-		X"00000000", -- 00001DF8
-		X"00000000", -- 00001DFC
-		X"00000000", -- 00001E00
-		X"00000000", -- 00001E04
-		X"00000000", -- 00001E08
-		X"00000000", -- 00001E0C
-		X"00000000", -- 00001E10
-		X"00000000", -- 00001E14
-		X"00000000", -- 00001E18
-		X"00000000", -- 00001E1C
-		X"00000000", -- 00001E20
-		X"00000000", -- 00001E24
-		X"00000000", -- 00001E28
-		X"00000000", -- 00001E2C
-		X"00000000", -- 00001E30
-		X"00000000", -- 00001E34
-		X"00000000", -- 00001E38
-		X"00000000", -- 00001E3C
-		X"00000000", -- 00001E40
-		X"00000000", -- 00001E44
-		X"00000000", -- 00001E48
-		X"00000000", -- 00001E4C
-		X"00000000", -- 00001E50
-		X"00000000", -- 00001E54
-		X"00000000", -- 00001E58
-		X"00000000", -- 00001E5C
-		X"00000000", -- 00001E60
-		X"00000000", -- 00001E64
-		X"00000000", -- 00001E68
-		X"00000000", -- 00001E6C
-		X"00000000", -- 00001E70
-		X"00000000", -- 00001E74
-		X"00000000", -- 00001E78
-		X"00000000", -- 00001E7C
-		X"00000000", -- 00001E80
-		X"00000000", -- 00001E84
-		X"00000000", -- 00001E88
-		X"00000000", -- 00001E8C
-		X"00000000", -- 00001E90
-		X"00000000", -- 00001E94
-		X"00000000", -- 00001E98
-		X"00000000", -- 00001E9C
-		X"00000000", -- 00001EA0
-		X"00000000", -- 00001EA4
-		X"00000000", -- 00001EA8
-		X"00000000", -- 00001EAC
-		X"00000000", -- 00001EB0
-		X"00000000", -- 00001EB4
-		X"00000000", -- 00001EB8
-		X"00000000", -- 00001EBC
-		X"00000000", -- 00001EC0
-		X"00000000", -- 00001EC4
-		X"00000000", -- 00001EC8
-		X"00000000", -- 00001ECC
-		X"00000000", -- 00001ED0
-		X"00000000", -- 00001ED4
-		X"00000000", -- 00001ED8
-		X"00000000", -- 00001EDC
-		X"00000000", -- 00001EE0
-		X"00000000", -- 00001EE4
-		X"00000000", -- 00001EE8
-		X"00000000", -- 00001EEC
-		X"00000000", -- 00001EF0
-		X"00000000", -- 00001EF4
-		X"00000000", -- 00001EF8
-		X"00000000", -- 00001EFC
-		X"00000000", -- 00001F00
-		X"00000000", -- 00001F04
-		X"00000000", -- 00001F08
-		X"00000000", -- 00001F0C
-		X"00000000", -- 00001F10
-		X"00000000", -- 00001F14
-		X"00000000", -- 00001F18
-		X"00000000", -- 00001F1C
-		X"00000000", -- 00001F20
-		X"00000000", -- 00001F24
-		X"00000000", -- 00001F28
-		X"00000000", -- 00001F2C
-		X"00000000", -- 00001F30
-		X"00000000", -- 00001F34
-		X"00000000", -- 00001F38
-		X"00000000", -- 00001F3C
-		X"00000000", -- 00001F40
-		X"00000000", -- 00001F44
-		X"00000000", -- 00001F48
-		X"00000000", -- 00001F4C
-		X"00000000", -- 00001F50
-		X"00000000", -- 00001F54
-		X"00000000", -- 00001F58
-		X"00000000", -- 00001F5C
-		X"00000000", -- 00001F60
-		X"00000000", -- 00001F64
-		X"00000000", -- 00001F68
-		X"00000000", -- 00001F6C
-		X"00000000", -- 00001F70
-		X"00000000", -- 00001F74
-		X"00000000", -- 00001F78
-		X"00000000", -- 00001F7C
-		X"00000000", -- 00001F80
-		X"00000000", -- 00001F84
-		X"00000000", -- 00001F88
-		X"00000000", -- 00001F8C
-		X"00000000", -- 00001F90
-		X"00000000", -- 00001F94
-		X"00000000", -- 00001F98
-		X"00000000", -- 00001F9C
-		X"00000000", -- 00001FA0
-		X"00000000", -- 00001FA4
-		X"00000000", -- 00001FA8
-		X"00000000", -- 00001FAC
-		X"00000000", -- 00001FB0
-		X"00000000", -- 00001FB4
-		X"00000000", -- 00001FB8
-		X"00000000", -- 00001FBC
-		X"00000000", -- 00001FC0
-		X"00000000", -- 00001FC4
-		X"00000000", -- 00001FC8
-		X"00000000", -- 00001FCC
-		X"00000000", -- 00001FD0
-		X"00000000", -- 00001FD4
-		X"00000000", -- 00001FD8
-		X"00000000", -- 00001FDC
-		X"00000000", -- 00001FE0
-		X"00000000", -- 00001FE4
-		X"00000000", -- 00001FE8
-		X"00000000", -- 00001FEC
-		X"00000000", -- 00001FF0
-		X"00000000", -- 00001FF4
-		X"00000000", -- 00001FF8
-		X"00000000"  -- 00001FFC
-	);
-
-begin
-
-PROM_READ:
-	process(clk)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= word_array(to_integer(addr(12 downto 2)));
-		end if;
-	end process;
-
-end data;
diff --git a/projects/mips_sys/src/bootloader.ROM_ld.vhd b/projects/mips_sys/src/bootloader.ROM_ld.vhd
deleted file mode 100644
index 4469193..0000000
--- a/projects/mips_sys/src/bootloader.ROM_ld.vhd
+++ /dev/null
@@ -1,2174 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-ENTITY rom IS
-	Port
-	(
-		clk		: in  STD_LOGIC;
-		ce		: in  STD_LOGIC;
-		addr		: in  unsigned(31 downto 0);
-		dout		: out unsigned(31 downto 0)
-	);
-END rom;
-
-ARCHITECTURE data OF rom IS
-
-	subtype word_t is unsigned(31 downto 0);
-	type word_array_t is array (0 to 2047) of word_t;
-	signal jtag_ld_clk		: STD_LOGIC;
-	signal jtag_ld_we		: STD_LOGIC;
-	signal jtag_ld_addr		: unsigned (15 downto 0);
-	signal jtag_ld_dout		: unsigned (31 downto 0);
-	signal jtag_ld_din		: unsigned (31 downto 0);
-	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
-	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
-	signal user_regi, user_rego : unsigned (47 downto 0);
-
-	signal word_array : word_array_t :=
-	(
-
-		X"3C1A1040", -- 00000000
-		X"375A000C", -- 00000004
-		X"409A6000", -- 00000008
-		X"241A0000", -- 0000000C
-		X"409A6800", -- 00000010
-		X"401A7800", -- 00000014
-		X"00000000", -- 00000018
-		X"409AF800", -- 0000001C
-		X"3C1ABFC0", -- 00000020
-		X"275A01C4", -- 00000024
-		X"03400008", -- 00000028
-		X"00000000", -- 0000002C
-		X"00000000", -- 00000030
-		X"00000000", -- 00000034
-		X"00000000", -- 00000038
-		X"00000000", -- 0000003C
-		X"00000000", -- 00000040
-		X"00000000", -- 00000044
-		X"00000000", -- 00000048
-		X"00000000", -- 0000004C
-		X"00000000", -- 00000050
-		X"00000000", -- 00000054
-		X"00000000", -- 00000058
-		X"00000000", -- 0000005C
-		X"00000000", -- 00000060
-		X"00000000", -- 00000064
-		X"00000000", -- 00000068
-		X"00000000", -- 0000006C
-		X"00000000", -- 00000070
-		X"00000000", -- 00000074
-		X"00000000", -- 00000078
-		X"00000000", -- 0000007C
-		X"00000000", -- 00000080
-		X"00000000", -- 00000084
-		X"00000000", -- 00000088
-		X"00000000", -- 0000008C
-		X"00000000", -- 00000090
-		X"00000000", -- 00000094
-		X"00000000", -- 00000098
-		X"00000000", -- 0000009C
-		X"00000000", -- 000000A0
-		X"00000000", -- 000000A4
-		X"00000000", -- 000000A8
-		X"00000000", -- 000000AC
-		X"00000000", -- 000000B0
-		X"00000000", -- 000000B4
-		X"00000000", -- 000000B8
-		X"00000000", -- 000000BC
-		X"00000000", -- 000000C0
-		X"00000000", -- 000000C4
-		X"00000000", -- 000000C8
-		X"00000000", -- 000000CC
-		X"00000000", -- 000000D0
-		X"00000000", -- 000000D4
-		X"00000000", -- 000000D8
-		X"00000000", -- 000000DC
-		X"00000000", -- 000000E0
-		X"00000000", -- 000000E4
-		X"00000000", -- 000000E8
-		X"00000000", -- 000000EC
-		X"00000000", -- 000000F0
-		X"00000000", -- 000000F4
-		X"00000000", -- 000000F8
-		X"00000000", -- 000000FC
-		X"00000000", -- 00000100
-		X"00000000", -- 00000104
-		X"00000000", -- 00000108
-		X"00000000", -- 0000010C
-		X"00000000", -- 00000110
-		X"00000000", -- 00000114
-		X"00000000", -- 00000118
-		X"00000000", -- 0000011C
-		X"00000000", -- 00000120
-		X"00000000", -- 00000124
-		X"00000000", -- 00000128
-		X"00000000", -- 0000012C
-		X"00000000", -- 00000130
-		X"00000000", -- 00000134
-		X"00000000", -- 00000138
-		X"00000000", -- 0000013C
-		X"00000000", -- 00000140
-		X"00000000", -- 00000144
-		X"00000000", -- 00000148
-		X"00000000", -- 0000014C
-		X"00000000", -- 00000150
-		X"00000000", -- 00000154
-		X"00000000", -- 00000158
-		X"00000000", -- 0000015C
-		X"00000000", -- 00000160
-		X"00000000", -- 00000164
-		X"00000000", -- 00000168
-		X"00000000", -- 0000016C
-		X"00000000", -- 00000170
-		X"00000000", -- 00000174
-		X"00000000", -- 00000178
-		X"00000000", -- 0000017C
-		X"401A6800", -- 00000180
-		X"3C1BA000", -- 00000184
-		X"277B0000", -- 00000188
-		X"001AD082", -- 0000018C
-		X"335A000F", -- 00000190
-		X"035BD025", -- 00000194
-		X"AF7A0000", -- 00000198
-		X"401A6800", -- 0000019C
-		X"00000000", -- 000001A0
-		X"001AD202", -- 000001A4
-		X"335A00FF", -- 000001A8
-		X"1740FFFB", -- 000001AC
-		X"00000000", -- 000001B0
-		X"401A7000", -- 000001B4
-		X"00000000", -- 000001B8
-		X"03400008", -- 000001BC
-		X"42000010", -- 000001C0
-		X"3C1AA001", -- 000001C4
-		X"275A0008", -- 000001C8
-		X"241B000D", -- 000001CC
-		X"A35B0000", -- 000001D0
-		X"3C1D8000", -- 000001D4
-		X"27BDFFF0", -- 000001D8
-		X"241A0005", -- 000001DC
-		X"1340009F", -- 000001E0
-		X"241AFFFB", -- 000001E4
-		X"1340009D", -- 000001E8
-		X"241A0000", -- 000001EC
-		X"13400003", -- 000001F0
-		X"00000000", -- 000001F4
-		X"0BF00118", -- 000001F8
-		X"00000000", -- 000001FC
-		X"241A0005", -- 00000200
-		X"241B0006", -- 00000204
-		X"135B0095", -- 00000208
-		X"241AFFFB", -- 0000020C
-		X"135B0093", -- 00000210
-		X"241A0000", -- 00000214
-		X"135B0091", -- 00000218
-		X"241A0006", -- 0000021C
-		X"135B0003", -- 00000220
-		X"00000000", -- 00000224
-		X"0BF00118", -- 00000228
-		X"00000000", -- 0000022C
-		X"241AFFFB", -- 00000230
-		X"0741008A", -- 00000234
-		X"241A0005", -- 00000238
-		X"07410002", -- 0000023C
-		X"00000000", -- 00000240
-		X"0BF00118", -- 00000244
-		X"241A0000", -- 00000248
-		X"07410002", -- 0000024C
-		X"00000000", -- 00000250
-		X"0BF00118", -- 00000254
-		X"241AFFFB", -- 00000258
-		X"1F400080", -- 0000025C
-		X"241A0000", -- 00000260
-		X"1F40007E", -- 00000264
-		X"241A0005", -- 00000268
-		X"1F400002", -- 0000026C
-		X"00000000", -- 00000270
-		X"0BF00118", -- 00000274
-		X"241A0005", -- 00000278
-		X"1B400078", -- 0000027C
-		X"241A0000", -- 00000280
-		X"1B400002", -- 00000284
-		X"00000000", -- 00000288
-		X"0BF00118", -- 0000028C
-		X"241AFFFB", -- 00000290
-		X"1B400002", -- 00000294
-		X"00000000", -- 00000298
-		X"0BF00118", -- 0000029C
-		X"241A0005", -- 000002A0
-		X"0740006E", -- 000002A4
-		X"241A0000", -- 000002A8
-		X"0740006C", -- 000002AC
-		X"241AFFFB", -- 000002B0
-		X"07400002", -- 000002B4
-		X"00000000", -- 000002B8
-		X"0BF00118", -- 000002BC
-		X"241A0005", -- 000002C0
-		X"241B0006", -- 000002C4
-		X"175B0002", -- 000002C8
-		X"00000000", -- 000002CC
-		X"0BF00118", -- 000002D0
-		X"241AFFFB", -- 000002D4
-		X"175B0002", -- 000002D8
-		X"00000000", -- 000002DC
-		X"0BF00118", -- 000002E0
-		X"241AFFFA", -- 000002E4
-		X"175B0002", -- 000002E8
-		X"00000000", -- 000002EC
-		X"0BF00118", -- 000002F0
-		X"241A0000", -- 000002F4
-		X"175B0002", -- 000002F8
-		X"00000000", -- 000002FC
-		X"0BF00118", -- 00000300
-		X"241A0006", -- 00000304
-		X"175B0055", -- 00000308
-		X"241A0005", -- 0000030C
-		X"17400002", -- 00000310
-		X"00000000", -- 00000314
-		X"0BF00118", -- 00000318
-		X"241AFFFB", -- 0000031C
-		X"17400002", -- 00000320
-		X"00000000", -- 00000324
-		X"0BF00118", -- 00000328
-		X"241A0000", -- 0000032C
-		X"1740004B", -- 00000330
-		X"241B0005", -- 00000334
-		X"2F7A0006", -- 00000338
-		X"2F7AFFFA", -- 0000033C
-		X"241BFFFB", -- 00000340
-		X"2F7A0006", -- 00000344
-		X"2F7AFFFA", -- 00000348
-		X"241B0006", -- 0000034C
-		X"2F7A0005", -- 00000350
-		X"2F7AFFFB", -- 00000354
-		X"241BFFFA", -- 00000358
-		X"2F7A0005", -- 0000035C
-		X"2F7AFFFB", -- 00000360
-		X"241B0005", -- 00000364
-		X"2B7A0006", -- 00000368
-		X"2B7AFFFA", -- 0000036C
-		X"241BFFFB", -- 00000370
-		X"2B7A0006", -- 00000374
-		X"2B7AFFFA", -- 00000378
-		X"241B0006", -- 0000037C
-		X"2B7A0005", -- 00000380
-		X"2B7AFFFB", -- 00000384
-		X"241BFFFA", -- 00000388
-		X"2B7A0005", -- 0000038C
-		X"2B7AFFFB", -- 00000390
-		X"241A0005", -- 00000394
-		X"241B0006", -- 00000398
-		X"035BD02B", -- 0000039C
-		X"241A0005", -- 000003A0
-		X"241BFFFA", -- 000003A4
-		X"035BD02B", -- 000003A8
-		X"241AFFFB", -- 000003AC
-		X"241B0006", -- 000003B0
-		X"035BD02B", -- 000003B4
-		X"241AFFFB", -- 000003B8
-		X"241BFFFA", -- 000003BC
-		X"035BD02B", -- 000003C0
-		X"241A0006", -- 000003C4
-		X"241B0005", -- 000003C8
-		X"035BD02B", -- 000003CC
-		X"241A0006", -- 000003D0
-		X"241BFFFB", -- 000003D4
-		X"035BD02B", -- 000003D8
-		X"241AFFFA", -- 000003DC
-		X"241B0005", -- 000003E0
-		X"035BD02B", -- 000003E4
-		X"241AFFFA", -- 000003E8
-		X"241BFFFB", -- 000003EC
-		X"035BD02B", -- 000003F0
-		X"241A0005", -- 000003F4
-		X"241B0006", -- 000003F8
-		X"035BD02A", -- 000003FC
-		X"241A0005", -- 00000400
-		X"241BFFFA", -- 00000404
-		X"035BD02A", -- 00000408
-		X"241AFFFB", -- 0000040C
-		X"241B0006", -- 00000410
-		X"035BD02A", -- 00000414
-		X"241AFFFB", -- 00000418
-		X"241BFFFA", -- 0000041C
-		X"035BD02A", -- 00000420
-		X"241A0006", -- 00000424
-		X"241B0005", -- 00000428
-		X"035BD02A", -- 0000042C
-		X"241A0006", -- 00000430
-		X"241BFFFB", -- 00000434
-		X"035BD02A", -- 00000438
-		X"241AFFFA", -- 0000043C
-		X"241B0005", -- 00000440
-		X"035BD02A", -- 00000444
-		X"241AFFFA", -- 00000448
-		X"241BFFFB", -- 0000044C
-		X"035BD02A", -- 00000450
-		X"3C1ABFC0", -- 00000454
-		X"275A0FC8", -- 00000458
-		X"0340F809", -- 0000045C
-		X"00000000", -- 00000460
-		X"0BF00118", -- 00000464
-		X"00000000", -- 00000468
-		X"40026000", -- 0000046C
-		X"03E00008", -- 00000470
-		X"00000000", -- 00000474
-		X"40846000", -- 00000478
-		X"03E00008", -- 0000047C
-		X"00000000", -- 00000480
-		X"40026800", -- 00000484
-		X"03E00008", -- 00000488
-		X"00000000", -- 0000048C
-		X"40846800", -- 00000490
-		X"03E00008", -- 00000494
-		X"00000000", -- 00000498
-		X"40027800", -- 0000049C
-		X"03E00008", -- 000004A0
-		X"00000000", -- 000004A4
-		X"3C02A001", -- 000004A8
-		X"34430004", -- 000004AC
-		X"8C620000", -- 000004B0
-		X"00000000", -- 000004B4
-		X"30420010", -- 000004B8
-		X"1040FFFC", -- 000004BC
-		X"3C02A001", -- 000004C0
-		X"8C420000", -- 000004C4
-		X"00000000", -- 000004C8
-		X"00021600", -- 000004CC
-		X"03E00008", -- 000004D0
-		X"00021603", -- 000004D4
-		X"00042600", -- 000004D8
-		X"3C02A001", -- 000004DC
-		X"00042603", -- 000004E0
-		X"34430004", -- 000004E4
-		X"8C620000", -- 000004E8
-		X"00000000", -- 000004EC
-		X"30420002", -- 000004F0
-		X"1440FFFC", -- 000004F4
-		X"3C02A001", -- 000004F8
-		X"AC440000", -- 000004FC
-		X"03E00008", -- 00000500
-		X"00000000", -- 00000504
-		X"00042600", -- 00000508
-		X"00042603", -- 0000050C
-		X"2402000A", -- 00000510
-		X"1482000A", -- 00000514
-		X"3C02A001", -- 00000518
-		X"34430004", -- 0000051C
-		X"8C620000", -- 00000520
-		X"00000000", -- 00000524
-		X"30420002", -- 00000528
-		X"1440FFFC", -- 0000052C
-		X"3C02A001", -- 00000530
-		X"2403000D", -- 00000534
-		X"AC430000", -- 00000538
-		X"3C02A001", -- 0000053C
-		X"34430004", -- 00000540
-		X"8C620000", -- 00000544
-		X"00000000", -- 00000548
-		X"30420002", -- 0000054C
-		X"1440FFFC", -- 00000550
-		X"3C02A001", -- 00000554
-		X"AC440000", -- 00000558
-		X"03E00008", -- 0000055C
-		X"00000000", -- 00000560
-		X"3C02A001", -- 00000564
-		X"34470004", -- 00000568
-		X"00802821", -- 0000056C
-		X"2409000A", -- 00000570
-		X"3C06A001", -- 00000574
-		X"0BF0016F", -- 00000578
-		X"2408000D", -- 0000057C
-		X"14690007", -- 00000580
-		X"00000000", -- 00000584
-		X"8CE20000", -- 00000588
-		X"00000000", -- 0000058C
-		X"30420002", -- 00000590
-		X"1440FFFC", -- 00000594
-		X"00000000", -- 00000598
-		X"ACC80000", -- 0000059C
-		X"8CE20000", -- 000005A0
-		X"00000000", -- 000005A4
-		X"30420002", -- 000005A8
-		X"1440FFFC", -- 000005AC
-		X"00000000", -- 000005B0
-		X"ACC30000", -- 000005B4
-		X"24A50001", -- 000005B8
-		X"80A30000", -- 000005BC
-		X"00000000", -- 000005C0
-		X"1460FFEE", -- 000005C4
-		X"00A41023", -- 000005C8
-		X"03E00008", -- 000005CC
-		X"00000000", -- 000005D0
-		X"00042600", -- 000005D4
-		X"3C02A001", -- 000005D8
-		X"00042603", -- 000005DC
-		X"344A0004", -- 000005E0
-		X"00003821", -- 000005E4
-		X"3C09A001", -- 000005E8
-		X"24080002", -- 000005EC
-		X"308200FF", -- 000005F0
-		X"00022902", -- 000005F4
-		X"00041100", -- 000005F8
-		X"00022600", -- 000005FC
-		X"2CA3000A", -- 00000600
-		X"00042603", -- 00000604
-		X"14600002", -- 00000608
-		X"24A60030", -- 0000060C
-		X"24A60037", -- 00000610
-		X"8D420000", -- 00000614
-		X"00000000", -- 00000618
-		X"30420002", -- 0000061C
-		X"1440FFFC", -- 00000620
-		X"00061600", -- 00000624
-		X"00021603", -- 00000628
-		X"24E70001", -- 0000062C
-		X"AD220000", -- 00000630
-		X"14E8FFEF", -- 00000634
-		X"308200FF", -- 00000638
-		X"03E00008", -- 0000063C
-		X"00000000", -- 00000640
-		X"27BDFFE0", -- 00000644
-		X"AFB20018", -- 00000648
-		X"AFB10014", -- 0000064C
-		X"AFB00010", -- 00000650
-		X"AFBF001C", -- 00000654
-		X"00808821", -- 00000658
-		X"00008021", -- 0000065C
-		X"24120004", -- 00000660
-		X"00112603", -- 00000664
-		X"0FF00175", -- 00000668
-		X"26100001", -- 0000066C
-		X"1612FFFC", -- 00000670
-		X"00118A00", -- 00000674
-		X"8FBF001C", -- 00000678
-		X"8FB20018", -- 0000067C
-		X"8FB10014", -- 00000680
-		X"8FB00010", -- 00000684
-		X"03E00008", -- 00000688
-		X"27BD0020", -- 0000068C
-		X"8C840000", -- 00000690
-		X"3C020070", -- 00000694
-		X"34420070", -- 00000698
-		X"3C0300FF", -- 0000069C
-		X"AC820000", -- 000006A0
-		X"346300FF", -- 000006A4
-		X"8C820000", -- 000006A8
-		X"AC830000", -- 000006AC
-		X"03E00008", -- 000006B0
-		X"00000000", -- 000006B4
-		X"AC850000", -- 000006B8
-		X"2482001C", -- 000006BC
-		X"0BF001B4", -- 000006C0
-		X"24840004", -- 000006C4
-		X"A0800000", -- 000006C8
-		X"24840001", -- 000006CC
-		X"1482FFFD", -- 000006D0
-		X"00000000", -- 000006D4
-		X"03E00008", -- 000006D8
-		X"00000000", -- 000006DC
-		X"3C02BFC0", -- 000006E0
-		X"24431580", -- 000006E4
-		X"8C421580", -- 000006E8
-		X"27BDFFF0", -- 000006EC
-		X"00804021", -- 000006F0
-		X"8D070000", -- 000006F4
-		X"8C640008", -- 000006F8
-		X"AFA20000", -- 000006FC
-		X"8C630004", -- 00000700
-		X"3C020098", -- 00000704
-		X"34420098", -- 00000708
-		X"AFA30004", -- 0000070C
-		X"AFA40008", -- 00000710
-		X"00002821", -- 00000714
-		X"ACE20000", -- 00000718
-		X"2406000C", -- 0000071C
-		X"00E51021", -- 00000720
-		X"03A51821", -- 00000724
-		X"90440040", -- 00000728
-		X"90620000", -- 0000072C
-		X"00000000", -- 00000730
-		X"10820003", -- 00000734
-		X"24A50001", -- 00000738
-		X"0BF00213", -- 0000073C
-		X"2405FFFF", -- 00000740
-		X"14A6FFF7", -- 00000744
-		X"00E51021", -- 00000748
-		X"3C0200FF", -- 0000074C
-		X"344200FF", -- 00000750
-		X"ACE20000", -- 00000754
-		X"3C020090", -- 00000758
-		X"34420090", -- 0000075C
-		X"ACE20000", -- 00000760
-		X"94E4009C", -- 00000764
-		X"24030002", -- 00000768
-		X"24020020", -- 0000076C
-		X"AD030004", -- 00000770
-		X"AD030018", -- 00000774
-		X"AD020014", -- 00000778
-		X"3084FFFF", -- 0000077C
-		X"0BF001E6", -- 00000780
-		X"00001821", -- 00000784
-		X"8D020004", -- 00000788
-		X"00000000", -- 0000078C
-		X"00021040", -- 00000790
-		X"AD020004", -- 00000794
-		X"0064102B", -- 00000798
-		X"1440FFFA", -- 0000079C
-		X"24630001", -- 000007A0
-		X"94E200AC", -- 000007A4
-		X"94E300A8", -- 000007A8
-		X"3042FFFF", -- 000007AC
-		X"8D040018", -- 000007B0
-		X"3063FFFF", -- 000007B4
-		X"00021200", -- 000007B8
-		X"00432825", -- 000007BC
-		X"AD040010", -- 000007C0
-		X"0BF001F7", -- 000007C4
-		X"00001821", -- 000007C8
-		X"8D020010", -- 000007CC
-		X"00000000", -- 000007D0
-		X"00021040", -- 000007D4
-		X"AD020010", -- 000007D8
-		X"0065102B", -- 000007DC
-		X"1440FFFA", -- 000007E0
-		X"24630001", -- 000007E4
-		X"94E200B8", -- 000007E8
-		X"94E400B4", -- 000007EC
-		X"3042FFFF", -- 000007F0
-		X"3084FFFF", -- 000007F4
-		X"00021200", -- 000007F8
-		X"8D060018", -- 000007FC
-		X"00441025", -- 00000800
-		X"24420001", -- 00000804
-		X"00460018", -- 00000808
-		X"94E300C0", -- 0000080C
-		X"94E500BC", -- 00000810
-		X"3063FFFF", -- 00000814
-		X"30A5FFFF", -- 00000818
-		X"00031A00", -- 0000081C
-		X"00651825", -- 00000820
-		X"00062200", -- 00000824
-		X"00002821", -- 00000828
-		X"00001012", -- 0000082C
-		X"AD02000C", -- 00000830
-		X"3C0200FF", -- 00000834
-		X"00830018", -- 00000838
-		X"344200FF", -- 0000083C
-		X"00002012", -- 00000840
-		X"AD040008", -- 00000844
-		X"ACE20000", -- 00000848
-		X"00A01021", -- 0000084C
-		X"03E00008", -- 00000850
-		X"27BD0010", -- 00000854
-		X"8C820004", -- 00000858
-		X"00A03021", -- 0000085C
-		X"00021082", -- 00000860
-		X"00A2102B", -- 00000864
-		X"8C850000", -- 00000868
-		X"10400018", -- 0000086C
-		X"2403FFFF", -- 00000870
-		X"8C82000C", -- 00000874
-		X"00000000", -- 00000878
-		X"2442FFFF", -- 0000087C
-		X"00021400", -- 00000880
-		X"00C21024", -- 00000884
-		X"00021080", -- 00000888
-		X"00A22021", -- 0000088C
-		X"3C020020", -- 00000890
-		X"34420020", -- 00000894
-		X"AC820000", -- 00000898
-		X"3C0200D0", -- 0000089C
-		X"344200D0", -- 000008A0
-		X"AC820000", -- 000008A4
-		X"3C020080", -- 000008A8
-		X"34430080", -- 000008AC
-		X"8C820000", -- 000008B0
-		X"00000000", -- 000008B4
-		X"00431024", -- 000008B8
-		X"1443FFFC", -- 000008BC
-		X"3C0200FF", -- 000008C0
-		X"344200FF", -- 000008C4
-		X"AC820000", -- 000008C8
-		X"00001821", -- 000008CC
-		X"03E00008", -- 000008D0
-		X"00601021", -- 000008D4
-		X"8C820004", -- 000008D8
-		X"00000000", -- 000008DC
-		X"00021082", -- 000008E0
-		X"00A2102B", -- 000008E4
-		X"8C840000", -- 000008E8
-		X"10400011", -- 000008EC
-		X"2403FFFF", -- 000008F0
-		X"00051080", -- 000008F4
-		X"00822021", -- 000008F8
-		X"3C020040", -- 000008FC
-		X"34420040", -- 00000900
-		X"AC820000", -- 00000904
-		X"3C020080", -- 00000908
-		X"AC860000", -- 0000090C
-		X"34430080", -- 00000910
-		X"8C820000", -- 00000914
-		X"00000000", -- 00000918
-		X"00431024", -- 0000091C
-		X"1443FFFC", -- 00000920
-		X"3C0200FF", -- 00000924
-		X"344200FF", -- 00000928
-		X"AC820000", -- 0000092C
-		X"00001821", -- 00000930
-		X"03E00008", -- 00000934
-		X"00601021", -- 00000938
-		X"8C820004", -- 0000093C
-		X"27BDFFF0", -- 00000940
-		X"00021082", -- 00000944
-		X"00A2102B", -- 00000948
-		X"AFB2000C", -- 0000094C
-		X"AFB10008", -- 00000950
-		X"AFB00004", -- 00000954
-		X"00807021", -- 00000958
-		X"00C09021", -- 0000095C
-		X"8C8F0000", -- 00000960
-		X"10400045", -- 00000964
-		X"2403FFFF", -- 00000968
-		X"8C82000C", -- 0000096C
-		X"00006021", -- 00000970
-		X"2442FFFF", -- 00000974
-		X"0002C400", -- 00000978
-		X"3C0200E8", -- 0000097C
-		X"345100E8", -- 00000980
-		X"3C020080", -- 00000984
-		X"344D0080", -- 00000988
-		X"3C0200D0", -- 0000098C
-		X"345000D0", -- 00000990
-		X"3C0200FF", -- 00000994
-		X"344600FF", -- 00000998
-		X"0BF0029C", -- 0000099C
-		X"3C190001", -- 000009A0
-		X"00651023", -- 000009A4
-		X"00595021", -- 000009A8
-		X"00EA102B", -- 000009AC
-		X"10400002", -- 000009B0
-		X"00031080", -- 000009B4
-		X"00E05021", -- 000009B8
-		X"0BF0029A", -- 000009BC
-		X"01E25821", -- 000009C0
-		X"AD710000", -- 000009C4
-		X"8D620000", -- 000009C8
-		X"00000000", -- 000009CC
-		X"004D1024", -- 000009D0
-		X"144DFFFC", -- 000009D4
-		X"00000000", -- 000009D8
-		X"8DC20010", -- 000009DC
-		X"00000000", -- 000009E0
-		X"00021882", -- 000009E4
-		X"006A102B", -- 000009E8
-		X"10400002", -- 000009EC
-		X"01404021", -- 000009F0
-		X"00604021", -- 000009F4
-		X"2503FFFF", -- 000009F8
-		X"00031400", -- 000009FC
-		X"00431025", -- 00000A00
-		X"00052080", -- 00000A04
-		X"000C1880", -- 00000A08
-		X"02434821", -- 00000A0C
-		X"AD620000", -- 00000A10
-		X"01E42021", -- 00000A14
-		X"0BF0028C", -- 00000A18
-		X"00001821", -- 00000A1C
-		X"8D220000", -- 00000A20
-		X"25290004", -- 00000A24
-		X"AC820000", -- 00000A28
-		X"24840004", -- 00000A2C
-		X"0068102B", -- 00000A30
-		X"1440FFFA", -- 00000A34
-		X"24630001", -- 00000A38
-		X"01886021", -- 00000A3C
-		X"AD700000", -- 00000A40
-		X"8D620000", -- 00000A44
-		X"00000000", -- 00000A48
-		X"004D1024", -- 00000A4C
-		X"144DFFFC", -- 00000A50
-		X"00000000", -- 00000A54
-		X"00E83823", -- 00000A58
-		X"00A82821", -- 00000A5C
-		X"01485023", -- 00000A60
-		X"AD660000", -- 00000A64
-		X"1540FFD6", -- 00000A68
-		X"00000000", -- 00000A6C
-		X"14E0FFCC", -- 00000A70
-		X"00B81824", -- 00000A74
-		X"00001821", -- 00000A78
-		X"00601021", -- 00000A7C
-		X"8FB2000C", -- 00000A80
-		X"8FB10008", -- 00000A84
-		X"8FB00004", -- 00000A88
-		X"03E00008", -- 00000A8C
-		X"27BD0010", -- 00000A90
-		X"AC850000", -- 00000A94
-		X"24820004", -- 00000A98
-		X"0BF002AB", -- 00000A9C
-		X"2483001C", -- 00000AA0
-		X"A0400000", -- 00000AA4
-		X"24420001", -- 00000AA8
-		X"1443FFFD", -- 00000AAC
-		X"00000000", -- 00000AB0
-		X"0BF001B8", -- 00000AB4
-		X"00000000", -- 00000AB8
-		X"27BDFFE0", -- 00000ABC
-		X"AFB20018", -- 00000AC0
-		X"AFB10014", -- 00000AC4
-		X"AFB00010", -- 00000AC8
-		X"AFBF001C", -- 00000ACC
-		X"00809021", -- 00000AD0
-		X"00C58821", -- 00000AD4
-		X"0BF002BD", -- 00000AD8
-		X"00A08021", -- 00000ADC
-		X"0FF00216", -- 00000AE0
-		X"00000000", -- 00000AE4
-		X"8E420008", -- 00000AE8
-		X"00000000", -- 00000AEC
-		X"02028021", -- 00000AF0
-		X"00102FC3", -- 00000AF4
-		X"00052F82", -- 00000AF8
-		X"00B02821", -- 00000AFC
-		X"0211102B", -- 00000B00
-		X"00052883", -- 00000B04
-		X"1440FFF5", -- 00000B08
-		X"02402021", -- 00000B0C
-		X"8FBF001C", -- 00000B10
-		X"00001021", -- 00000B14
-		X"8FB20018", -- 00000B18
-		X"8FB10014", -- 00000B1C
-		X"8FB00010", -- 00000B20
-		X"03E00008", -- 00000B24
-		X"27BD0020", -- 00000B28
-		X"00052882", -- 00000B2C
-		X"0BF0024F", -- 00000B30
-		X"00073882", -- 00000B34
-		X"8C820000", -- 00000B38
-		X"00002021", -- 00000B3C
-		X"0BF002D7", -- 00000B40
-		X"00454021", -- 00000B44
-		X"90630000", -- 00000B48
-		X"90A20000", -- 00000B4C
-		X"00000000", -- 00000B50
-		X"14620006", -- 00000B54
-		X"2402FFFF", -- 00000B58
-		X"0087102B", -- 00000B5C
-		X"01041821", -- 00000B60
-		X"00C42821", -- 00000B64
-		X"1440FFF7", -- 00000B68
-		X"24840001", -- 00000B6C
-		X"03E00008", -- 00000B70
-		X"00000000", -- 00000B74
-		X"90830000", -- 00000B78
-		X"00000000", -- 00000B7C
-		X"2C620041", -- 00000B80
-		X"14400002", -- 00000B84
-		X"2462FFD0", -- 00000B88
-		X"2462FFC9", -- 00000B8C
-		X"90840001", -- 00000B90
-		X"304200FF", -- 00000B94
-		X"304300FF", -- 00000B98
-		X"2C820041", -- 00000B9C
-		X"14400003", -- 00000BA0
-		X"00000000", -- 00000BA4
-		X"0BF002ED", -- 00000BA8
-		X"2482FFC9", -- 00000BAC
-		X"2482FFD0", -- 00000BB0
-		X"304400FF", -- 00000BB4
-		X"00031100", -- 00000BB8
-		X"00821025", -- 00000BBC
-		X"03E00008", -- 00000BC0
-		X"304200FF", -- 00000BC4
-		X"10C00094", -- 00000BC8
-		X"00805021", -- 00000BCC
-		X"24020003", -- 00000BD0
-		X"AC820008", -- 00000BD4
-		X"90A40001", -- 00000BD8
-		X"00000000", -- 00000BDC
-		X"2482FFCF", -- 00000BE0
-		X"304200FF", -- 00000BE4
-		X"2C420003", -- 00000BE8
-		X"10400005", -- 00000BEC
-		X"2482FFC9", -- 00000BF0
-		X"24020002", -- 00000BF4
-		X"AD420008", -- 00000BF8
-		X"0BF0030F", -- 00000BFC
-		X"2489FFD1", -- 00000C00
-		X"304200FF", -- 00000C04
-		X"2C420003", -- 00000C08
-		X"10400006", -- 00000C0C
-		X"24020030", -- 00000C10
-		X"2402003B", -- 00000C14
-		X"00444823", -- 00000C18
-		X"24020004", -- 00000C1C
-		X"0BF0030F", -- 00000C20
-		X"AD420008", -- 00000C24
-		X"14820004", -- 00000C28
-		X"00004821", -- 00000C2C
-		X"24020001", -- 00000C30
-		X"AD420008", -- 00000C34
-		X"24090002", -- 00000C38
-		X"90A30002", -- 00000C3C
-		X"00000000", -- 00000C40
-		X"2C620041", -- 00000C44
-		X"10400003", -- 00000C48
-		X"24A40002", -- 00000C4C
-		X"0BF00317", -- 00000C50
-		X"2462FFD0", -- 00000C54
-		X"2462FFC9", -- 00000C58
-		X"90830001", -- 00000C5C
-		X"304200FF", -- 00000C60
-		X"304400FF", -- 00000C64
-		X"2C620041", -- 00000C68
-		X"10400002", -- 00000C6C
-		X"2462FFC9", -- 00000C70
-		X"2462FFD0", -- 00000C74
-		X"304300FF", -- 00000C78
-		X"00041100", -- 00000C7C
-		X"00621025", -- 00000C80
-		X"304200FF", -- 00000C84
-		X"AD420004", -- 00000C88
-		X"AD400000", -- 00000C8C
-		X"00405821", -- 00000C90
-		X"00A03021", -- 00000C94
-		X"0BF00343", -- 00000C98
-		X"00003821", -- 00000C9C
-		X"90C20004", -- 00000CA0
-		X"00000000", -- 00000CA4
-		X"2443FFC9", -- 00000CA8
-		X"2444FFD0", -- 00000CAC
-		X"2C420041", -- 00000CB0
-		X"10400002", -- 00000CB4
-		X"306300FF", -- 00000CB8
-		X"308300FF", -- 00000CBC
-		X"90C20005", -- 00000CC0
-		X"306800FF", -- 00000CC4
-		X"2444FFC9", -- 00000CC8
-		X"2443FFD0", -- 00000CCC
-		X"2C420041", -- 00000CD0
-		X"10400002", -- 00000CD4
-		X"308400FF", -- 00000CD8
-		X"306400FF", -- 00000CDC
-		X"8D430000", -- 00000CE0
-		X"00081100", -- 00000CE4
-		X"00821025", -- 00000CE8
-		X"304200FF", -- 00000CEC
-		X"00031A00", -- 00000CF0
-		X"004B2021", -- 00000CF4
-		X"00431025", -- 00000CF8
-		X"AD420000", -- 00000CFC
-		X"308B00FF", -- 00000D00
-		X"24E70001", -- 00000D04
-		X"24C60002", -- 00000D08
-		X"00E9102A", -- 00000D0C
-		X"1440FFE3", -- 00000D10
-		X"25220002", -- 00000D14
-		X"8D440004", -- 00000D18
-		X"00021040", -- 00000D1C
-		X"00091827", -- 00000D20
-		X"00832021", -- 00000D24
-		X"00A21021", -- 00000D28
-		X"AD440004", -- 00000D2C
-		X"AD42000C", -- 00000D30
-		X"0BF00367", -- 00000D34
-		X"00003021", -- 00000D38
-		X"90E20000", -- 00000D3C
-		X"00000000", -- 00000D40
-		X"2444FFC9", -- 00000D44
-		X"2445FFD0", -- 00000D48
-		X"2C420041", -- 00000D4C
-		X"10400002", -- 00000D50
-		X"308400FF", -- 00000D54
-		X"30A400FF", -- 00000D58
-		X"90E20001", -- 00000D5C
-		X"308700FF", -- 00000D60
-		X"2445FFC9", -- 00000D64
-		X"2444FFD0", -- 00000D68
-		X"2C420041", -- 00000D6C
-		X"14400002", -- 00000D70
-		X"308400FF", -- 00000D74
-		X"30A400FF", -- 00000D78
-		X"00071100", -- 00000D7C
-		X"00821025", -- 00000D80
-		X"304200FF", -- 00000D84
-		X"00661821", -- 00000D88
-		X"004B2021", -- 00000D8C
-		X"A0620000", -- 00000D90
-		X"308B00FF", -- 00000D94
-		X"24C60001", -- 00000D98
-		X"8D420004", -- 00000D9C
-		X"8D43000C", -- 00000DA0
-		X"00062040", -- 00000DA4
-		X"00C2102A", -- 00000DA8
-		X"1440FFE3", -- 00000DAC
-		X"00643821", -- 00000DB0
-		X"90E40000", -- 00000DB4
-		X"00000000", -- 00000DB8
-		X"2C820041", -- 00000DBC
-		X"10400003", -- 00000DC0
-		X"00E01821", -- 00000DC4
-		X"0BF00375", -- 00000DC8
-		X"2482FFD0", -- 00000DCC
-		X"2482FFC9", -- 00000DD0
-		X"90630001", -- 00000DD4
-		X"304200FF", -- 00000DD8
-		X"304400FF", -- 00000DDC
-		X"2C620041", -- 00000DE0
-		X"10400002", -- 00000DE4
-		X"2462FFC9", -- 00000DE8
-		X"2462FFD0", -- 00000DEC
-		X"304200FF", -- 00000DF0
-		X"00041900", -- 00000DF4
-		X"00431825", -- 00000DF8
-		X"000B1027", -- 00000DFC
-		X"304200FF", -- 00000E00
-		X"306300FF", -- 00000E04
-		X"14430004", -- 00000E08
-		X"00000000", -- 00000E0C
-		X"8D420008", -- 00000E10
-		X"03E00008", -- 00000E14
-		X"00000000", -- 00000E18
-		X"03E00008", -- 00000E1C
-		X"00001021", -- 00000E20
-		X"00800008", -- 00000E24
-		X"00000000", -- 00000E28
-		X"03E00008", -- 00000E2C
-		X"00000000", -- 00000E30
-		X"401A6000", -- 00000E34
-		X"3C1BFFBF", -- 00000E38
-		X"377BFFFF", -- 00000E3C
-		X"035BD024", -- 00000E40
-		X"409A6000", -- 00000E44
-		X"00800008", -- 00000E48
-		X"42000010", -- 00000E4C
-		X"03E00008", -- 00000E50
-		X"00000000", -- 00000E54
-		X"27BDFFC0", -- 00000E58
-		X"AFB20038", -- 00000E5C
-		X"3C05BFC0", -- 00000E60
-		X"27B20010", -- 00000E64
-		X"24A51670", -- 00000E68
-		X"2406001C", -- 00000E6C
-		X"02402021", -- 00000E70
-		X"AFBF003C", -- 00000E74
-		X"AFB10034", -- 00000E78
-		X"0FF004BF", -- 00000E7C
-		X"AFB00030", -- 00000E80
-		X"0FF0011B", -- 00000E84
-		X"00000000", -- 00000E88
-		X"3C04BFC0", -- 00000E8C
-		X"00408021", -- 00000E90
-		X"0FF00159", -- 00000E94
-		X"2484158C", -- 00000E98
-		X"0FF00191", -- 00000E9C
-		X"02002021", -- 00000EA0
-		X"3C04BFC0", -- 00000EA4
-		X"0FF00159", -- 00000EA8
-		X"24841608", -- 00000EAC
-		X"0FF00127", -- 00000EB0
-		X"00000000", -- 00000EB4
-		X"00408821", -- 00000EB8
-		X"3C04BFC0", -- 00000EBC
-		X"00021203", -- 00000EC0
-		X"305000FF", -- 00000EC4
-		X"0FF00159", -- 00000EC8
-		X"24841598", -- 00000ECC
-		X"2602FFFF", -- 00000ED0
-		X"2C420006", -- 00000ED4
-		X"1040000D", -- 00000ED8
-		X"00101080", -- 00000EDC
-		X"02421021", -- 00000EE0
-		X"8C440000", -- 00000EE4
-		X"0FF00159", -- 00000EE8
-		X"00000000", -- 00000EEC
-		X"3C04BFC0", -- 00000EF0
-		X"0FF00159", -- 00000EF4
-		X"248415A4", -- 00000EF8
-		X"00112600", -- 00000EFC
-		X"0FF00175", -- 00000F00
-		X"00042603", -- 00000F04
-		X"0BF003C8", -- 00000F08
-		X"3C04BFC0", -- 00000F0C
-		X"3C04BFC0", -- 00000F10
-		X"0FF00159", -- 00000F14
-		X"248415AC", -- 00000F18
-		X"3C04BFC0", -- 00000F1C
-		X"8FBF003C", -- 00000F20
-		X"8FB20038", -- 00000F24
-		X"8FB10034", -- 00000F28
-		X"8FB00030", -- 00000F2C
-		X"24841608", -- 00000F30
-		X"0BF00159", -- 00000F34
-		X"27BD0040", -- 00000F38
-		X"27BDFFD8", -- 00000F3C
-		X"AFB30020", -- 00000F40
-		X"AFB10018", -- 00000F44
-		X"AFB00014", -- 00000F48
-		X"AFBF0024", -- 00000F4C
-		X"AFB2001C", -- 00000F50
-		X"00809821", -- 00000F54
-		X"24110073", -- 00000F58
-		X"24100053", -- 00000F5C
-		X"0FF0012A", -- 00000F60
-		X"00000000", -- 00000F64
-		X"14510005", -- 00000F68
-		X"00000000", -- 00000F6C
-		X"00008021", -- 00000F70
-		X"2412000A", -- 00000F74
-		X"0BF003E8", -- 00000F78
-		X"2411000D", -- 00000F7C
-		X"1450FFF7", -- 00000F80
-		X"00000000", -- 00000F84
-		X"0BF003DD", -- 00000F88
-		X"00008021", -- 00000F8C
-		X"0FF0012A", -- 00000F90
-		X"A0620000", -- 00000F94
-		X"10510003", -- 00000F98
-		X"26100001", -- 00000F9C
-		X"1452FFFB", -- 00000FA0
-		X"02701821", -- 00000FA4
-		X"8FBF0024", -- 00000FA8
-		X"02001021", -- 00000FAC
-		X"8FB30020", -- 00000FB0
-		X"8FB2001C", -- 00000FB4
-		X"8FB10018", -- 00000FB8
-		X"8FB00014", -- 00000FBC
-		X"03E00008", -- 00000FC0
-		X"27BD0028", -- 00000FC4
-		X"27BDFD98", -- 00000FC8
-		X"27A4013C", -- 00000FCC
-		X"00002821", -- 00000FD0
-		X"24060100", -- 00000FD4
-		X"AFBF0264", -- 00000FD8
-		X"AFBE0260", -- 00000FDC
-		X"AFB7025C", -- 00000FE0
-		X"AFB60258", -- 00000FE4
-		X"AFB50254", -- 00000FE8
-		X"AFB40250", -- 00000FEC
-		X"AFB3024C", -- 00000FF0
-		X"AFB20248", -- 00000FF4
-		X"AFB10244", -- 00000FF8
-		X"0FF00524", -- 00000FFC
-		X"AFB00240", -- 00001000
-		X"3C02A000", -- 00001004
-		X"AC400000", -- 00001008
-		X"8C420000", -- 0000100C
-		X"00000000", -- 00001010
-		X"1440002D", -- 00001014
-		X"3C04BFC0", -- 00001018
-		X"0FF00159", -- 0000101C
-		X"248415D0", -- 00001020
-		X"3C04BFC0", -- 00001024
-		X"0FF00159", -- 00001028
-		X"248415B4", -- 0000102C
-		X"3C02A400", -- 00001030
-		X"8C44000C", -- 00001034
-		X"8C460004", -- 00001038
-		X"8C430008", -- 0000103C
-		X"00042082", -- 00001040
-		X"00621821", -- 00001044
-		X"00C08021", -- 00001048
-		X"0BF00419", -- 0000104C
-		X"00002821", -- 00001050
-		X"8C620000", -- 00001054
-		X"24630004", -- 00001058
-		X"ACC20000", -- 0000105C
-		X"24C60004", -- 00001060
-		X"00A4102B", -- 00001064
-		X"1440FFFA", -- 00001068
-		X"24A50001", -- 0000106C
-		X"3C04BFC0", -- 00001070
-		X"0FF00159", -- 00001074
-		X"248415CC", -- 00001078
-		X"401A6000", -- 0000107C
-		X"3C1BFFBF", -- 00001080
-		X"377BFFFF", -- 00001084
-		X"035BD024", -- 00001088
-		X"409A6000", -- 0000108C
-		X"02000008", -- 00001090
-		X"42000010", -- 00001094
-		X"8FBF0264", -- 00001098
-		X"00001021", -- 0000109C
-		X"8FBE0260", -- 000010A0
-		X"8FB7025C", -- 000010A4
-		X"8FB60258", -- 000010A8
-		X"8FB50254", -- 000010AC
-		X"8FB40250", -- 000010B0
-		X"8FB3024C", -- 000010B4
-		X"8FB20248", -- 000010B8
-		X"8FB10244", -- 000010BC
-		X"8FB00240", -- 000010C0
-		X"03E00008", -- 000010C4
-		X"27BD0268", -- 000010C8
-		X"27A40020", -- 000010CC
-		X"0FF002A5", -- 000010D0
-		X"3C05A400", -- 000010D4
-		X"3C024000", -- 000010D8
-		X"3C034010", -- 000010DC
-		X"AC400000", -- 000010E0
-		X"24420004", -- 000010E4
-		X"1443FFFD", -- 000010E8
-		X"3C04BFC0", -- 000010EC
-		X"0FF00159", -- 000010F0
-		X"248415D0", -- 000010F4
-		X"3C04BFC0", -- 000010F8
-		X"0FF00159", -- 000010FC
-		X"248415D4", -- 00001100
-		X"3C02BFC0", -- 00001104
-		X"24551604", -- 00001108
-		X"3C02BFC0", -- 0000110C
-		X"245315F8", -- 00001110
-		X"00008821", -- 00001114
-		X"27B4003C", -- 00001118
-		X"27B20020", -- 0000111C
-		X"3C04BFC0", -- 00001120
-		X"0FF00159", -- 00001124
-		X"248415C8", -- 00001128
-		X"241E004A", -- 0000112C
-		X"24170046", -- 00001130
-		X"27B6013C", -- 00001134
-		X"0FF003CF", -- 00001138
-		X"02802021", -- 0000113C
-		X"00403021", -- 00001140
-		X"27A40010", -- 00001144
-		X"02802821", -- 00001148
-		X"0FF002F2", -- 0000114C
-		X"00408021", -- 00001150
-		X"3C03A000", -- 00001154
-		X"AC600000", -- 00001158
-		X"24030002", -- 0000115C
-		X"10430005", -- 00001160
-		X"24030004", -- 00001164
-		X"14430060", -- 00001168
-		X"3C034000", -- 0000116C
-		X"0BF00475", -- 00001170
-		X"3C04BFC0", -- 00001174
-		X"8FA20014", -- 00001178
-		X"8FA50010", -- 0000117C
-		X"00000000", -- 00001180
-		X"00A21821", -- 00001184
-		X"0223102B", -- 00001188
-		X"10400002", -- 0000118C
-		X"00000000", -- 00001190
-		X"00608821", -- 00001194
-		X"0BF0046E", -- 00001198
-		X"00001821", -- 0000119C
-		X"8FA2001C", -- 000011A0
-		X"00000000", -- 000011A4
-		X"00431021", -- 000011A8
-		X"90420000", -- 000011AC
-		X"24630001", -- 000011B0
-		X"A0820000", -- 000011B4
-		X"8FA20014", -- 000011B8
-		X"00000000", -- 000011BC
-		X"0062102B", -- 000011C0
-		X"1440FFF6", -- 000011C4
-		X"00652021", -- 000011C8
-		X"0BF004B9", -- 000011CC
-		X"00000000", -- 000011D0
-		X"0FF00159", -- 000011D4
-		X"248415CC", -- 000011D8
-		X"8FA50010", -- 000011DC
-		X"24020049", -- 000011E0
-		X"A3A2013E", -- 000011E4
-		X"3C04BFC0", -- 000011E8
-		X"24020031", -- 000011EC
-		X"02251823", -- 000011F0
-		X"248415E8", -- 000011F4
-		X"A3A2013F", -- 000011F8
-		X"24020100", -- 000011FC
-		X"AFA50140", -- 00001200
-		X"AFA30148", -- 00001204
-		X"AFA20144", -- 00001208
-		X"A3BE013C", -- 0000120C
-		X"A3B7013D", -- 00001210
-		X"0FF00159", -- 00001214
-		X"AFA0014C", -- 00001218
-		X"8FA60148", -- 0000121C
-		X"02402021", -- 00001220
-		X"24C60100", -- 00001224
-		X"0FF002AF", -- 00001228
-		X"00002821", -- 0000122C
-		X"04400020", -- 00001230
-		X"00000000", -- 00001234
-		X"0FF00159", -- 00001238
-		X"02A02021", -- 0000123C
-		X"3C04BFC0", -- 00001240
-		X"0FF00159", -- 00001244
-		X"2484160C", -- 00001248
-		X"02402021", -- 0000124C
-		X"00002821", -- 00001250
-		X"02C03021", -- 00001254
-		X"0FF002CB", -- 00001258
-		X"24070100", -- 0000125C
-		X"04400014", -- 00001260
-		X"00000000", -- 00001264
-		X"8FA50144", -- 00001268
-		X"8FA70148", -- 0000126C
-		X"02402021", -- 00001270
-		X"0FF002CB", -- 00001274
-		X"3C064000", -- 00001278
-		X"0440000D", -- 0000127C
-		X"00000000", -- 00001280
-		X"0FF00159", -- 00001284
-		X"02A02021", -- 00001288
-		X"3C04BFC0", -- 0000128C
-		X"0FF00159", -- 00001290
-		X"2484161C", -- 00001294
-		X"8FA50144", -- 00001298
-		X"8FA70148", -- 0000129C
-		X"02402021", -- 000012A0
-		X"0FF002CE", -- 000012A4
-		X"3C064000", -- 000012A8
-		X"04410005", -- 000012AC
-		X"00000000", -- 000012B0
-		X"0FF00159", -- 000012B4
-		X"02602021", -- 000012B8
-		X"0BF004BB", -- 000012BC
-		X"3C034000", -- 000012C0
-		X"3C04BFC0", -- 000012C4
-		X"0FF00159", -- 000012C8
-		X"2484162C", -- 000012CC
-		X"3C02BFC0", -- 000012D0
-		X"00400008", -- 000012D4
-		X"00000000", -- 000012D8
-		X"0BF0044E", -- 000012DC
-		X"00000000", -- 000012E0
-		X"0601FF94", -- 000012E4
-		X"3C034000", -- 000012E8
-		X"3C02A000", -- 000012EC
-		X"AC430000", -- 000012F0
-		X"0BF00449", -- 000012F4
-		X"3C04BFC0", -- 000012F8
-		X"00A41025", -- 000012FC
-		X"30420003", -- 00001300
-		X"00806021", -- 00001304
-		X"1440002F", -- 00001308
-		X"00A05821", -- 0000130C
-		X"00065102", -- 00001310
-		X"00804021", -- 00001314
-		X"30C6000F", -- 00001318
-		X"11400011", -- 0000131C
-		X"00A03821", -- 00001320
-		X"01404821", -- 00001324
-		X"8CE30004", -- 00001328
-		X"8CE40008", -- 0000132C
-		X"8CE5000C", -- 00001330
-		X"8CE20000", -- 00001334
-		X"2529FFFF", -- 00001338
-		X"AD020000", -- 0000133C
-		X"AD030004", -- 00001340
-		X"AD040008", -- 00001344
-		X"AD05000C", -- 00001348
-		X"24E70010", -- 0000134C
-		X"1520FFF5", -- 00001350
-		X"25080010", -- 00001354
-		X"000A1100", -- 00001358
-		X"01623821", -- 0000135C
-		X"01824021", -- 00001360
-		X"00064882", -- 00001364
-		X"1120000D", -- 00001368
-		X"30C60003", -- 0000136C
-		X"01002821", -- 00001370
-		X"00E02021", -- 00001374
-		X"01201821", -- 00001378
-		X"8C820000", -- 0000137C
-		X"2463FFFF", -- 00001380
-		X"ACA20000", -- 00001384
-		X"24840004", -- 00001388
-		X"1460FFFB", -- 0000138C
-		X"24A50004", -- 00001390
-		X"00091080", -- 00001394
-		X"01024021", -- 00001398
-		X"00E23821", -- 0000139C
-		X"10C00007", -- 000013A0
-		X"00002821", -- 000013A4
-		X"00E51021", -- 000013A8
-		X"90440000", -- 000013AC
-		X"01051821", -- 000013B0
-		X"24A50001", -- 000013B4
-		X"14A6FFFB", -- 000013B8
-		X"A0640000", -- 000013BC
-		X"03E00008", -- 000013C0
-		X"01801021", -- 000013C4
-		X"00A04021", -- 000013C8
-		X"00803821", -- 000013CC
-		X"04C00027", -- 000013D0
-		X"00C01821", -- 000013D4
-		X"3C028000", -- 000013D8
-		X"34420003", -- 000013DC
-		X"00C23024", -- 000013E0
-		X"04C0001B", -- 000013E4
-		X"00034883", -- 000013E8
-		X"1120000F", -- 000013EC
-		X"00000000", -- 000013F0
-		X"01602821", -- 000013F4
-		X"01802021", -- 000013F8
-		X"01201821", -- 000013FC
-		X"2463FFFF", -- 00001400
-		X"88A20003", -- 00001404
-		X"98A20000", -- 00001408
-		X"24A50004", -- 0000140C
-		X"A8820003", -- 00001410
-		X"B8820000", -- 00001414
-		X"1460FFF9", -- 00001418
-		X"24840004", -- 0000141C
-		X"00091080", -- 00001420
-		X"01624021", -- 00001424
-		X"01823821", -- 00001428
-		X"18C0FFE4", -- 0000142C
-		X"00002821", -- 00001430
-		X"01051021", -- 00001434
-		X"90440000", -- 00001438
-		X"00E51821", -- 0000143C
-		X"24A50001", -- 00001440
-		X"14A6FFFB", -- 00001444
-		X"A0640000", -- 00001448
-		X"03E00008", -- 0000144C
-		X"01801021", -- 00001450
-		X"24C6FFFF", -- 00001454
-		X"2402FFFC", -- 00001458
-		X"00C23025", -- 0000145C
-		X"1520FFE4", -- 00001460
-		X"24C60001", -- 00001464
-		X"0BF0050B", -- 00001468
-		X"00000000", -- 0000146C
-		X"3C028000", -- 00001470
-		X"34420003", -- 00001474
-		X"24C30003", -- 00001478
-		X"00C23024", -- 0000147C
-		X"04C1FFDA", -- 00001480
-		X"00034883", -- 00001484
-		X"0BF00516", -- 00001488
-		X"24C6FFFF", -- 0000148C
-		X"2CC20010", -- 00001490
-		X"00804821", -- 00001494
-		X"1440002D", -- 00001498
-		X"00804021", -- 0000149C
-		X"30870003", -- 000014A0
-		X"10E0000E", -- 000014A4
-		X"24820004", -- 000014A8
-		X"00052600", -- 000014AC
-		X"00471023", -- 000014B0
-		X"00042603", -- 000014B4
-		X"01201821", -- 000014B8
-		X"A0640000", -- 000014BC
-		X"24630001", -- 000014C0
-		X"1462FFFD", -- 000014C4
-		X"00000000", -- 000014C8
-		X"00071027", -- 000014CC
-		X"24C3FFFB", -- 000014D0
-		X"24440005", -- 000014D4
-		X"00623023", -- 000014D8
-		X"01244021", -- 000014DC
-		X"30A500FF", -- 000014E0
-		X"01003821", -- 000014E4
-		X"10A00005", -- 000014E8
-		X"00A01821", -- 000014EC
-		X"00051200", -- 000014F0
-		X"00451025", -- 000014F4
-		X"00021C00", -- 000014F8
-		X"00621825", -- 000014FC
-		X"000610C2", -- 00001500
-		X"1040001C", -- 00001504
-		X"30C60007", -- 00001508
-		X"01002021", -- 0000150C
-		X"00403821", -- 00001510
-		X"24E7FFFF", -- 00001514
-		X"AC830000", -- 00001518
-		X"AC830004", -- 0000151C
-		X"14E0FFFC", -- 00001520
-		X"24840008", -- 00001524
-		X"000210C0", -- 00001528
-		X"01023821", -- 0000152C
-		X"00E02021", -- 00001530
-		X"2CC20004", -- 00001534
-		X"14400005", -- 00001538
-		X"00804021", -- 0000153C
-		X"ACE30000", -- 00001540
-		X"24E40004", -- 00001544
-		X"24C6FFFC", -- 00001548
-		X"00804021", -- 0000154C
-		X"10C00007", -- 00001550
-		X"00000000", -- 00001554
-		X"00051600", -- 00001558
-		X"00021603", -- 0000155C
-		X"24C6FFFF", -- 00001560
-		X"A1020000", -- 00001564
-		X"14C0FFFD", -- 00001568
-		X"25080001", -- 0000156C
-		X"03E00008", -- 00001570
-		X"01201021", -- 00001574
-		X"0BF0054D", -- 00001578
-		X"01002021", -- 0000157C
-		X"00510051", -- 00001580
-		X"00520052", -- 00001584
-		X"00590059", -- 00001588
-		X"74617453", -- 0000158C
-		X"20207375", -- 00001590
-		X"0000203A", -- 00001594
-		X"20555043", -- 00001598
-		X"65707974", -- 0000159C
-		X"0000203A", -- 000015A0
-		X"76655220", -- 000015A4
-		X"0000002E", -- 000015A8
-		X"6E6B6E55", -- 000015AC
-		X"006E776F", -- 000015B0
-		X"746F6F42", -- 000015B4
-		X"20676E69", -- 000015B8
-		X"6D6F7266", -- 000015BC
-		X"616C6620", -- 000015C0
-		X"2E2E6873", -- 000015C4
-		X"0000002E", -- 000015C8
-		X"656E6F64", -- 000015CC
-		X"00000A0A", -- 000015D0
-		X"746F6F42", -- 000015D4
-		X"20676E69", -- 000015D8
-		X"6D6F7266", -- 000015DC
-		X"52415520", -- 000015E0
-		X"002E2E54", -- 000015E4
-		X"73616C46", -- 000015E8
-		X"72652068", -- 000015EC
-		X"2E657361", -- 000015F0
-		X"00002E2E", -- 000015F4
-		X"6C696166", -- 000015F8
-		X"0A216465", -- 000015FC
-		X"00000000", -- 00001600
-		X"656E6F64", -- 00001604
-		X"0000000A", -- 00001608
-		X"73616C46", -- 0000160C
-		X"72772068", -- 00001610
-		X"2E657469", -- 00001614
-		X"00002E2E", -- 00001618
-		X"73616C46", -- 0000161C
-		X"65762068", -- 00001620
-		X"79666972", -- 00001624
-		X"002E2E2E", -- 00001628
-		X"73736170", -- 0000162C
-		X"000A6465", -- 00001630
-		X"61766E69", -- 00001634
-		X"0064696C", -- 00001638
-		X"30303252", -- 0000163C
-		X"00000030", -- 00001640
-		X"30303352", -- 00001644
-		X"00000030", -- 00001648
-		X"30303652", -- 0000164C
-		X"00000030", -- 00001650
-		X"30303452", -- 00001654
-		X"00000030", -- 00001658
-		X"65736572", -- 0000165C
-		X"64657672", -- 00001660
-		X"00000000", -- 00001664
-		X"30303652", -- 00001668
-		X"00004130", -- 0000166C
-		X"BFC01634", -- 00001670
-		X"BFC0163C", -- 00001674
-		X"BFC01644", -- 00001678
-		X"BFC0164C", -- 0000167C
-		X"BFC01654", -- 00001680
-		X"BFC0165C", -- 00001684
-		X"BFC01668", -- 00001688
-		X"00000000", -- 0000168C
-		X"00000000", -- 00001690
-		X"00000000", -- 00001694
-		X"00000000", -- 00001698
-		X"00000000", -- 0000169C
-		X"00000000", -- 000016A0
-		X"00000000", -- 000016A4
-		X"00000000", -- 000016A8
-		X"00000000", -- 000016AC
-		X"00000000", -- 000016B0
-		X"00000000", -- 000016B4
-		X"00000000", -- 000016B8
-		X"00000000", -- 000016BC
-		X"00000000", -- 000016C0
-		X"00000000", -- 000016C4
-		X"00000000", -- 000016C8
-		X"00000000", -- 000016CC
-		X"00000000", -- 000016D0
-		X"00000000", -- 000016D4
-		X"00000000", -- 000016D8
-		X"00000000", -- 000016DC
-		X"00000000", -- 000016E0
-		X"00000000", -- 000016E4
-		X"00000000", -- 000016E8
-		X"00000000", -- 000016EC
-		X"00000000", -- 000016F0
-		X"00000000", -- 000016F4
-		X"00000000", -- 000016F8
-		X"00000000", -- 000016FC
-		X"00000000", -- 00001700
-		X"00000000", -- 00001704
-		X"00000000", -- 00001708
-		X"00000000", -- 0000170C
-		X"00000000", -- 00001710
-		X"00000000", -- 00001714
-		X"00000000", -- 00001718
-		X"00000000", -- 0000171C
-		X"00000000", -- 00001720
-		X"00000000", -- 00001724
-		X"00000000", -- 00001728
-		X"00000000", -- 0000172C
-		X"00000000", -- 00001730
-		X"00000000", -- 00001734
-		X"00000000", -- 00001738
-		X"00000000", -- 0000173C
-		X"00000000", -- 00001740
-		X"00000000", -- 00001744
-		X"00000000", -- 00001748
-		X"00000000", -- 0000174C
-		X"00000000", -- 00001750
-		X"00000000", -- 00001754
-		X"00000000", -- 00001758
-		X"00000000", -- 0000175C
-		X"00000000", -- 00001760
-		X"00000000", -- 00001764
-		X"00000000", -- 00001768
-		X"00000000", -- 0000176C
-		X"00000000", -- 00001770
-		X"00000000", -- 00001774
-		X"00000000", -- 00001778
-		X"00000000", -- 0000177C
-		X"00000000", -- 00001780
-		X"00000000", -- 00001784
-		X"00000000", -- 00001788
-		X"00000000", -- 0000178C
-		X"00000000", -- 00001790
-		X"00000000", -- 00001794
-		X"00000000", -- 00001798
-		X"00000000", -- 0000179C
-		X"00000000", -- 000017A0
-		X"00000000", -- 000017A4
-		X"00000000", -- 000017A8
-		X"00000000", -- 000017AC
-		X"00000000", -- 000017B0
-		X"00000000", -- 000017B4
-		X"00000000", -- 000017B8
-		X"00000000", -- 000017BC
-		X"00000000", -- 000017C0
-		X"00000000", -- 000017C4
-		X"00000000", -- 000017C8
-		X"00000000", -- 000017CC
-		X"00000000", -- 000017D0
-		X"00000000", -- 000017D4
-		X"00000000", -- 000017D8
-		X"00000000", -- 000017DC
-		X"00000000", -- 000017E0
-		X"00000000", -- 000017E4
-		X"00000000", -- 000017E8
-		X"00000000", -- 000017EC
-		X"00000000", -- 000017F0
-		X"00000000", -- 000017F4
-		X"00000000", -- 000017F8
-		X"00000000", -- 000017FC
-		X"00000000", -- 00001800
-		X"00000000", -- 00001804
-		X"00000000", -- 00001808
-		X"00000000", -- 0000180C
-		X"00000000", -- 00001810
-		X"00000000", -- 00001814
-		X"00000000", -- 00001818
-		X"00000000", -- 0000181C
-		X"00000000", -- 00001820
-		X"00000000", -- 00001824
-		X"00000000", -- 00001828
-		X"00000000", -- 0000182C
-		X"00000000", -- 00001830
-		X"00000000", -- 00001834
-		X"00000000", -- 00001838
-		X"00000000", -- 0000183C
-		X"00000000", -- 00001840
-		X"00000000", -- 00001844
-		X"00000000", -- 00001848
-		X"00000000", -- 0000184C
-		X"00000000", -- 00001850
-		X"00000000", -- 00001854
-		X"00000000", -- 00001858
-		X"00000000", -- 0000185C
-		X"00000000", -- 00001860
-		X"00000000", -- 00001864
-		X"00000000", -- 00001868
-		X"00000000", -- 0000186C
-		X"00000000", -- 00001870
-		X"00000000", -- 00001874
-		X"00000000", -- 00001878
-		X"00000000", -- 0000187C
-		X"00000000", -- 00001880
-		X"00000000", -- 00001884
-		X"00000000", -- 00001888
-		X"00000000", -- 0000188C
-		X"00000000", -- 00001890
-		X"00000000", -- 00001894
-		X"00000000", -- 00001898
-		X"00000000", -- 0000189C
-		X"00000000", -- 000018A0
-		X"00000000", -- 000018A4
-		X"00000000", -- 000018A8
-		X"00000000", -- 000018AC
-		X"00000000", -- 000018B0
-		X"00000000", -- 000018B4
-		X"00000000", -- 000018B8
-		X"00000000", -- 000018BC
-		X"00000000", -- 000018C0
-		X"00000000", -- 000018C4
-		X"00000000", -- 000018C8
-		X"00000000", -- 000018CC
-		X"00000000", -- 000018D0
-		X"00000000", -- 000018D4
-		X"00000000", -- 000018D8
-		X"00000000", -- 000018DC
-		X"00000000", -- 000018E0
-		X"00000000", -- 000018E4
-		X"00000000", -- 000018E8
-		X"00000000", -- 000018EC
-		X"00000000", -- 000018F0
-		X"00000000", -- 000018F4
-		X"00000000", -- 000018F8
-		X"00000000", -- 000018FC
-		X"00000000", -- 00001900
-		X"00000000", -- 00001904
-		X"00000000", -- 00001908
-		X"00000000", -- 0000190C
-		X"00000000", -- 00001910
-		X"00000000", -- 00001914
-		X"00000000", -- 00001918
-		X"00000000", -- 0000191C
-		X"00000000", -- 00001920
-		X"00000000", -- 00001924
-		X"00000000", -- 00001928
-		X"00000000", -- 0000192C
-		X"00000000", -- 00001930
-		X"00000000", -- 00001934
-		X"00000000", -- 00001938
-		X"00000000", -- 0000193C
-		X"00000000", -- 00001940
-		X"00000000", -- 00001944
-		X"00000000", -- 00001948
-		X"00000000", -- 0000194C
-		X"00000000", -- 00001950
-		X"00000000", -- 00001954
-		X"00000000", -- 00001958
-		X"00000000", -- 0000195C
-		X"00000000", -- 00001960
-		X"00000000", -- 00001964
-		X"00000000", -- 00001968
-		X"00000000", -- 0000196C
-		X"00000000", -- 00001970
-		X"00000000", -- 00001974
-		X"00000000", -- 00001978
-		X"00000000", -- 0000197C
-		X"00000000", -- 00001980
-		X"00000000", -- 00001984
-		X"00000000", -- 00001988
-		X"00000000", -- 0000198C
-		X"00000000", -- 00001990
-		X"00000000", -- 00001994
-		X"00000000", -- 00001998
-		X"00000000", -- 0000199C
-		X"00000000", -- 000019A0
-		X"00000000", -- 000019A4
-		X"00000000", -- 000019A8
-		X"00000000", -- 000019AC
-		X"00000000", -- 000019B0
-		X"00000000", -- 000019B4
-		X"00000000", -- 000019B8
-		X"00000000", -- 000019BC
-		X"00000000", -- 000019C0
-		X"00000000", -- 000019C4
-		X"00000000", -- 000019C8
-		X"00000000", -- 000019CC
-		X"00000000", -- 000019D0
-		X"00000000", -- 000019D4
-		X"00000000", -- 000019D8
-		X"00000000", -- 000019DC
-		X"00000000", -- 000019E0
-		X"00000000", -- 000019E4
-		X"00000000", -- 000019E8
-		X"00000000", -- 000019EC
-		X"00000000", -- 000019F0
-		X"00000000", -- 000019F4
-		X"00000000", -- 000019F8
-		X"00000000", -- 000019FC
-		X"00000000", -- 00001A00
-		X"00000000", -- 00001A04
-		X"00000000", -- 00001A08
-		X"00000000", -- 00001A0C
-		X"00000000", -- 00001A10
-		X"00000000", -- 00001A14
-		X"00000000", -- 00001A18
-		X"00000000", -- 00001A1C
-		X"00000000", -- 00001A20
-		X"00000000", -- 00001A24
-		X"00000000", -- 00001A28
-		X"00000000", -- 00001A2C
-		X"00000000", -- 00001A30
-		X"00000000", -- 00001A34
-		X"00000000", -- 00001A38
-		X"00000000", -- 00001A3C
-		X"00000000", -- 00001A40
-		X"00000000", -- 00001A44
-		X"00000000", -- 00001A48
-		X"00000000", -- 00001A4C
-		X"00000000", -- 00001A50
-		X"00000000", -- 00001A54
-		X"00000000", -- 00001A58
-		X"00000000", -- 00001A5C
-		X"00000000", -- 00001A60
-		X"00000000", -- 00001A64
-		X"00000000", -- 00001A68
-		X"00000000", -- 00001A6C
-		X"00000000", -- 00001A70
-		X"00000000", -- 00001A74
-		X"00000000", -- 00001A78
-		X"00000000", -- 00001A7C
-		X"00000000", -- 00001A80
-		X"00000000", -- 00001A84
-		X"00000000", -- 00001A88
-		X"00000000", -- 00001A8C
-		X"00000000", -- 00001A90
-		X"00000000", -- 00001A94
-		X"00000000", -- 00001A98
-		X"00000000", -- 00001A9C
-		X"00000000", -- 00001AA0
-		X"00000000", -- 00001AA4
-		X"00000000", -- 00001AA8
-		X"00000000", -- 00001AAC
-		X"00000000", -- 00001AB0
-		X"00000000", -- 00001AB4
-		X"00000000", -- 00001AB8
-		X"00000000", -- 00001ABC
-		X"00000000", -- 00001AC0
-		X"00000000", -- 00001AC4
-		X"00000000", -- 00001AC8
-		X"00000000", -- 00001ACC
-		X"00000000", -- 00001AD0
-		X"00000000", -- 00001AD4
-		X"00000000", -- 00001AD8
-		X"00000000", -- 00001ADC
-		X"00000000", -- 00001AE0
-		X"00000000", -- 00001AE4
-		X"00000000", -- 00001AE8
-		X"00000000", -- 00001AEC
-		X"00000000", -- 00001AF0
-		X"00000000", -- 00001AF4
-		X"00000000", -- 00001AF8
-		X"00000000", -- 00001AFC
-		X"00000000", -- 00001B00
-		X"00000000", -- 00001B04
-		X"00000000", -- 00001B08
-		X"00000000", -- 00001B0C
-		X"00000000", -- 00001B10
-		X"00000000", -- 00001B14
-		X"00000000", -- 00001B18
-		X"00000000", -- 00001B1C
-		X"00000000", -- 00001B20
-		X"00000000", -- 00001B24
-		X"00000000", -- 00001B28
-		X"00000000", -- 00001B2C
-		X"00000000", -- 00001B30
-		X"00000000", -- 00001B34
-		X"00000000", -- 00001B38
-		X"00000000", -- 00001B3C
-		X"00000000", -- 00001B40
-		X"00000000", -- 00001B44
-		X"00000000", -- 00001B48
-		X"00000000", -- 00001B4C
-		X"00000000", -- 00001B50
-		X"00000000", -- 00001B54
-		X"00000000", -- 00001B58
-		X"00000000", -- 00001B5C
-		X"00000000", -- 00001B60
-		X"00000000", -- 00001B64
-		X"00000000", -- 00001B68
-		X"00000000", -- 00001B6C
-		X"00000000", -- 00001B70
-		X"00000000", -- 00001B74
-		X"00000000", -- 00001B78
-		X"00000000", -- 00001B7C
-		X"00000000", -- 00001B80
-		X"00000000", -- 00001B84
-		X"00000000", -- 00001B88
-		X"00000000", -- 00001B8C
-		X"00000000", -- 00001B90
-		X"00000000", -- 00001B94
-		X"00000000", -- 00001B98
-		X"00000000", -- 00001B9C
-		X"00000000", -- 00001BA0
-		X"00000000", -- 00001BA4
-		X"00000000", -- 00001BA8
-		X"00000000", -- 00001BAC
-		X"00000000", -- 00001BB0
-		X"00000000", -- 00001BB4
-		X"00000000", -- 00001BB8
-		X"00000000", -- 00001BBC
-		X"00000000", -- 00001BC0
-		X"00000000", -- 00001BC4
-		X"00000000", -- 00001BC8
-		X"00000000", -- 00001BCC
-		X"00000000", -- 00001BD0
-		X"00000000", -- 00001BD4
-		X"00000000", -- 00001BD8
-		X"00000000", -- 00001BDC
-		X"00000000", -- 00001BE0
-		X"00000000", -- 00001BE4
-		X"00000000", -- 00001BE8
-		X"00000000", -- 00001BEC
-		X"00000000", -- 00001BF0
-		X"00000000", -- 00001BF4
-		X"00000000", -- 00001BF8
-		X"00000000", -- 00001BFC
-		X"00000000", -- 00001C00
-		X"00000000", -- 00001C04
-		X"00000000", -- 00001C08
-		X"00000000", -- 00001C0C
-		X"00000000", -- 00001C10
-		X"00000000", -- 00001C14
-		X"00000000", -- 00001C18
-		X"00000000", -- 00001C1C
-		X"00000000", -- 00001C20
-		X"00000000", -- 00001C24
-		X"00000000", -- 00001C28
-		X"00000000", -- 00001C2C
-		X"00000000", -- 00001C30
-		X"00000000", -- 00001C34
-		X"00000000", -- 00001C38
-		X"00000000", -- 00001C3C
-		X"00000000", -- 00001C40
-		X"00000000", -- 00001C44
-		X"00000000", -- 00001C48
-		X"00000000", -- 00001C4C
-		X"00000000", -- 00001C50
-		X"00000000", -- 00001C54
-		X"00000000", -- 00001C58
-		X"00000000", -- 00001C5C
-		X"00000000", -- 00001C60
-		X"00000000", -- 00001C64
-		X"00000000", -- 00001C68
-		X"00000000", -- 00001C6C
-		X"00000000", -- 00001C70
-		X"00000000", -- 00001C74
-		X"00000000", -- 00001C78
-		X"00000000", -- 00001C7C
-		X"00000000", -- 00001C80
-		X"00000000", -- 00001C84
-		X"00000000", -- 00001C88
-		X"00000000", -- 00001C8C
-		X"00000000", -- 00001C90
-		X"00000000", -- 00001C94
-		X"00000000", -- 00001C98
-		X"00000000", -- 00001C9C
-		X"00000000", -- 00001CA0
-		X"00000000", -- 00001CA4
-		X"00000000", -- 00001CA8
-		X"00000000", -- 00001CAC
-		X"00000000", -- 00001CB0
-		X"00000000", -- 00001CB4
-		X"00000000", -- 00001CB8
-		X"00000000", -- 00001CBC
-		X"00000000", -- 00001CC0
-		X"00000000", -- 00001CC4
-		X"00000000", -- 00001CC8
-		X"00000000", -- 00001CCC
-		X"00000000", -- 00001CD0
-		X"00000000", -- 00001CD4
-		X"00000000", -- 00001CD8
-		X"00000000", -- 00001CDC
-		X"00000000", -- 00001CE0
-		X"00000000", -- 00001CE4
-		X"00000000", -- 00001CE8
-		X"00000000", -- 00001CEC
-		X"00000000", -- 00001CF0
-		X"00000000", -- 00001CF4
-		X"00000000", -- 00001CF8
-		X"00000000", -- 00001CFC
-		X"00000000", -- 00001D00
-		X"00000000", -- 00001D04
-		X"00000000", -- 00001D08
-		X"00000000", -- 00001D0C
-		X"00000000", -- 00001D10
-		X"00000000", -- 00001D14
-		X"00000000", -- 00001D18
-		X"00000000", -- 00001D1C
-		X"00000000", -- 00001D20
-		X"00000000", -- 00001D24
-		X"00000000", -- 00001D28
-		X"00000000", -- 00001D2C
-		X"00000000", -- 00001D30
-		X"00000000", -- 00001D34
-		X"00000000", -- 00001D38
-		X"00000000", -- 00001D3C
-		X"00000000", -- 00001D40
-		X"00000000", -- 00001D44
-		X"00000000", -- 00001D48
-		X"00000000", -- 00001D4C
-		X"00000000", -- 00001D50
-		X"00000000", -- 00001D54
-		X"00000000", -- 00001D58
-		X"00000000", -- 00001D5C
-		X"00000000", -- 00001D60
-		X"00000000", -- 00001D64
-		X"00000000", -- 00001D68
-		X"00000000", -- 00001D6C
-		X"00000000", -- 00001D70
-		X"00000000", -- 00001D74
-		X"00000000", -- 00001D78
-		X"00000000", -- 00001D7C
-		X"00000000", -- 00001D80
-		X"00000000", -- 00001D84
-		X"00000000", -- 00001D88
-		X"00000000", -- 00001D8C
-		X"00000000", -- 00001D90
-		X"00000000", -- 00001D94
-		X"00000000", -- 00001D98
-		X"00000000", -- 00001D9C
-		X"00000000", -- 00001DA0
-		X"00000000", -- 00001DA4
-		X"00000000", -- 00001DA8
-		X"00000000", -- 00001DAC
-		X"00000000", -- 00001DB0
-		X"00000000", -- 00001DB4
-		X"00000000", -- 00001DB8
-		X"00000000", -- 00001DBC
-		X"00000000", -- 00001DC0
-		X"00000000", -- 00001DC4
-		X"00000000", -- 00001DC8
-		X"00000000", -- 00001DCC
-		X"00000000", -- 00001DD0
-		X"00000000", -- 00001DD4
-		X"00000000", -- 00001DD8
-		X"00000000", -- 00001DDC
-		X"00000000", -- 00001DE0
-		X"00000000", -- 00001DE4
-		X"00000000", -- 00001DE8
-		X"00000000", -- 00001DEC
-		X"00000000", -- 00001DF0
-		X"00000000", -- 00001DF4
-		X"00000000", -- 00001DF8
-		X"00000000", -- 00001DFC
-		X"00000000", -- 00001E00
-		X"00000000", -- 00001E04
-		X"00000000", -- 00001E08
-		X"00000000", -- 00001E0C
-		X"00000000", -- 00001E10
-		X"00000000", -- 00001E14
-		X"00000000", -- 00001E18
-		X"00000000", -- 00001E1C
-		X"00000000", -- 00001E20
-		X"00000000", -- 00001E24
-		X"00000000", -- 00001E28
-		X"00000000", -- 00001E2C
-		X"00000000", -- 00001E30
-		X"00000000", -- 00001E34
-		X"00000000", -- 00001E38
-		X"00000000", -- 00001E3C
-		X"00000000", -- 00001E40
-		X"00000000", -- 00001E44
-		X"00000000", -- 00001E48
-		X"00000000", -- 00001E4C
-		X"00000000", -- 00001E50
-		X"00000000", -- 00001E54
-		X"00000000", -- 00001E58
-		X"00000000", -- 00001E5C
-		X"00000000", -- 00001E60
-		X"00000000", -- 00001E64
-		X"00000000", -- 00001E68
-		X"00000000", -- 00001E6C
-		X"00000000", -- 00001E70
-		X"00000000", -- 00001E74
-		X"00000000", -- 00001E78
-		X"00000000", -- 00001E7C
-		X"00000000", -- 00001E80
-		X"00000000", -- 00001E84
-		X"00000000", -- 00001E88
-		X"00000000", -- 00001E8C
-		X"00000000", -- 00001E90
-		X"00000000", -- 00001E94
-		X"00000000", -- 00001E98
-		X"00000000", -- 00001E9C
-		X"00000000", -- 00001EA0
-		X"00000000", -- 00001EA4
-		X"00000000", -- 00001EA8
-		X"00000000", -- 00001EAC
-		X"00000000", -- 00001EB0
-		X"00000000", -- 00001EB4
-		X"00000000", -- 00001EB8
-		X"00000000", -- 00001EBC
-		X"00000000", -- 00001EC0
-		X"00000000", -- 00001EC4
-		X"00000000", -- 00001EC8
-		X"00000000", -- 00001ECC
-		X"00000000", -- 00001ED0
-		X"00000000", -- 00001ED4
-		X"00000000", -- 00001ED8
-		X"00000000", -- 00001EDC
-		X"00000000", -- 00001EE0
-		X"00000000", -- 00001EE4
-		X"00000000", -- 00001EE8
-		X"00000000", -- 00001EEC
-		X"00000000", -- 00001EF0
-		X"00000000", -- 00001EF4
-		X"00000000", -- 00001EF8
-		X"00000000", -- 00001EFC
-		X"00000000", -- 00001F00
-		X"00000000", -- 00001F04
-		X"00000000", -- 00001F08
-		X"00000000", -- 00001F0C
-		X"00000000", -- 00001F10
-		X"00000000", -- 00001F14
-		X"00000000", -- 00001F18
-		X"00000000", -- 00001F1C
-		X"00000000", -- 00001F20
-		X"00000000", -- 00001F24
-		X"00000000", -- 00001F28
-		X"00000000", -- 00001F2C
-		X"00000000", -- 00001F30
-		X"00000000", -- 00001F34
-		X"00000000", -- 00001F38
-		X"00000000", -- 00001F3C
-		X"00000000", -- 00001F40
-		X"00000000", -- 00001F44
-		X"00000000", -- 00001F48
-		X"00000000", -- 00001F4C
-		X"00000000", -- 00001F50
-		X"00000000", -- 00001F54
-		X"00000000", -- 00001F58
-		X"00000000", -- 00001F5C
-		X"00000000", -- 00001F60
-		X"00000000", -- 00001F64
-		X"00000000", -- 00001F68
-		X"00000000", -- 00001F6C
-		X"00000000", -- 00001F70
-		X"00000000", -- 00001F74
-		X"00000000", -- 00001F78
-		X"00000000", -- 00001F7C
-		X"00000000", -- 00001F80
-		X"00000000", -- 00001F84
-		X"00000000", -- 00001F88
-		X"00000000", -- 00001F8C
-		X"00000000", -- 00001F90
-		X"00000000", -- 00001F94
-		X"00000000", -- 00001F98
-		X"00000000", -- 00001F9C
-		X"00000000", -- 00001FA0
-		X"00000000", -- 00001FA4
-		X"00000000", -- 00001FA8
-		X"00000000", -- 00001FAC
-		X"00000000", -- 00001FB0
-		X"00000000", -- 00001FB4
-		X"00000000", -- 00001FB8
-		X"00000000", -- 00001FBC
-		X"00000000", -- 00001FC0
-		X"00000000", -- 00001FC4
-		X"00000000", -- 00001FC8
-		X"00000000", -- 00001FCC
-		X"00000000", -- 00001FD0
-		X"00000000", -- 00001FD4
-		X"00000000", -- 00001FD8
-		X"00000000", -- 00001FDC
-		X"00000000", -- 00001FE0
-		X"00000000", -- 00001FE4
-		X"00000000", -- 00001FE8
-		X"00000000", -- 00001FEC
-		X"00000000", -- 00001FF0
-		X"00000000", -- 00001FF4
-		X"00000000", -- 00001FF8
-		X"00000000"  -- 00001FFC
-	);
-
-begin
-
-PROM_READ:
-	process(clk)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= word_array(to_integer(addr(12 downto 2)));
-		end if;
-	end process;
-
-
---------------------------------------------------------------------------
--- Virtex-4: JTAG Loader
---------------------------------------------------------------------------
-	i00_BUFG : BUFG
-	port map
-	(
-		O => bs_clk1,
-        I => bs_clk0
-	);
-	
-	i01_BUFG : BUFG
-	port map
-	(
-		O => bs_update1,
-        I => bs_update0
-	);
-
-	BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 
-	generic map
-	(
-		JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
-	)
-	port map 
-	(
-		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
-		DRCK => bs_clk0,       -- Data register output for USER functions
-		RESET => bs_rst,       -- Reset output from TAP controller
-		SEL => bs_sel,         -- USER active output
-		SHIFT => bs_shift,     -- SHIFT output from TAP controller
-		TDI => bs_tdi,        -- TDI output from TAP controller
-		UPDATE => bs_update0,   -- UPDATE output from TAP controller
-		TDO => bs_tdo         -- Data input for USER function
-	);
-
-	jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);
-	jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);
-	jtag_ld_clk <= bs_update1;
-	jtag_ld_we <= bs_sel;
-	
-sipo:
-	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
-	begin
-		if bs_rst = '1' then
-			user_regi <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
-			end if;
-		end if;
-	end process;	
-
-piso:
-	process (bs_rst, bs_clk1, bs_shift, user_rego)
-	begin
-		bs_tdo <= user_rego(0);
-		if bs_rst = '1' then
-			user_rego <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
-			else
-				user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;	
-	
-			end if;
-		end if;
-	end process;
-
-PROM_WRITE:
-	process(jtag_ld_clk, jtag_ld_we)
-	begin
-		if rising_edge(jtag_ld_clk) then
-			if jtag_ld_we = '1' then
-				word_array(to_integer(jtag_ld_addr(10 downto 0))) <= jtag_ld_din;
-			else
-				jtag_ld_dout <= word_array(to_integer(jtag_ld_addr(10 downto 0)));
-			end if;
-		end if;
-	end process;
-
-end data;
diff --git a/projects/mips_sys/src/mips_sys.vhd b/projects/mips_sys/src/mips_sys.vhd
deleted file mode 100644
index 76893e1..0000000
--- a/projects/mips_sys/src/mips_sys.vhd
+++ /dev/null
@@ -1,870 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: system test using Xilinx ML-402
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-Library UNISIM;
-use UNISIM.vcomponents.all;
-
-library work;
-use work.mips_types.all;
-use work.sdram_config.all;
-use work.sdram_types.all;
-use work.vga_types.all;
-use work.async_types.all;
-use work.async_defs.all;
-
-
-ENTITY mips_sys IS
-GENERIC
-(
-	sys_freq			: integer		    := 100E6;
-	ddr_phaseshift		: integer			:= 0;
-	ddr_frequency_hz	: integer			:= 100E6
-);
-PORT
-(
-	sys_rst_n_in		: in std_logic;
-	sys_clk_in			: in std_logic;
-
-	-- Buttons and LEDs
-	sys_btn				: in unsigned(4 downto 0);
-	sys_dip				: in unsigned(7 downto 0);
-	sys_led				: out unsigned(8 downto 0);
-
-	-- UART
-	sys_rx				: in std_logic;
-	sys_tx				: out std_logic;
-
-	-- LCD
-	sys_lcd_d			: inout unsigned(3 downto 0);
-	sys_lcd_e			: out std_logic;
-	sys_lcd_rs			: out std_logic;
-	sys_lcd_rw			: out std_logic;
-
-	-- DDR SDRAM
-	sys_sdr_clk_p		: out std_logic;    -- ddr_sdram_clock
-	sys_sdr_clk_n		: out std_logic;    -- /ddr_sdram_clock
-	sys_sdr_cke_q		: out std_logic;    -- clock enable
-	sys_sdr_cs_qn		: out std_logic;    -- /chip select
-	sys_sdr_ras_qn		: out std_logic;    -- /ras
-	sys_sdr_cas_qn		: out std_logic;    -- /cas
-	sys_sdr_we_qn		: out std_logic;    -- /write enable
-	sys_sdr_dm_q		: out unsigned(DDR_DM_WIDTH-1 downto 0);     -- data mask bits, set to "00"
-	sys_sdr_dqs_q		: inout unsigned(DDR_DQS_WIDTH-1 downto 0);    -- data strobe, only for write
-	sys_sdr_ba_q		: out unsigned(DDR_BANK_WIDTH-1 downto 0);   -- bank select
-	sys_sdr_a_q			: out unsigned(DDR_ADDR_WIDTH-1 downto 0);   -- address bus 
-	sys_sdr_data		: inout unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus
-	sys_sdr_clk_fb		: in std_logic;
-	
-	-- VGA
-	sys_vga_clk			: out std_logic;
-	sys_vga_red			: out unsigned(7 downto 0);
-	sys_vga_green		: out unsigned(7 downto 0);
-	sys_vga_blue		: out unsigned(7 downto 0);
-	sys_vga_blank_n		: out std_logic;
-	sys_vga_sync_n		: out std_logic;
-	sys_vga_hsync		: out std_logic;
-	sys_vga_vsync		: out std_logic;
-
-	sys_usb_d			: inout unsigned(15 downto 0);
-	sys_usb_a			: out unsigned(1 downto 0);
-	sys_usb_csn			: out std_logic;
-	sys_usb_wrn			: out std_logic;
-	sys_usb_rdn			: out std_logic;
-	sys_usb_rstn		: out std_logic;
-	sys_usb_int			: in std_logic;
-
-	sys_flash_d			: inout unsigned(31 downto 0);
-	sys_flash_a			: out unsigned(24 downto 0);
-	sys_flash_ce		: out std_logic;
-	sys_flash_wrn		: out std_logic;
-	sys_flash_rdn		: out std_logic;
-	sys_flash_ac97_rstn	: out std_logic;
-	sys_flash_byten		: out std_logic;	
-
-	sys_ac97_sdata_in	: in  std_logic;
-	sys_ac97_bit_clk	: in  std_logic;
-	sys_ac97_sdata_out	: out std_logic;
-	sys_ac97_ssync		: out std_logic;
-
-	sys_error			: out unsigned(1 downto 0) -- indicates Errors
-	
-);
---	attribute BUFFER_TYPE : string;
---	attribute BUFFER_TYPE of sys_clk_in			: signal is "BUFG";
---	attribute BUFFER_TYPE of sys_sdr_dcm_clk_fb	: signal is "BUFG";
-
-END mips_sys;
-
-ARCHITECTURE behavior OF mips_sys IS 
-
-	COMPONENT mips_top
-	Port 
-	(
-		debug		: out unsigned(1 downto 0);
-		RST_I		: in  STD_LOGIC;
-		CLK_I		: in  STD_LOGIC;
-		ACK_I		: in  STD_LOGIC;
-		SRDY_I		: in  STD_LOGIC;
-		ADDR_O		: out word_t;
-		DAT_I		: in  word_t;
-		DAT_O		: out word_t;
-		WE_O		: out STD_LOGIC;
-		SEL_O		: out unsigned(3 downto 0);
-		CYC_O		: out STD_LOGIC;
-		STB_O		: out STD_LOGIC;
-		MRDY_O		: out STD_LOGIC;
-		INT			: in  unsigned (5 downto 0)
-		
-	);
-	END COMPONENT;
-	
-	COMPONENT rom_wb
-	PORT
-	(
-		CLK_I		: in  STD_LOGIC;
-		RST_I		: in  STD_LOGIC;
-		CYC_I		: in  STD_LOGIC;
-		STB_I		: in  STD_LOGIC;
-		ACK_O		: out STD_LOGIC;
-		MRDY_I		: in  STD_LOGIC;
-		SRDY_O		: out STD_LOGIC;
-		ADDR_I		: in  unsigned(31 downto 0);
-		DAT_O		: out unsigned(31 downto 0)
-	);
-	END COMPONENT;
-
-	COMPONENT lcd_port
-	PORT 
-	(
-		rst			: in std_logic;
-		clk			: in std_logic;
-		we			: in std_logic;
-		din			: in unsigned(7 downto 0);
-		dout		: out unsigned(7 downto 0);
-		lcd_d		: inout unsigned(3 downto 0);
-		lcd_e		: out std_logic;
-		lcd_rs		: out std_logic;
-		lcd_rw		: out std_logic
-	);
-	END COMPONENT;
-
-	COMPONENT async_port_wb
-	GENERIC
-	(
-		addr_width		: natural := 32;
-		data_width		: natural := 32;
-		byte_sel_width	: natural := 4;
-		async_timespec	: async_timespec_t
-	);
-	PORT
-	(
-		CLK_I		: in  STD_LOGIC;
-		RST_I		: in  STD_LOGIC;
-		CYC_I		: in  STD_LOGIC;
-		STB_I		: in  STD_LOGIC;
-		WE_I		: in  STD_LOGIC;
-		ACK_O		: out STD_LOGIC;
-		SRDY_O		: out STD_LOGIC;
-		MRDY_I		: in  STD_LOGIC;
-		SEL_I		: in  unsigned(3 downto 0);
-		ADDR_I		: in  unsigned(31 downto 0);
-		DAT_I		: in  unsigned(31 downto 0);
-		DAT_O		: out unsigned(31 downto 0);
-		async_a		: out unsigned(addr_width-1 downto 0);
-		async_d		: inout unsigned(data_width-1 downto 0);
-		async_cs	: out std_logic;
-		async_wr	: out std_logic;
-		async_rd	: out std_logic;
-		async_be	: out unsigned(byte_sel_width-1 downto 0);
-		async_rst	: out std_logic
-	);
-	END COMPONENT;
-
-	COMPONENT uart_wb
-	PORT
-	(
-		CLK_I		: in  STD_LOGIC;
-		RST_I		: in  STD_LOGIC;
-		CYC_I		: in  STD_LOGIC;
-		STB_I		: in  STD_LOGIC;
-		SEL_I		: in  unsigned(3 downto 0);
-		WE_I		: in  STD_LOGIC;
-		ACK_O		: out STD_LOGIC;
-		SRDY_O		: out STD_LOGIC;
-		MRDY_I		: in  STD_LOGIC;
-		ADDR_I		: in  unsigned(31 downto 0);
-		DAT_I		: in  unsigned(31 downto 0);
-		DAT_O		: out unsigned(31 downto 0);
-		INT_RX_O	: out STD_LOGIC;
-		INT_TX_O	: out STD_LOGIC;
-		ser_rx		: in std_logic;
-		ser_tx		: out std_logic
-	);
-	END COMPONENT;
-
-	COMPONENT gpio_wb
-	PORT
-	(
-		CLK_I		: in  STD_LOGIC;
-		RST_I		: in  STD_LOGIC;
-		CYC_I		: in  STD_LOGIC;
-		STB_I		: in  STD_LOGIC;
-		SEL_I		: in  unsigned(3 downto 0);
-		WE_I		: in  STD_LOGIC;
-		ACK_O		: out STD_LOGIC;
-		SRDY_O		: out STD_LOGIC;
-		MRDY_I		: in  STD_LOGIC;
-		ADDR_I		: in  unsigned(31 downto 0);
-		DAT_I		: in  unsigned(31 downto 0);
-		DAT_O		: out unsigned(31 downto 0);
-
-		sys_gpo0	: out unsigned(31 downto 0);
-		sys_gpo1	: out unsigned(31 downto 0);
-		sys_gpi0	: in  unsigned(31 downto 0);
-		sys_gpi1	: in  unsigned(31 downto 0)
-	);
-	END COMPONENT;
-
-	COMPONENT vga_frontend64
-	GENERIC
-	(
-		sys_freq					: integer;
-		fifo_depth					: integer;
-		fifo_almost_full_thresh		: natural;
-		fifo_almost_empty_thresh	: natural;
-		tsvga						: vga_timespec_t
-	);
-	PORT
-	(
-		-- System signals
-		RST_I			: in  STD_LOGIC;
-		CLK_I			: in  STD_LOGIC;
-
-		-- JBUS Master signals
-		CYC_O			: out STD_LOGIC;
-		STB_O			: out STD_LOGIC;
-		WE_O			: out STD_LOGIC;
-		SEL_O			: out unsigned(7 downto 0);
-		ACK_I			: in  STD_LOGIC;
-		SRDY_I			: in  STD_LOGIC;
-		MRDY_O			: out STD_LOGIC;
-		ADDR_O			: out unsigned(31 downto 0);
-		MDAT_I			: in  unsigned(63 downto 0);
-		MDAT_O			: out unsigned(63 downto 0);
-		
-		-- JBUS Slave signals
-		CYC_I			: in  STD_LOGIC;
-		STB_I			: in  STD_LOGIC;
-		WE_I			: in  STD_LOGIC;
-		SEL_I			: in  unsigned(3 downto 0);
-		ACK_O			: out STD_LOGIC;
-		SRDY_O			: out STD_LOGIC;
-		MRDY_I			: in  STD_LOGIC;
-		ADDR_I			: in  unsigned(31 downto 0);
-		SDAT_I			: in  unsigned(31 downto 0);
-		SDAT_O			: out unsigned(31 downto 0);
-		
-		-- VGA signals
-		vga_clk_out		: out std_logic;
-		vga_red			: out unsigned(7 downto 0);
-		vga_green		: out unsigned(7 downto 0);
-		vga_blue		: out unsigned(7 downto 0);
-		vga_blank_n		: out std_logic;
-		vga_sync_n		: out std_logic;
-		vga_hsync		: out std_logic;
-		vga_vsync		: out std_logic
-	);
-	END COMPONENT;
-
-	signal rst			: std_logic;
-	signal clk			: std_logic;
-	signal clk270		: std_logic;
-	signal clk270var	: std_logic;
-	signal rst_in		: std_logic;
-	signal int_uart_rx	: std_logic;
-	signal locked		: std_logic;
-	signal usb_addr 	: unsigned(31 downto 0);
-	signal flash_addr	: unsigned(31 downto 0);
-	signal ac97_rstn	: std_logic;
-	signal flash_rstn	: std_logic;
-
-	-- Arbiter
-	constant ARB_MAX_MASTER	: natural := 2;
-	signal	arb_idx		: natural range 0 to ARB_MAX_MASTER-1;
-	signal	arb_req		: unsigned (ARB_MAX_MASTER-1 downto 0);
-	signal	arb_gnt		: unsigned (ARB_MAX_MASTER-1 downto 0);
-	
-	-- J-Bus signals
-	signal INT	 		: unsigned(5 downto 0);
-	signal MDAT_I		: word_t;
-	signal MDAT_O 		: word_t;
-	signal ADDR_O 		: word_t;
-	signal SEL_O 		: unsigned(3 downto 0);
-	signal WE_O 		: std_logic;
-	signal CYC_O 		: std_logic;
-	signal STB_O 		: std_logic;
-	signal ACK_I		: std_logic;
-	signal SRDY_I		: std_logic;
-	signal MRDY_O		: std_logic;
-
-	-- CPU Master
-	signal MRDY_O_cpu	: std_logic;
-	signal MDAT_O_cpu	: word_t;
-	signal ADDR_O_cpu	: word_t;
-	signal SEL_O_cpu	: unsigned(3 downto 0);
-	signal WE_O_cpu		: std_logic;
-	signal CYC_O_cpu	: std_logic;
-	signal STB_O_cpu	: std_logic;
-	signal SRDY_I_cpu	: std_logic;
-	signal ACK_I_cpu	: std_logic;
-
-	-- VGA Master
-	signal MRDY_O_vga	: std_logic;
-	signal ADDR_O_vga	: word_t;
-	signal SEL_O_vga	: unsigned(7 downto 0);
-	signal WE_O_vga		: std_logic;
-	signal CYC_O_vga	: std_logic;
-	signal STB_O_vga	: std_logic;
-	signal SRDY_I_vga	: std_logic;
-	signal ACK_I_vga	: std_logic;
-	signal MDAT_I_vga	: unsigned(63 downto 0);
-	signal MDAT_O_vga	: unsigned(63 downto 0);
-
-	-- Slaves
-	signal CYC_I_flash	: std_logic;
-	signal ACK_O_flash	: std_logic;
-	signal SRDY_O_flash	: std_logic;
-	signal SDAT_O_flash	: unsigned(31 downto 0);
-
-	signal CYC_I_usb	: std_logic;
-	signal ACK_O_usb	: std_logic;
-	signal SRDY_O_usb	: std_logic;
-	signal SDAT_O_usb	: unsigned(31 downto 0);
-
-	signal CYC_I_sdram	: std_logic;
-	signal ACK_O_sdram	: std_logic;
-	signal SRDY_O_sdram	: std_logic;
-	signal SDAT_O_sdram	: unsigned(63 downto 0);
-	signal SDAT_I_sdram	: unsigned(63 downto 0);
-	signal SEL_I_sdram	: unsigned(7 downto 0);
-
-	signal CYC_I_rom	: std_logic;
-	signal ACK_O_rom	: std_logic;
-	signal SRDY_O_rom	: std_logic;
-	signal SDAT_O_rom	: unsigned(31 downto 0);
-
-	signal CYC_I_gpio	: std_logic;
-	signal ACK_O_gpio	: std_logic;
-	signal SRDY_O_gpio	: std_logic;
-	signal SDAT_O_gpio	: unsigned(31 downto 0);
-
-	signal CYC_I_uart	: std_logic;
-	signal ACK_O_uart	: std_logic;
-	signal SRDY_O_uart	: std_logic;
-	signal SDAT_O_uart	: unsigned(31 downto 0);
-
-	signal CYC_I_vga	: std_logic;
-	signal ACK_O_vga	: std_logic;
-	signal SRDY_O_vga	: std_logic;
-	signal SDAT_O_vga	: unsigned(31 downto 0);
-
-	signal INT_O_ac97	: std_logic;
-	signal CYC_I_ac97	: std_logic;
-	signal ACK_O_ac97	: std_logic;
-	signal SRDY_O_ac97	: std_logic;
-	signal SDAT_O_ac97	: unsigned(31 downto 0);
-
-	signal gpo0			: unsigned(31 downto 0);
-	signal gpo1			: unsigned(31 downto 0);
-	signal gpi0			: unsigned(31 downto 0);
-	signal gpi1			: unsigned(31 downto 0);
-
-	signal debug		: unsigned(1 downto 0);
-
-	-- DDR SDRAM
-	constant BURST_LEN		: natural := 2;
-
-	
---	attribute rom_style: string;
---	attribute rom_style of cmd_fifo_dout: signal is "DISTRIBUTED";
---	attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
---	attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";
-
-	type mem_area_t is (mem_dead, mem_flash, mem_usb, mem_rom, mem_gpio, mem_uart, mem_sdram, mem_vga, mem_ac97);
-	signal mem_area : mem_area_t;
-
-BEGIN
-
-	gpi0(4 downto 0)	<= sys_btn;
-	gpi1(7 downto 0)	<= sys_dip;
-	sys_led				<= gpo0(8 downto 0);
-	sys_error			<= debug;
-	rst_in 				<= not sys_rst_n_in;
-	rst					<= not locked;
-	sys_usb_rstn		<= not gpo1(0);
-	sys_flash_byten		<= '1';
-	usb_addr			<= X"0000000" & "00" & ADDR_O(3 downto 2);
-	flash_addr			<= "0000000" & ADDR_O(25 downto 2) & '0';
-
-	SDAT_I_sdram		<= MDAT_O & MDAT_O;
-	SEL_I_sdram			<= "0000" & SEL_O;
-	
-	sys_flash_ac97_rstn	<= ac97_rstn and flash_rstn;
-	
-	---------------------------------------------------------------
-	-- Arbiter
-	MRDY_O		<= MRDY_O_cpu when arb_gnt(0) = '1' else MRDY_O_vga when arb_gnt(1) = '1' else '0';
-	MDAT_O		<= MDAT_O_cpu when arb_gnt(0) = '1' else MDAT_O_vga(31 downto 0) when arb_gnt(1) = '1' else (others => '0');
-	ADDR_O		<= ADDR_O_cpu when arb_gnt(0) = '1' else ADDR_O_vga when arb_gnt(1) = '1' else (others => '0');
-	SEL_O		<= SEL_O_cpu when arb_gnt(0) = '1' else SEL_O_vga(3 downto 0) when arb_gnt(1) = '1' else (others => '0');
-	WE_O		<= WE_O_cpu when arb_gnt(0) = '1' else WE_O_vga when arb_gnt(1) = '1' else '0';
-	CYC_O		<= CYC_O_cpu when arb_gnt(0) = '1' else CYC_O_vga when arb_gnt(1) = '1' else '0';
-	STB_O		<= STB_O_cpu when arb_gnt(0) = '1' else STB_O_vga when arb_gnt(1) = '1' else '0';
-	SRDY_I_cpu	<= SRDY_I and arb_gnt(0);
-	SRDY_I_vga	<= SRDY_I and arb_gnt(1);
-	ACK_I_cpu	<= ACK_I and arb_gnt(0);
-	ACK_I_vga	<= ACK_I and arb_gnt(1);
-	
-	arb_req(0)	<= CYC_O_cpu;
-	arb_req(1)	<= CYC_O_vga;
-	
-	MDAT_I_vga	<= SDAT_O_sdram(63 downto 32) & MDAT_I;
-	
-arbiter_proc:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				arb_gnt	<= (others => '0');
-				arb_idx	<= 0;
-			elsif arb_req(arb_idx) = '0' then
-				if arb_idx /= ARB_MAX_MASTER-1 then
-					arb_idx	<= arb_idx + 1;
-				else
-					arb_idx	<= 0;
-				end if;
-			else	
-				arb_gnt	<= (others => '0');
-				arb_gnt(arb_idx)	<= '1';
-			end if;	
-		end if;
-	end process;
-	
-int_sample:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			int <= "00" & INT_O_ac97 & sys_usb_int & int_uart_rx & sys_btn(4);
-		end if;
-	end process;
-	
-mem_mux:
-	process(ADDR_O)
-	begin
-		mem_area	<= mem_dead;
---		if ADDR_O(31 downto 28) = X"0" then
---			mem_area	<= mem_flash;
-		if ADDR_O(31 downto 28) = X"A" then
-			if ADDR_O(27 downto 26) = "00" then
-				if ADDR_O(18 downto 16) = "000" then
-					mem_area	<= mem_gpio;
-				elsif ADDR_O(18 downto 16) = "001" then
-					mem_area	<= mem_uart;
-				elsif ADDR_O(18 downto 16) = "010" then
-					mem_area	<= mem_usb;
-				elsif ADDR_O(18 downto 16) = "011" then
-					mem_area	<= mem_vga;
-				elsif ADDR_O(18 downto 16) = "100" then
-					mem_area	<= mem_ac97;
-				end if;	
-			elsif ADDR_O(27 downto 26) = "01" then
-				mem_area	<= mem_flash;
-			end if;	
-		elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
-			mem_area	<= mem_rom;
---		elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
-		elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
-			mem_area	<= mem_sdram;
-		end if;
-	end process;	
-
-signal_mux:
-	process(mem_area, CYC_O)
-	begin
-	
-		CYC_I_uart		<= '0';
-		CYC_I_gpio		<= '0';
-		CYC_I_flash		<= '0';
-		CYC_I_usb		<= '0';
-		CYC_I_rom		<= '0';
-		CYC_I_sdram		<= '0';
-		CYC_I_vga		<= '0';
-		CYC_I_ac97		<= '0';
-		
-		case mem_area is
-
-		when mem_gpio =>
-			CYC_I_gpio		<= CYC_O;
-
-		when mem_uart =>
-			CYC_I_uart		<= CYC_O;
-
-		when mem_flash =>
-			CYC_I_flash		<= CYC_O;
-
-		when mem_usb =>
-			CYC_I_usb		<= CYC_O;
-
-		when mem_rom =>
-			CYC_I_rom		<= CYC_O;
-
-		when mem_sdram =>
-			CYC_I_sdram		<= CYC_O;
-		
-		when mem_vga =>
-			CYC_I_vga		<= CYC_O;
-
-		when mem_ac97 =>
-			CYC_I_ac97		<= CYC_O;
-
-		when others => null;
-		
-		end case;
-		
-	end process;
-
-------------------------------------------------------------------
- 	SRDY_I		<=	SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
- 	ACK_I		<=	ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
- 	MDAT_I		<=	SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else
-					SDAT_O_rom when CYC_I_rom = '1' else
-					SDAT_O_flash when CYC_I_flash = '1' else
-					SDAT_O_usb when CYC_I_usb = '1' else
-					SDAT_O_uart when CYC_I_uart = '1' else
-					SDAT_O_vga when CYC_I_vga = '1' else
-					SDAT_O_ac97 when CYC_I_ac97 = '1' else
-					SDAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
-
-------------------------------------------------------------------
-inst_mips_top: mips_top
-	PORT MAP
-	(
-		debug			=> debug,
-		RST_I			=> rst,
-		CLK_I			=> clk,
-		ACK_I			=> ACK_I_cpu,
-		SRDY_I			=> SRDY_I_cpu,
-		MRDY_O			=> MRDY_O_cpu,
-		CYC_O			=> CYC_O_cpu,
-		STB_O			=> STB_O_cpu,
-		WE_O			=> WE_O_cpu,
-		SEL_O			=> SEL_O_cpu,
-		DAT_I			=> MDAT_I,
-		DAT_O			=> MDAT_O_cpu,
-		ADDR_O			=> ADDR_O_cpu,
-		INT				=> INT
-	);
-
-inst_rom_wb : rom_wb
-	PORT MAP
-	(
-		CLK_I	=> clk,
-		RST_I	=> rst,
-		CYC_I	=> CYC_I_rom,
-		STB_I	=> STB_O,
-		ACK_O	=> ACK_O_rom,
-		MRDY_I	=> MRDY_O,
-		SRDY_O	=> SRDY_O_rom,
-		ADDR_I	=> ADDR_O,
-		DAT_O	=> SDAT_O_rom
-	);
-
-
-inst_lcd_port: lcd_port
-	PORT MAP
-	(
-		clk => clk,
-		rst => rst,
-		we => '0',
-		din => X"00",
-		dout => open,
-		lcd_d => sys_lcd_d,
-		lcd_e => sys_lcd_e,
-		lcd_rs => sys_lcd_rs,
-		lcd_rw => sys_lcd_rw
-	);
-	
-inst_gpio_wb : gpio_wb
-	PORT MAP
-	(
-		CLK_I		=> clk,
-		RST_I		=> rst,
-		CYC_I		=> CYC_I_gpio,
-		STB_I		=> STB_O,
-		SEL_I		=> SEL_O,
-		WE_I		=> WE_O,
-		ACK_O		=> ACK_O_gpio,
-		SRDY_O		=> SRDY_O_gpio,
-		MRDY_I		=> MRDY_O,
-		ADDR_I		=> ADDR_O,
-		DAT_I		=> MDAT_O,
-		DAT_O		=> SDAT_O_gpio,
-
-		sys_gpo0	=> gpo0,
-		sys_gpo1	=> gpo1,
-		sys_gpi0	=> gpi0,
-		sys_gpi1	=> gpi1
-	);
-
-inst_flash_port : async_port_wb
-	GENERIC MAP
-	(
-		addr_width		=> 25,
-		data_width		=> 32,
-		byte_sel_width	=> 1,
-		async_timespec	=> ts_flash
-	)
-	PORT MAP
-	(
-		CLK_I		=> clk,
-		RST_I		=> rst,
-		CYC_I		=> CYC_I_flash,
-		STB_I		=> STB_O,
-		WE_I		=> WE_O,
-		ACK_O		=> ACK_O_flash,
-		SRDY_O		=> SRDY_O_flash,
-		MRDY_I		=> MRDY_O,
-		SEL_I		=> SEL_O,
-		ADDR_I		=> flash_addr,
-		DAT_I		=> MDAT_O,
-		DAT_O		=> SDAT_O_flash,
-		async_a		=> sys_flash_a,
-		async_d		=> sys_flash_d,
-		async_cs	=> sys_flash_ce,
-		async_wr	=> sys_flash_wrn,
-		async_rd	=> sys_flash_rdn,
-		async_be	=> open,
-		async_rst	=> flash_rstn
-	);
-
-inst_usb_port : async_port_wb
-	GENERIC MAP
-	(
-		addr_width		=> 2,
-		data_width		=> 16,
-		byte_sel_width	=> 1,
-		async_timespec	=> ts_usb
-	)
-	PORT MAP
-	(
-		CLK_I		=> clk,
-		RST_I		=> rst,
-		CYC_I		=> CYC_I_usb,
-		STB_I		=> STB_O,
-		WE_I		=> WE_O,
-		ACK_O		=> ACK_O_usb,
-		SRDY_O		=> SRDY_O_usb,
-		MRDY_I		=> MRDY_O,
-		SEL_I		=> SEL_O,
-		ADDR_I		=> usb_addr,
-		DAT_I		=> MDAT_O,
-		DAT_O		=> SDAT_O_usb,
-		async_a		=> sys_usb_a,
-		async_d		=> sys_usb_d,
-		async_cs	=> sys_usb_csn,
-		async_wr	=> sys_usb_wrn,
-		async_rd	=> sys_usb_rdn,
-		async_be	=> open,
-		async_rst	=> open
-	);
-
-inst_uart_wb : uart_wb
-	PORT MAP
-	(
-		CLK_I		=> clk,
-		RST_I		=> rst,
-		CYC_I		=> CYC_I_uart,
-		STB_I		=> STB_O,
-		SEL_I		=> SEL_O,
-		WE_I		=> WE_O,
-		ACK_O		=> ACK_O_uart,
-		SRDY_O		=> SRDY_O_uart,
-		MRDY_I		=> MRDY_O,
-		ADDR_I		=> ADDR_O,
-		DAT_I		=> MDAT_O,
-		DAT_O		=> SDAT_O_uart,
-		INT_RX_O	=> int_uart_rx,
-		INT_TX_O	=> open,
-		ser_rx		=> sys_rx,
-		ser_tx		=> sys_tx
-	);
-
-
-inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
-	GENERIC MAP
-	(
-		BL			=> BURST_LEN,
-		f_sysclk	=> ddr_frequency_hz,
-		fifo_depth	=> 5
-	)
-	PORT MAP
-	(
-		RST_I			=> rst,
-		CLK_I			=> clk,
-		CLK270_I		=> clk270,
-		CLK270VAR_I		=> clk270var,
-		
-		CYC_I			=> CYC_I_sdram,
-		STB_I			=> STB_O,
-		SEL_I			=> SEL_I_sdram,
-		WE_I			=> WE_O,
-		ACK_O			=> ACK_O_sdram,
-		MRDY_I			=> MRDY_O,
-		SRDY_O			=> SRDY_O_sdram,
-		ADDR_I			=> ADDR_O,
-		DAT_I			=> SDAT_I_sdram,
-		DAT_O			=> SDAT_O_sdram,
-
-		-- SDRAM signals
-		sd_clk_p		=> sys_sdr_clk_p,
-		sd_clk_n		=> sys_sdr_clk_n,
-		sd_cke			=> sys_sdr_cke_q,
-		sd_cs_n			=> sys_sdr_cs_qn,
-		sd_cas_n		=> sys_sdr_cas_qn,
-		sd_ras_n		=> sys_sdr_ras_qn,
-		sd_we_n			=> sys_sdr_we_qn,
-		sd_addr			=> sys_sdr_a_q,
-		sd_ba			=> sys_sdr_ba_q,
-		sd_dm			=> sys_sdr_dm_q,
-		sd_dqs			=> sys_sdr_dqs_q,
-		sd_data			=> sys_sdr_data
-		
-	);
-
-inst_clockgen : entity work.clockgen
-	GENERIC MAP
-	(
-		sys1_phaseshift	=> 0,
-		frequency_hz	=> 100E6
-	)
-	PORT MAP 
-	(
-		-- Clocks and Reset
-		rst				=> rst_in,   -- external async reset, low active
-		clk_in			=> sys_clk_in,   -- system clock (e.g. 100MHz), from board
-		clk_fb_in		=> sys_sdr_clk_fb,   -- feedback clock
-		sys1_clk0_out	=> open,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
-		sys1_clk270_out	=> clk270var,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
-		sys0_clk0_out	=> clk,  -- System clock #0, dcm#0 output 0°
-		sys0_clk270_out	=> clk270,  -- System clock #0, dcm#0 output 270°
-		locked_out		=> locked,  -- DCM locked status
-		error_out		=> open
-	);
-
-inst_vga_frontend : vga_frontend64
-	GENERIC MAP
-	(
-		sys_freq					=> 100E6,
-		fifo_depth					=> 2048,
-		fifo_almost_full_thresh		=> 1860,
-		fifo_almost_empty_thresh	=> 256,
-		tsvga						=> ts_vga_800_600_72
-	)
-	PORT MAP
-	(
-		-- System signals
-		RST_I			=> rst,
-		CLK_I			=> clk,
-
-		-- JBUS Master signals
-		CYC_O			=> CYC_O_vga,
-		STB_O			=> STB_O_vga,
-		WE_O			=> WE_O_vga,
-		SEL_O			=> SEL_O_vga,
-		ACK_I			=> ACK_I_vga,
-		SRDY_I			=> SRDY_I_vga,
-		MRDY_O			=> MRDY_O_vga,
-		ADDR_O			=> ADDR_O_vga,
-		MDAT_I			=> MDAT_I_vga,
-		MDAT_O			=> MDAT_O_vga,
-
-		-- JBUS Slave signals
-		CYC_I			=> CYC_I_vga,
-		STB_I			=> STB_O,
-		WE_I			=> WE_O,
-		SEL_I			=> SEL_O,
-		ACK_O			=> ACK_O_vga,
-		SRDY_O			=> SRDY_O_vga,
-		MRDY_I			=> MRDY_O,
-		ADDR_I			=> ADDR_O,
-		SDAT_I			=> MDAT_O,
-		SDAT_O			=> SDAT_O_vga,
-		
-		-- VGA signals
-		vga_clk_out		=> sys_vga_clk,
-		vga_red			=> sys_vga_red,
-		vga_green		=> sys_vga_green,
-		vga_blue		=> sys_vga_blue,
-		vga_blank_n		=> sys_vga_blank_n,
-		vga_sync_n		=> sys_vga_sync_n,
-		vga_hsync		=> sys_vga_hsync,
-		vga_vsync		=> sys_vga_vsync	
-	);
-
-inst_ac97_wb : entity work.ac97_wb
-	GENERIC MAP
-	(
-		fifo_depth		=> 8
-	)
-	PORT MAP
-	(
-		-- J-Bus domain
-		CLK_I			=> clk,
-		RST_I			=> rst,
-		CYC_I			=> CYC_I_ac97,
-		STB_I			=> STB_O,
-		WE_I			=> WE_O,
-		ACK_O			=> ACK_O_ac97,
-		SRDY_O			=> SRDY_O_ac97,
-		MRDY_I			=> MRDY_O,
-		ADDR_I			=> ADDR_O,
-		DAT_I			=> MDAT_O,
-		DAT_O			=> SDAT_O_ac97,
-		INT_O			=> INT_O_ac97,
-
-		-- AC97 domain
-		ac97_sdata_in	=> sys_ac97_sdata_in,
-		ac97_bit_clk	=> sys_ac97_bit_clk,          
-		ac97_reset_n	=> ac97_rstn,
-		ac97_sdata_out	=> sys_ac97_sdata_out,
-		ac97_ssync		=> sys_ac97_ssync		
-	);
-
-	------------------------------------------------------------------
-END;
diff --git a/projects/mips_sys/src/mips_sys_sim.vhd b/projects/mips_sys/src/mips_sys_sim.vhd
deleted file mode 100644
index 160e06c..0000000
--- a/projects/mips_sys/src/mips_sys_sim.vhd
+++ /dev/null
@@ -1,1011 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: system test using Xilinx ML-402
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-Library UNISIM;
-use UNISIM.vcomponents.all;
-
-library work;
-use work.mips_types.all;
---use work.fifo_ctrl_pkg.all;
-use work.sdram_config.all;
-use work.sdram_types.all;
-use work.vga_types.all;
-use work.async_types.all;
-use work.async_defs.all;
-
-
-ENTITY mips_sys IS
-GENERIC
-(
-	sys_freq			: integer		    := 100E6;
-	ddr_phaseshift		: integer			:= 0;
-	ddr_frequency_hz	: integer			:= 100E6
-);
-PORT
-(
-	sys_rst_n_in		: in std_logic;
-	sys_clk_in			: in std_logic;
-
-	-- Buttons and LEDs
-	sys_btn				: in unsigned(4 downto 0);
-	sys_dip				: in unsigned(7 downto 0);
-	sys_led				: out unsigned(8 downto 0);
-
-	-- UART
-	sys_rx				: in std_logic;
-	sys_tx				: out std_logic;
-
-	-- LCD
-	sys_lcd_d			: inout unsigned(3 downto 0);
-	sys_lcd_e			: out std_logic;
-	sys_lcd_rs			: out std_logic;
-	sys_lcd_rw			: out std_logic;
-
-	-- DDR SDRAM
-	sys_sdr_clk_p		: out std_logic;    -- ddr_sdram_clock
-	sys_sdr_clk_n		: out std_logic;    -- /ddr_sdram_clock
-	sys_sdr_cke_q		: out std_logic;    -- clock enable
-	sys_sdr_cs_qn		: out std_logic;    -- /chip select
-	sys_sdr_ras_qn		: out std_logic;    -- /ras
-	sys_sdr_cas_qn		: out std_logic;    -- /cas
-	sys_sdr_we_qn		: out std_logic;    -- /write enable
-	sys_sdr_dm_q		: out unsigned(DDR_DM_WIDTH-1 downto 0);     -- data mask bits, set to "00"
-	sys_sdr_dqs_q		: inout unsigned(DDR_DQS_WIDTH-1 downto 0);    -- data strobe, only for write
-	sys_sdr_ba_q		: out unsigned(DDR_BANK_WIDTH-1 downto 0);   -- bank select
-	sys_sdr_a_q			: out unsigned(DDR_ADDR_WIDTH-1 downto 0);   -- address bus 
-	sys_sdr_data		: inout unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus
-	sys_sdr_clk_fb		: in std_logic;
-	
-	-- VGA
-	sys_vga_clk			: out std_logic;
-	sys_vga_red			: out unsigned(7 downto 0);
-	sys_vga_green		: out unsigned(7 downto 0);
-	sys_vga_blue		: out unsigned(7 downto 0);
-	sys_vga_blank_n		: out std_logic;
-	sys_vga_sync_n		: out std_logic;
-	sys_vga_hsync		: out std_logic;
-	sys_vga_vsync		: out std_logic;
-
-	sys_usb_d			: inout unsigned(15 downto 0);
-	sys_usb_a			: out unsigned(1 downto 0);
-	sys_usb_csn			: out std_logic;
-	sys_usb_wrn			: out std_logic;
-	sys_usb_rdn			: out std_logic;
-	sys_usb_rstn		: out std_logic;
-	sys_usb_int			: in std_logic;
-
-	sys_flash_ssram_d		: inout unsigned(31 downto 0);
-	sys_flash_ssram_a		: out unsigned(24 downto 0);
-	sys_flash_ce			: out std_logic;
-	sys_flash_ssram_we_n	: out std_logic;
-	sys_flash_ssram_oe_n	: out std_logic;
-	sys_flash_ac97_rstn		: out std_logic;
-	sys_flash_byten			: out std_logic;	
-	
-	sys_ssram_clk			: out std_logic;
-	sys_ssram_clk_fb		: in std_logic;
-	sys_ssram_cke_n			: out std_logic;
-	sys_ssram_ce_n			: out std_logic;
-	sys_ssram_bw_n			: out unsigned(3 downto 0);
-	sys_ssram_dp			: inout unsigned(3 downto 0);
-	sys_ssram_adv			: out std_logic;
-	sys_ssram_mode			: out std_logic;
-	sys_ssram_zz			: out std_logic;
-
-	sys_ac97_sdata_in		: in  std_logic;
-	sys_ac97_bit_clk		: in  std_logic;
-	sys_ac97_sdata_out		: out std_logic;
-	sys_ac97_ssync			: out std_logic;
-
-	sys_error				: out unsigned(1 downto 0) -- indicates Errors
-	
-);
---	attribute BUFFER_TYPE : string;
---	attribute BUFFER_TYPE of sys_clk_in			: signal is "BUFG";
---	attribute BUFFER_TYPE of sys_sdr_dcm_clk_fb	: signal is "BUFG";
-
-END mips_sys;
-
-ARCHITECTURE behavior OF mips_sys IS 
-
-	COMPONENT mips_top
-	Port 
-	(
-		debug		: out unsigned(1 downto 0);
-		RST_I		: in  STD_LOGIC;
-		CLK_I		: in  STD_LOGIC;
-		ACK_I		: in  STD_LOGIC;
-		SRDY_I		: in  STD_LOGIC;
-		ADDR_O		: out word_t;
-		DAT_I		: in  word_t;
-		DAT_O		: out word_t;
-		WE_O		: out STD_LOGIC;
-		SEL_O		: out unsigned(3 downto 0);
-		CYC_O		: out STD_LOGIC;
-		STB_O		: out STD_LOGIC;
-		MRDY_O		: out STD_LOGIC;
-		INT			: in  unsigned (5 downto 0)
-		
-	);
-	END COMPONENT;
-	
-	COMPONENT rom_wb
-	PORT
-	(
-		CLK_I		: in  STD_LOGIC;
-		RST_I		: in  STD_LOGIC;
-		CYC_I		: in  STD_LOGIC;
-		STB_I		: in  STD_LOGIC;
-		ACK_O		: out STD_LOGIC;
-		MRDY_I		: in  STD_LOGIC;
-		SRDY_O		: out STD_LOGIC;
-		ADDR_I		: in  unsigned(31 downto 0);
-		DAT_O		: out unsigned(31 downto 0)
-	);
-	END COMPONENT;
-
-	COMPONENT lcd_port
-	PORT 
-	(
-		rst			: in std_logic;
-		clk			: in std_logic;
-		we			: in std_logic;
-		din			: in unsigned(7 downto 0);
-		dout		: out unsigned(7 downto 0);
-		lcd_d		: inout unsigned(3 downto 0);
-		lcd_e		: out std_logic;
-		lcd_rs		: out std_logic;
-		lcd_rw		: out std_logic
-	);
-	END COMPONENT;
-
-	COMPONENT async_port_wb
-	GENERIC
-	(
-		addr_width		: natural := 32;
-		data_width		: natural := 32;
-		byte_sel_width	: natural := 4;
-		async_timespec	: async_timespec_t
-	);
-	PORT
-	(
-		CLK_I		: in  STD_LOGIC;
-		RST_I		: in  STD_LOGIC;
-		CYC_I		: in  STD_LOGIC;
-		STB_I		: in  STD_LOGIC;
-		WE_I		: in  STD_LOGIC;
-		ACK_O		: out STD_LOGIC;
-		SRDY_O		: out STD_LOGIC;
-		MRDY_I		: in  STD_LOGIC;
-		SEL_I		: in  unsigned(3 downto 0);
-		ADDR_I		: in  unsigned(31 downto 0);
-		DAT_I		: in  unsigned(31 downto 0);
-		DAT_O		: out unsigned(31 downto 0);
-		async_a		: out unsigned(addr_width-1 downto 0);
-		async_d		: inout unsigned(data_width-1 downto 0);
-		async_cs	: out std_logic;
-		async_wr	: out std_logic;
-		async_rd	: out std_logic;
-		async_be	: out unsigned(byte_sel_width-1 downto 0);
-		async_rst	: out std_logic
-	);
-	END COMPONENT;
-
-	COMPONENT flash_port_wb
-	GENERIC
-	(
-		addr_width		: natural := 32;
-		data_width		: natural := 32;
-		async_timespec	: async_timespec_t
-	);
-	PORT
-	(
-		CLK_I		: in  STD_LOGIC;
-		RST_I		: in  STD_LOGIC;
-		CYC_I		: in  STD_LOGIC;
-		STB_I		: in  STD_LOGIC;
-		WE_I		: in  STD_LOGIC;
-		ACK_O		: out STD_LOGIC;
-		SRDY_O		: out STD_LOGIC;
-		MRDY_I		: in  STD_LOGIC;
-		ADDR_I		: in  unsigned(31 downto 0);
-		DAT_I		: in  unsigned(31 downto 0);
-		DAT_O		: out unsigned(31 downto 0);
-		port_bsyo	: out std_logic;
-		port_bsyi	: in  std_logic;
-		port_a		: out unsigned(addr_width-1 downto 0);
-		port_di		: in  unsigned(data_width-1 downto 0);
-		port_do		: out unsigned(data_width-1 downto 0);
-		port_d_drv	: out STD_LOGIC;
-		port_wr		: out STD_LOGIC;
-		port_rd		: out STD_LOGIC;
-		flash_cs	: out std_logic;
-		flash_rst	: out std_logic
-	);
-	END COMPONENT;
-	
-	COMPONENT uart_wb
-	PORT
-	(
-		CLK_I		: in  STD_LOGIC;
-		RST_I		: in  STD_LOGIC;
-		CYC_I		: in  STD_LOGIC;
-		STB_I		: in  STD_LOGIC;
-		SEL_I		: in  unsigned(3 downto 0);
-		WE_I		: in  STD_LOGIC;
-		ACK_O		: out STD_LOGIC;
-		SRDY_O		: out STD_LOGIC;
-		MRDY_I		: in  STD_LOGIC;
-		ADDR_I		: in  unsigned(31 downto 0);
-		DAT_I		: in  unsigned(31 downto 0);
-		DAT_O		: out unsigned(31 downto 0);
-		INT_RX_O	: out STD_LOGIC;
-		INT_TX_O	: out STD_LOGIC;
-		ser_rx		: in std_logic;
-		ser_tx		: out std_logic
-	);
-	END COMPONENT;
-
-	COMPONENT gpio_wb
-	PORT
-	(
-		CLK_I		: in  STD_LOGIC;
-		RST_I		: in  STD_LOGIC;
-		CYC_I		: in  STD_LOGIC;
-		STB_I		: in  STD_LOGIC;
-		SEL_I		: in  unsigned(3 downto 0);
-		WE_I		: in  STD_LOGIC;
-		ACK_O		: out STD_LOGIC;
-		SRDY_O		: out STD_LOGIC;
-		MRDY_I		: in  STD_LOGIC;
-		ADDR_I		: in  unsigned(31 downto 0);
-		DAT_I		: in  unsigned(31 downto 0);
-		DAT_O		: out unsigned(31 downto 0);
-
-		sys_gpo0	: out unsigned(31 downto 0);
-		sys_gpo1	: out unsigned(31 downto 0);
-		sys_gpi0	: in  unsigned(31 downto 0);
-		sys_gpi1	: in  unsigned(31 downto 0)
-	);
-	END COMPONENT;
-
-	COMPONENT vga_frontend64
-	GENERIC
-	(
-		sys_freq					: integer;
-		fifo_depth					: integer;
-		fifo_almost_full_thresh		: natural;
-		fifo_almost_empty_thresh	: natural;
-		tsvga						: vga_timespec_t
-	);
-	PORT
-	(
-		-- System signals
-		RST_I			: in  STD_LOGIC;
-		CLK_I			: in  STD_LOGIC;
-
-		-- JBUS Master signals
-		CYC_O			: out STD_LOGIC;
-		STB_O			: out STD_LOGIC;
-		WE_O			: out STD_LOGIC;
-		SEL_O			: out unsigned(7 downto 0);
-		ACK_I			: in  STD_LOGIC;
-		SRDY_I			: in  STD_LOGIC;
-		MRDY_O			: out STD_LOGIC;
-		ADDR_O			: out unsigned(31 downto 0);
-		MDAT_I			: in  unsigned(63 downto 0);
-		MDAT_O			: out unsigned(63 downto 0);
-
-		-- JBUS Slave signals
-		CYC_I			: in  STD_LOGIC;
-		STB_I			: in  STD_LOGIC;
-		WE_I			: in  STD_LOGIC;
-		SEL_I			: in  unsigned(3 downto 0);
-		ACK_O			: out STD_LOGIC;
-		SRDY_O			: out STD_LOGIC;
-		MRDY_I			: in  STD_LOGIC;
-		ADDR_I			: in  unsigned(31 downto 0);
-		SDAT_I			: in  unsigned(31 downto 0);
-		SDAT_O			: out unsigned(31 downto 0);
-		
-		-- VGA signals
-		vga_clk_out		: out std_logic;
-		vga_red			: out unsigned(7 downto 0);
-		vga_green		: out unsigned(7 downto 0);
-		vga_blue		: out unsigned(7 downto 0);
-		vga_blank_n		: out std_logic;
-		vga_sync_n		: out std_logic;
-		vga_hsync		: out std_logic;
-		vga_vsync		: out std_logic
-	);
-	END COMPONENT;
-
-	signal rst			: std_logic;
-	signal clk			: std_logic;
-	signal clk270		: std_logic;
-	signal clk270var	: std_logic;
-	signal rst_in		: std_logic;
-	signal int_uart_rx	: std_logic;
-	signal locked		: std_logic;
-	signal ac97_rstn	: std_logic;
-	signal flash_rstn	: std_logic;
-	signal ADDR_I_usb 	: unsigned(31 downto 0);
-	signal ADDR_I_flash	: unsigned(31 downto 0);
-	signal ADDR_I_ssram	: unsigned(31 downto 0);
-	signal ssram_clk	: std_logic;
-	signal ssram_a		: unsigned(24 downto 0);
-	signal ssram_do		: unsigned(31 downto 0);
-	signal ssram_oe_n	: std_logic;
-	signal ssram_we_n	: std_logic;
-	signal ssram_d_drv	: std_logic;
-	signal ssram_bsy	: std_logic;
-	signal flash_a		: unsigned(24 downto 0);
-	signal flash_do		: unsigned(31 downto 0);
-	signal flash_oe_n	: std_logic;
-	signal flash_we_n	: std_logic;
-	signal flash_d_drv	: std_logic;
-	signal flash_bsy	: std_logic;
-	
-	-- Arbiter
-	constant ARB_MAX_MASTER	: natural := 2;
-	signal arb_idx		: natural range 0 to ARB_MAX_MASTER-1;
-	signal arb_req		: unsigned (ARB_MAX_MASTER-1 downto 0);
-	signal arb_gnt		: unsigned (ARB_MAX_MASTER-1 downto 0);
-	
-	-- J-Bus signals
-	signal INT	 		: unsigned(5 downto 0);
-	signal MDAT_I		: word_t;
-	signal MDAT_O 		: word_t;
-	signal ADDR_O 		: word_t;
-	signal SEL_O 		: unsigned(3 downto 0);
-	signal WE_O 		: std_logic;
-	signal CYC_O 		: std_logic;
-	signal STB_O 		: std_logic;
-	signal ACK_I		: std_logic;
-	signal SRDY_I		: std_logic;
-	signal MRDY_O		: std_logic;
-
-	-- CPU Master
-	signal MRDY_O_cpu	: std_logic;
-	signal MDAT_O_cpu	: word_t;
-	signal ADDR_O_cpu	: word_t;
-	signal SEL_O_cpu	: unsigned(3 downto 0);
-	signal WE_O_cpu		: std_logic;
-	signal CYC_O_cpu	: std_logic;
-	signal STB_O_cpu	: std_logic;
-	signal SRDY_I_cpu	: std_logic;
-	signal ACK_I_cpu	: std_logic;
-
-	-- VGA Master
-	signal MRDY_O_vga	: std_logic;
-	signal ADDR_O_vga	: word_t;
-	signal SEL_O_vga	: unsigned(7 downto 0);
-	signal WE_O_vga		: std_logic;
-	signal CYC_O_vga	: std_logic;
-	signal STB_O_vga	: std_logic;
-	signal SRDY_I_vga	: std_logic;
-	signal ACK_I_vga	: std_logic;
-	signal MDAT_I_vga	: unsigned(63 downto 0);
-	signal MDAT_O_vga	: unsigned(63 downto 0);
-
-	-- Slaves
-	signal CYC_I_flash	: std_logic;
-	signal ACK_O_flash	: std_logic;
-	signal SRDY_O_flash	: std_logic;
-	signal SDAT_O_flash	: unsigned(31 downto 0);
-
-	signal CYC_I_usb	: std_logic;
-	signal ACK_O_usb	: std_logic;
-	signal SRDY_O_usb	: std_logic;
-	signal SDAT_O_usb	: unsigned(31 downto 0);
-
-	signal CYC_I_sdram	: std_logic;
-	signal ACK_O_sdram	: std_logic;
-	signal SRDY_O_sdram	: std_logic;
-	signal SDAT_O_sdram	: unsigned(63 downto 0);
-	signal SDAT_I_sdram	: unsigned(63 downto 0);
-	signal SEL_I_sdram	: unsigned(7 downto 0);
-
-	signal CYC_I_rom	: std_logic;
-	signal ACK_O_rom	: std_logic;
-	signal SRDY_O_rom	: std_logic;
-	signal SDAT_O_rom	: unsigned(31 downto 0);
-
-	signal CYC_I_gpio	: std_logic;
-	signal ACK_O_gpio	: std_logic;
-	signal SRDY_O_gpio	: std_logic;
-	signal SDAT_O_gpio	: unsigned(31 downto 0);
-
-	signal CYC_I_uart	: std_logic;
-	signal ACK_O_uart	: std_logic;
-	signal SRDY_O_uart	: std_logic;
-	signal SDAT_O_uart	: unsigned(31 downto 0);
-
-	signal CYC_I_vga	: std_logic;
-	signal ACK_O_vga	: std_logic;
-	signal SRDY_O_vga	: std_logic;
-	signal SDAT_O_vga	: unsigned(31 downto 0);
-
-	signal CYC_I_ssram	: std_logic;
-	signal ACK_O_ssram	: std_logic;
-	signal SRDY_O_ssram	: std_logic;
-	signal SDAT_O_ssram	: unsigned(31 downto 0);
-
-	signal INT_O_ac97	: std_logic;
-	signal CYC_I_ac97	: std_logic;
-	signal ACK_O_ac97	: std_logic;
-	signal SRDY_O_ac97	: std_logic;
-	signal SDAT_O_ac97	: unsigned(31 downto 0);
-
-	signal gpo0			: unsigned(31 downto 0);
-	signal gpo1			: unsigned(31 downto 0);
-	signal gpi0			: unsigned(31 downto 0);
-	signal gpi1			: unsigned(31 downto 0);
-
-	signal debug		: unsigned(1 downto 0);
-
-	-- DDR SDRAM
-	constant BURST_LEN	: natural := 2;
-	constant topad	: time := 3 ns;
-
-	
---	attribute rom_style: string;
---	attribute rom_style of cmd_fifo_dout: signal is "DISTRIBUTED";
---	attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
---	attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";
-
-	type mem_area_t is (mem_dead, mem_flash, mem_ssram, mem_usb, mem_rom, mem_gpio, mem_uart, mem_sdram, mem_vga, mem_ac97);
-	signal mem_area : mem_area_t;
-
-BEGIN
-
-	gpi0(4 downto 0)	<= sys_btn;
-	gpi1(7 downto 0)	<= sys_dip;
-	sys_led				<= gpo0(8 downto 0);
-	sys_error			<= debug;
-	rst_in 				<= not sys_rst_n_in;
-	rst					<= not locked;
-	sys_usb_rstn		<= not gpo1(0);
-	sys_flash_byten		<= '1';
-	ADDR_I_usb			<= X"0000000" & "00" & ADDR_O(3 downto 2);
-	ADDR_I_flash		<= "0000000" & ADDR_O(25 downto 2) & '0';
-	ADDR_I_ssram		<= ("0000000000000" & ADDR_O(19 downto 2)) & '0';
-
-	SDAT_I_sdram		<= MDAT_O & MDAT_O;
-	SEL_I_sdram			<= "0000" & SEL_O;
-
-	sys_flash_ac97_rstn	<= ac97_rstn and flash_rstn;
-	
-sys_flash_ssram_out:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			sys_flash_ssram_d		<= (others => 'Z') after topad;
-			sys_flash_ssram_oe_n	<= '1';
-			sys_flash_ssram_we_n	<= '1';
-			if flash_bsy = '1' then
-				sys_flash_ssram_oe_n	<= flash_oe_n;
-				sys_flash_ssram_we_n	<= flash_we_n;
-				sys_flash_ssram_a 		<= flash_a after topad;
-				if flash_d_drv = '1' then
-					sys_flash_ssram_d	<= flash_do after topad;
-				end if;
-			elsif ssram_bsy = '1' then
-				sys_flash_ssram_oe_n	<= ssram_oe_n;
-				sys_flash_ssram_we_n	<= ssram_we_n;
-				sys_flash_ssram_a 		<= ssram_a after topad;
-				if ssram_d_drv = '1' then
-					sys_flash_ssram_d	<= ssram_do after topad;
-				end if;
-			end if;	
-		end if;
-	end process;
-	
-	---------------------------------------------------------------
-	-- Arbiter
-	MRDY_O		<= MRDY_O_cpu when arb_gnt(0) = '1' else MRDY_O_vga when arb_gnt(1) = '1' else '0';
-	MDAT_O		<= MDAT_O_cpu when arb_gnt(0) = '1' else MDAT_O_vga(31 downto 0) when arb_gnt(1) = '1' else (others => '0');
-	ADDR_O		<= ADDR_O_cpu when arb_gnt(0) = '1' else ADDR_O_vga when arb_gnt(1) = '1' else (others => '0');
-	SEL_O		<= SEL_O_cpu when arb_gnt(0) = '1' else SEL_O_vga(3 downto 0) when arb_gnt(1) = '1' else (others => '0');
-	WE_O		<= WE_O_cpu when arb_gnt(0) = '1' else WE_O_vga when arb_gnt(1) = '1' else '0';
-	CYC_O		<= CYC_O_cpu when arb_gnt(0) = '1' else CYC_O_vga when arb_gnt(1) = '1' else '0';
-	STB_O		<= STB_O_cpu when arb_gnt(0) = '1' else STB_O_vga when arb_gnt(1) = '1' else '0';
-	SRDY_I_cpu	<= SRDY_I and arb_gnt(0);
-	SRDY_I_vga	<= SRDY_I and arb_gnt(1);
-	ACK_I_cpu	<= ACK_I and arb_gnt(0);
-	ACK_I_vga	<= ACK_I and arb_gnt(1);
-	
-	arb_req(0)	<= CYC_O_cpu;
-	arb_req(1)	<= CYC_O_vga;
-	
-	MDAT_I_vga	<= SDAT_O_sdram(63 downto 32) & MDAT_I;
-	
-arbiter_proc:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				arb_gnt	<= (others => '0');
-				arb_idx	<= 0;
-			elsif arb_req(arb_idx) = '0' then
-				if arb_idx /= ARB_MAX_MASTER-1 then
-					arb_idx	<= arb_idx + 1;
-				else
-					arb_idx	<= 0;
-				end if;
-			else	
-				arb_gnt	<= (others => '0');
-				arb_gnt(arb_idx)	<= '1';
-			end if;	
-		end if;
-	end process;
-	
-int_sample:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			int <= "00" & INT_O_ac97 & sys_usb_int & int_uart_rx & sys_btn(4);
-		end if;
-	end process;
-	
-mem_mux:
-	process(ADDR_O)
-	begin
-		mem_area	<= mem_dead;
-		if ADDR_O(31 downto 28) = X"0" then
-			mem_area	<= mem_flash;
-		elsif ADDR_O(31 downto 28) = X"A" then
-			if ADDR_O(27 downto 26) = "00" then
-				if ADDR_O(18 downto 16) = "000" then
-					mem_area	<= mem_gpio;
-				elsif ADDR_O(18 downto 16) = "001" then
-					mem_area	<= mem_uart;
-				elsif ADDR_O(18 downto 16) = "010" then
-					mem_area	<= mem_usb;
-				elsif ADDR_O(18 downto 16) = "011" then
-					mem_area	<= mem_vga;
-				elsif ADDR_O(18 downto 16) = "100" then
-					mem_area	<= mem_ac97;
-				end if;	
-			elsif ADDR_O(27 downto 26) = "01" then
-				mem_area	<= mem_flash;
-			elsif ADDR_O(27 downto 26) = "10" then
-				mem_area	<= mem_ssram;
-			end if;	
-		elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
-			mem_area	<= mem_rom;
---		elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
-			-- kernel sram
-		elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
-			mem_area	<= mem_sdram;
-		end if;
-	end process;	
-
-signal_mux:
-	process(mem_area, CYC_O)
-	begin
-	
-		CYC_I_uart		<= '0';
-		CYC_I_gpio		<= '0';
-		CYC_I_flash		<= '0';
-		CYC_I_usb		<= '0';
-		CYC_I_rom		<= '0';
-		CYC_I_sdram		<= '0';
-		CYC_I_vga		<= '0';
-		CYC_I_ssram		<= '0';
-		CYC_I_ac97		<= '0';
-		
-		case mem_area is
-
-		when mem_gpio =>
-			CYC_I_gpio		<= CYC_O;
-
-		when mem_uart =>
-			CYC_I_uart		<= CYC_O;
-
-		when mem_flash =>
-			CYC_I_flash		<= CYC_O;
-
-		when mem_usb =>
-			CYC_I_usb		<= CYC_O;
-
-		when mem_rom =>
-			CYC_I_rom		<= CYC_O;
-
-		when mem_sdram =>
-			CYC_I_sdram		<= CYC_O;
-		
-		when mem_vga =>
-			CYC_I_vga		<= CYC_O;
-
-		when mem_ac97 =>
-			CYC_I_ac97		<= CYC_O;
-
-		when mem_ssram =>
-			CYC_I_ssram		<= CYC_O;
-
-		when others => null;
-		
-		end case;
-		
-	end process;
-
-------------------------------------------------------------------
- 	SRDY_I		<=	SRDY_O_flash or SRDY_O_ssram or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
- 	ACK_I		<=	ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ssram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
- 	MDAT_I		<=	SDAT_O_ssram when CYC_I_ssram = '1' else
- 					SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else
-					SDAT_O_rom when CYC_I_rom = '1' else
-					SDAT_O_flash when CYC_I_flash = '1' else
-					SDAT_O_usb when CYC_I_usb = '1' else
-					SDAT_O_uart when CYC_I_uart = '1' else
-					SDAT_O_vga when CYC_I_vga = '1' else
-					SDAT_O_ac97 when CYC_I_ac97 = '1' else
-					SDAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
-
-------------------------------------------------------------------
-inst_mips_top: mips_top
-	PORT MAP
-	(
-		debug			=> debug,
-		RST_I			=> rst,
-		CLK_I			=> clk,
-		ACK_I			=> ACK_I_cpu,
-		SRDY_I			=> SRDY_I_cpu,
-		MRDY_O			=> MRDY_O_cpu,
-		CYC_O			=> CYC_O_cpu,
-		STB_O			=> STB_O_cpu,
-		WE_O			=> WE_O_cpu,
-		SEL_O			=> SEL_O_cpu,
-		DAT_I			=> MDAT_I,
-		DAT_O			=> MDAT_O_cpu,
-		ADDR_O			=> ADDR_O_cpu,
-		INT				=> INT
-	);
-
-inst_rom_wb : rom_wb
-	PORT MAP
-	(
-		CLK_I	=> clk,
-		RST_I	=> rst,
-		CYC_I	=> CYC_I_rom,
-		STB_I	=> STB_O,
-		ACK_O	=> ACK_O_rom,
-		MRDY_I	=> MRDY_O,
-		SRDY_O	=> SRDY_O_rom,
-		ADDR_I	=> ADDR_O,
-		DAT_O	=> SDAT_O_rom
-	);
-
-
-inst_lcd_port: lcd_port
-	PORT MAP
-	(
-		clk => clk,
-		rst => rst,
-		we => '0',
-		din => X"00",
-		dout => open,
-		lcd_d => sys_lcd_d,
-		lcd_e => sys_lcd_e,
-		lcd_rs => sys_lcd_rs,
-		lcd_rw => sys_lcd_rw
-	);
-	
-inst_gpio_wb : gpio_wb
-	PORT MAP
-	(
-		CLK_I		=> clk,
-		RST_I		=> rst,
-		CYC_I		=> CYC_I_gpio,
-		STB_I		=> STB_O,
-		SEL_I		=> SEL_O,
-		WE_I		=> WE_O,
-		ACK_O		=> ACK_O_gpio,
-		SRDY_O		=> SRDY_O_gpio,
-		MRDY_I		=> MRDY_O,
-		ADDR_I		=> ADDR_O,
-		DAT_I		=> MDAT_O,
-		DAT_O		=> SDAT_O_gpio,
-
-		sys_gpo0	=> gpo0,
-		sys_gpo1	=> gpo1,
-		sys_gpi0	=> gpi0,
-		sys_gpi1	=> gpi1
-	);
-
-inst_flash_port : flash_port_wb
-	GENERIC MAP
-	(
-		addr_width		=> 25,
-		data_width		=> 32,
-		async_timespec	=> ts_flash
-	)
-	PORT MAP
-	(
-		CLK_I		=> clk,
-		RST_I		=> rst,
-		CYC_I		=> CYC_I_flash,
-		STB_I		=> STB_O,
-		WE_I		=> WE_O,
-		ACK_O		=> ACK_O_flash,
-		SRDY_O		=> SRDY_O_flash,
-		MRDY_I		=> MRDY_O,
-		ADDR_I		=> ADDR_I_flash,
-		DAT_I		=> MDAT_O,
-		DAT_O		=> SDAT_O_flash,
-		port_bsyo	=> flash_bsy,
-		port_bsyi	=> ssram_bsy,
-		port_a		=> flash_a,
-		port_di		=> sys_flash_ssram_d,
-		port_do		=> flash_do,
-		port_d_drv	=> flash_d_drv,
-		port_wr		=> flash_we_n,
-		port_rd		=> flash_oe_n,
-		flash_cs	=> sys_flash_ce,
-		flash_rst	=> flash_rstn
-	);
-
-inst_usb_port : async_port_wb
-	GENERIC MAP
-	(
-		addr_width		=> 2,
-		data_width		=> 16,
-		byte_sel_width	=> 1,
-		async_timespec	=> ts_usb
-	)
-	PORT MAP
-	(
-		CLK_I		=> clk,
-		RST_I		=> rst,
-		CYC_I		=> CYC_I_usb,
-		STB_I		=> STB_O,
-		WE_I		=> WE_O,
-		ACK_O		=> ACK_O_usb,
-		SRDY_O		=> SRDY_O_usb,
-		MRDY_I		=> MRDY_O,
-		SEL_I		=> SEL_O,
-		ADDR_I		=> ADDR_I_usb,
-		DAT_I		=> MDAT_O,
-		DAT_O		=> SDAT_O_usb,
-		async_a		=> sys_usb_a,
-		async_d		=> sys_usb_d,
-		async_cs	=> sys_usb_csn,
-		async_wr	=> sys_usb_wrn,
-		async_rd	=> sys_usb_rdn,
-		async_be	=> open,
-		async_rst	=> open
-	);
-
-inst_uart_wb : uart_wb
-	PORT MAP
-	(
-		CLK_I		=> clk,
-		RST_I		=> rst,
-		CYC_I		=> CYC_I_uart,
-		STB_I		=> STB_O,
-		SEL_I		=> SEL_O,
-		WE_I		=> WE_O,
-		ACK_O		=> ACK_O_uart,
-		SRDY_O		=> SRDY_O_uart,
-		MRDY_I		=> MRDY_O,
-		ADDR_I		=> ADDR_O,
-		DAT_I		=> MDAT_O,
-		DAT_O		=> SDAT_O_uart,
-		INT_RX_O	=> int_uart_rx,
-		INT_TX_O	=> open,
-		ser_rx		=> sys_rx,
-		ser_tx		=> sys_tx
-	);
-
-inst_ssram_port_wb : entity work.ssram_port_wb
-	GENERIC MAP
-	(
-		addr_width		=> 25,
-		data_width		=> 32,
-		parity_width	=> 4
-	)
-	PORT MAP
-	(
-		-- J-Bus domain
-		RST_I		=> rst,
-		CLK_I		=> clk,
-		CYC_I		=> CYC_I_ssram,
-		STB_I		=> STB_O,
-		SEL_I		=> SEL_O,
-		WE_I		=> WE_O,
-		ACK_O		=> ACK_O_ssram,
-		SRDY_O		=> SRDY_O_ssram,
-		MRDY_I		=> MRDY_O,
-		ADDR_I		=> ADDR_I_ssram,
-		DAT_I		=> MDAT_O,
-		DAT_O		=> SDAT_O_ssram,
-		
-		-- Sync SRAM domain
-		ssram_clk_o		=> sys_ssram_clk,
-		ssram_clk_fb	=> sys_ssram_clk_fb,
-		ssram_cke_n		=> sys_ssram_cke_n,
-		ssram_ce_n		=> sys_ssram_ce_n,
-		port_bsyo		=> ssram_bsy,
-		port_bsyi		=> flash_bsy,
-		port_di			=> sys_flash_ssram_d,
-		port_do			=> ssram_do,
-		port_d_drv		=> ssram_d_drv,
-		port_wr			=> ssram_we_n,
-		port_rd			=> ssram_oe_n,
-		port_a			=> ssram_a,
-		ssram_adv		=> sys_ssram_adv,
-		ssram_mode		=> sys_ssram_mode,
-		ssram_zz		=> sys_ssram_zz,
-		ssram_dp		=> sys_ssram_dp,
-		ssram_bw_n		=> sys_ssram_bw_n
-	);
-
-inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
-	GENERIC MAP
-	(
-		BL			=> BURST_LEN,
-		f_sysclk	=> ddr_frequency_hz,
-		fifo_depth	=> 5
-	)
-	PORT MAP
-	(
-		RST_I			=> rst,
-		CLK_I			=> clk,
-		CLK270_I		=> clk270,
-		CLK270VAR_I		=> clk270var,
-		
-		CYC_I			=> CYC_I_sdram,
-		STB_I			=> STB_O,
-		SEL_I			=> SEL_I_sdram,
-		WE_I			=> WE_O,
-		ACK_O			=> ACK_O_sdram,
-		MRDY_I			=> MRDY_O,
-		SRDY_O			=> SRDY_O_sdram,
-		ADDR_I			=> ADDR_O,
-		DAT_I			=> SDAT_I_sdram,
-		DAT_O			=> SDAT_O_sdram,
-
-		-- SDRAM signals
-		sd_clk_p		=> sys_sdr_clk_p,
-		sd_clk_n		=> sys_sdr_clk_n,
-		sd_cke			=> sys_sdr_cke_q,
-		sd_cs_n			=> sys_sdr_cs_qn,
-		sd_cas_n		=> sys_sdr_cas_qn,
-		sd_ras_n		=> sys_sdr_ras_qn,
-		sd_we_n			=> sys_sdr_we_qn,
-		sd_addr			=> sys_sdr_a_q,
-		sd_ba			=> sys_sdr_ba_q,
-		sd_dm			=> sys_sdr_dm_q,
-		sd_dqs			=> sys_sdr_dqs_q,
-		sd_data			=> sys_sdr_data
-		
-	);
-
-inst_clockgen : entity work.clockgen
-	GENERIC MAP
-	(
-		sys1_phaseshift	=> 0,
-		frequency_hz	=> 100E6
-	)
-	PORT MAP 
-	(
-		-- Clocks and Reset
-		rst				=> rst_in,   -- external async reset, low active
-		clk_in			=> sys_clk_in,   -- system clock (e.g. 100MHz), from board
-		clk_fb_in		=> sys_sdr_clk_fb,   -- feedback clock
-		sys1_clk0_out	=> open,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
-		sys1_clk270_out	=> clk270var,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
-		sys0_clk0_out	=> clk,  -- System clock #0, dcm#0 output 0°
-		sys0_clk270_out	=> clk270,  -- System clock #0, dcm#0 output 270°
-		locked_out		=> locked,  -- DCM locked status
-		error_out		=> open
-	);
-
-inst_vga_frontend : vga_frontend64
-	GENERIC MAP
-	(
-		sys_freq					=> 100E6,
-		fifo_depth					=> 2048,
-		fifo_almost_full_thresh		=> 1860,
-		fifo_almost_empty_thresh	=> 256,
-		tsvga						=> ts_vga_testbench
-	)
-	PORT MAP
-	(
-		-- System signals
-		RST_I			=> rst,
-		CLK_I			=> clk,
-
-		-- JBUS Master signals
-		CYC_O			=> CYC_O_vga,
-		STB_O			=> STB_O_vga,
-		WE_O			=> WE_O_vga,
-		SEL_O			=> SEL_O_vga,
-		ACK_I			=> ACK_I_vga,
-		SRDY_I			=> SRDY_I_vga,
-		MRDY_O			=> MRDY_O_vga,
-		ADDR_O			=> ADDR_O_vga,
-		MDAT_I			=> MDAT_I_vga,
-		MDAT_O			=> MDAT_O_vga,
-
-		-- JBUS Slave signals
-		CYC_I			=> CYC_I_vga,
-		STB_I			=> STB_O,
-		WE_I			=> WE_O,
-		SEL_I			=> SEL_O,
-		ACK_O			=> ACK_O_vga,
-		SRDY_O			=> SRDY_O_vga,
-		MRDY_I			=> MRDY_O,
-		ADDR_I			=> ADDR_O,
-		SDAT_I			=> MDAT_O,
-		SDAT_O			=> SDAT_O_vga,
-
-		-- VGA signals
-		vga_clk_out		=> sys_vga_clk,
-		vga_red			=> sys_vga_red,
-		vga_green		=> sys_vga_green,
-		vga_blue		=> sys_vga_blue,
-		vga_blank_n		=> sys_vga_blank_n,
-		vga_sync_n		=> sys_vga_sync_n,
-		vga_hsync		=> sys_vga_hsync,
-		vga_vsync		=> sys_vga_vsync	
-	);
-
-inst_ac97_wb : entity work.ac97_wb
-	GENERIC MAP
-	(
-		fifo_depth		=> 4
-	)
-	PORT MAP
-	(
-		-- J-Bus domain
-		CLK_I			=> clk,
-		RST_I			=> rst,
-		CYC_I			=> CYC_I_ac97,
-		STB_I			=> STB_O,
-		WE_I			=> WE_O,
-		ACK_O			=> ACK_O_ac97,
-		SRDY_O			=> SRDY_O_ac97,
-		MRDY_I			=> MRDY_O,
-		ADDR_I			=> ADDR_O,
-		DAT_I			=> MDAT_O,
-		DAT_O			=> SDAT_O_ac97,
-		INT_O			=> INT_O_ac97,
-
-		-- AC97 domain
-		ac97_sdata_in	=> sys_ac97_sdata_in,
-		ac97_bit_clk	=> sys_ac97_bit_clk,          
-		ac97_reset_n	=> ac97_rstn,
-		ac97_sdata_out	=> sys_ac97_sdata_out,
-		ac97_ssync		=> sys_ac97_ssync		
-	);
-
-	------------------------------------------------------------------
-END;
diff --git a/projects/mips_sys/src/ram_ld.vhd b/projects/mips_sys/src/ram_ld.vhd
deleted file mode 100644
index 17879e1..0000000
--- a/projects/mips_sys/src/ram_ld.vhd
+++ /dev/null
@@ -1,173 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-ENTITY ram IS
-	Port 
-	(
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		we			: in  unsigned(3 downto 0);
-		addr		: in  unsigned(31 downto 0);
-		din			: in  unsigned(31 downto 0);
-		dout		: out unsigned(31 downto 0)
-	);
-END ram;
-
-ARCHITECTURE behavior OF ram IS 
-
-	COMPONENT dpram_2w2r
-	Generic 
-	(
-		addr_width : integer;
-		data_width : integer
-	);
-	Port
-	(
-		clk_a		: in  STD_LOGIC;
-		clk_b		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		we_b		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		din_b		: in  unsigned (data_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-	END COMPONENT;
-	
-	signal jtag_clk		: STD_LOGIC;
-	signal jtag_we		: unsigned(3 downto 0);
-	signal jtag_addr	: unsigned (15 downto 0);
-	signal jtag_dout	: unsigned (31 downto 0);
-	signal jtag_din		: unsigned (31 downto 0);
-	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
-	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
-	signal user_regi, user_rego : unsigned (47 downto 0);
-	
-BEGIN
-
-gen_sram:
-	for i in 0 to 3 generate
-	begin
-	inst_dpram_2w2r : dpram_2w2r
-		GENERIC MAP
-		(
-			addr_width	=> 11,
-			data_width	=> 8
-		)
-		PORT MAP
-		(
-			clk_a		=> clk,
-			en_a		=> ce,
-			we_a		=> we(i),
-			addr_a		=> addr(12 downto 2),
-			din_a		=> din((i+1)*8-1 downto i*8),
-			dout_a		=> dout((i+1)*8-1 downto i*8),
-
-			clk_b		=> jtag_clk,
-			en_b		=> jtag_we(i),
-			we_b		=> jtag_we(i),
-			addr_b		=> jtag_addr(10 downto 0),
-			din_b		=> jtag_din((i+1)*8-1 downto i*8),
-			dout_b		=> jtag_dout((i+1)*8-1 downto i*8)
-		);
-	end generate;
-	
---------------------------------------------------------------------------
--- Virtex-4: JTAG Loader
---------------------------------------------------------------------------
-	i00_BUFG : BUFG
-	port map
-	(
-		O => bs_clk1,
-        I => bs_clk0
-	);
-	
-	i01_BUFG : BUFG
-	port map
-	(
-		O => bs_update1,
-        I => bs_update0
-	);
-
-	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
-	generic map
-	(
-		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
-	)
-	port map 
-	(
-		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
-		DRCK => bs_clk0,       -- Data register output for USER functions
-		RESET => bs_rst,       -- Reset output from TAP controller
-		SEL => bs_sel,         -- USER active output
-		SHIFT => bs_shift,     -- SHIFT output from TAP controller
-		TDI => bs_tdi,        -- TDI output from TAP controller
-		UPDATE => bs_update0,   -- UPDATE output from TAP controller
-		TDO => bs_tdo         -- Data input for USER function
-	);
-
-	jtag_addr	<= user_regi(user_regi'left downto jtag_dout'length);
-	jtag_din	<= user_regi(jtag_dout'length-1 downto 0);
-	jtag_clk	<= bs_update1;
-	jtag_we		<= (3 downto 0 => bs_sel);
-	
-sipo:
-	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
-	begin
-		if bs_rst = '1' then
-			user_regi <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
-			end if;
-		end if;
-	end process;	
-
-piso:
-	process (bs_rst, bs_clk1, bs_shift, user_rego)
-	begin
-		bs_tdo <= user_rego(0);
-		if bs_rst = '1' then
-			user_rego <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
-			else
-				user_rego <= (user_rego'left downto jtag_dout'length => '0') & jtag_dout;	
-			end if;
-		end if;
-	end process;	
-	
---------------------------------------------------------------------------
-end behavior;
diff --git a/projects/mips_sys/src/ram_sim.vhd b/projects/mips_sys/src/ram_sim.vhd
deleted file mode 100644
index 6d26672..0000000
--- a/projects/mips_sys/src/ram_sim.vhd
+++ /dev/null
@@ -1,88 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-
-ENTITY ram IS
-	Generic 
-	(
-		word_addr_width 	: integer := 6
-	);
-	Port 
-	(
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		we			: in  unsigned(3 downto 0);
-		addr		: in  unsigned(31 downto 0);
-		din			: in  unsigned(31 downto 0);
-		dout		: out unsigned(31 downto 0)
-	);
-END ram;
-
-ARCHITECTURE behavior OF ram IS 
-
-	constant depth : natural := 2**word_addr_width;
-	
-	type sram_t is array (0 to depth-1) of unsigned(31 downto 0);
-
-	function sram_clear return sram_t is
-
-	variable result : sram_t;
-	begin
-		for i in 0 to sram_t'length-1 loop
-			result(i) := (others => '0');
-		end loop;
-		return result;
-	end sram_clear;
-
-	signal sram : sram_t := sram_clear;
-	
-BEGIN
-
-
-SRAM_RW:
-	process(clk)
-	variable index : natural range 0 to depth-1;
-	begin
-		if rising_edge(clk) and ce = '1' then
-			index := to_integer(addr(word_addr_width+1 downto 2));
-			if we(0) = '1' then
-				sram(index)(7 downto 0)		<= din(7 downto 0);
-			end if;	
-			if we(1) = '1' then
-				sram(index)(15 downto 8)	<= din(15 downto 8);
-			end if;	
-			if we(2) = '1' then
-				sram(index)(23 downto 16)	<= din(23 downto 16);
-			end if;	
-			if we(3) = '1' then
-				sram(index)(31 downto 24)	<= din(31 downto 24);
-			end if;	
-			dout <= sram(index);
-		end if;	
-	end process;
-	
-end behavior;
diff --git a/projects/mips_sys/src/sdram_config.vhd b/projects/mips_sys/src/sdram_config.vhd
deleted file mode 100644
index 1bdf8e0..0000000
--- a/projects/mips_sys/src/sdram_config.vhd
+++ /dev/null
@@ -1,74 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: User SDRAM component adjustments
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-package sdram_config is
-
-	constant DDR_DATA_WIDTH 	: positive := 32;  -- External DDR-SDRAM Module data bus width
-	constant DDR_ADDR_WIDTH 	: positive := 13;  -- number of address lines to DDR-SDRAM Device/Module
-	constant DDR_BANK_WIDTH 	: positive := 2;   -- Number of BANK address lines of external DDR-SDRAM
-	constant DDR_ROW_ADDR_WIDTH	: positive := 13;  -- 
-	constant DDR_COL_ADDR_WIDTH	: positive := 9;  -- 
-	
-	constant LMR_REG_BASE		: natural := 0;
-	constant LMR_REG_EXTENDED	: natural := 1;
-	constant LMR_OP_NORMAL		: natural := 0;
-	constant LMR_OP_RES_DLL		: natural := 2;
-	constant LMR_BT_SEQ			: natural := 0;
-	constant LMR_BT_ILVD		: natural := 1;
-	constant LMR_BL2			: natural := 1;
-	constant LMR_BL4			: natural := 2;
-	constant LMR_BL8			: natural := 3;
-	constant LMR_CL2			: natural := 2;
-	constant LMR_CL3			: natural := 3;
-	constant LMR_CL2_5			: natural := 6;
-	
-	-- DDR SDRAM Hardware defined constants
-	constant BIT_AUTO_PRE		: positive := 10; -- bit-position in column address for auto precharge (see Data Sheet)
-	constant BIT_PRE_ALL		: positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
-	constant ENABLE_PRE_ALL		: std_logic := '1';
-	constant ENABLE_AUTO_PRE	: std_logic := '0';
-	
-	-- DDR-SDR TIMING constants ------------------------------------------------------------------
-	-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh 
-	constant REFRESH_INTERVAL : real := 7.8125; -- us
-
-	-- These values are for your SDRAM part (see datasheet) 
-	constant TCAS : positive  := 2;   -- CAS latency [clocks]
-	constant TRP  : positive  := 2;   -- precharge command period
-	constant TRAS : positive  := 5;   -- active to precharge delay 
-	constant TRFC : positive  := 8;   -- auto refresh command period
-	constant TMRD : positive  := 2;   -- load mode register command cylce time
-	constant TRCD : positive  := 2;   -- active to read or write delay !
-	constant TWR  : positive  := 2;   -- write recovery time
-
-	constant PWR_UP_WAIT : natural := 222; -- µs
-
-	subtype user_tag_t is unsigned(3 downto 0);
-
-	----------------------------------------------------------------------------------------------
-	
-end sdram_config;
diff --git a/projects/mips_sys/src/sdram_config_sim.vhd b/projects/mips_sys/src/sdram_config_sim.vhd
deleted file mode 100644
index f698b29..0000000
--- a/projects/mips_sys/src/sdram_config_sim.vhd
+++ /dev/null
@@ -1,74 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: User SDRAM component adjustments
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-package sdram_config is
-
-	constant DDR_DATA_WIDTH 	: positive := 32;  -- External DDR-SDRAM Module data bus width
-	constant DDR_ADDR_WIDTH 	: positive := 13;  -- number of address lines to DDR-SDRAM Device/Module
-	constant DDR_BANK_WIDTH 	: positive := 2;   -- Number of BANK address lines of external DDR-SDRAM
-	constant DDR_ROW_ADDR_WIDTH	: positive := 13;  -- 
-	constant DDR_COL_ADDR_WIDTH	: positive := 9;  -- 
-	
-	constant LMR_REG_BASE		: natural := 0;
-	constant LMR_REG_EXTENDED	: natural := 1;
-	constant LMR_OP_NORMAL		: natural := 0;
-	constant LMR_OP_RES_DLL		: natural := 2;
-	constant LMR_BT_SEQ			: natural := 0;
-	constant LMR_BT_ILVD		: natural := 1;
-	constant LMR_BL2			: natural := 1;
-	constant LMR_BL4			: natural := 2;
-	constant LMR_BL8			: natural := 3;
-	constant LMR_CL2			: natural := 2;
-	constant LMR_CL3			: natural := 3;
-	constant LMR_CL2_5			: natural := 6;
-	
-	-- DDR SDRAM Hardware defined constants
-	constant BIT_AUTO_PRE		: positive := 10; -- bit-position in column address for auto precharge (see Data Sheet)
-	constant BIT_PRE_ALL		: positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
-	constant ENABLE_PRE_ALL		: std_logic := '1';
-	constant ENABLE_AUTO_PRE	: std_logic := '0';
-	
-	-- DDR-SDR TIMING constants ------------------------------------------------------------------
-	-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh 
-	constant REFRESH_INTERVAL : real := 7.8125; -- us
-
-	-- These values are for your SDRAM part (see datasheet) 
-	constant TCAS : positive  := 2;   -- CAS latency [clocks]
-	constant TRP  : positive  := 2;   -- precharge command period
-	constant TRAS : positive  := 5;   -- active to precharge delay 
-	constant TRFC : positive  := 8;   -- auto refresh command period
-	constant TMRD : positive  := 2;   -- load mode register command cylce time
-	constant TRCD : positive  := 2;   -- active to read or write delay !
-	constant TWR  : positive  := 2;   -- write recovery time
-
-	constant PWR_UP_WAIT : natural := 22; -- µs
-
-	subtype user_tag_t is unsigned(3 downto 0);
-
-	----------------------------------------------------------------------------------------------
-	
-end sdram_config;
diff --git a/projects/mips_sys/src/sys_types.vhd b/projects/mips_sys/src/sys_types.vhd
deleted file mode 100644
index de3de9e..0000000
--- a/projects/mips_sys/src/sys_types.vhd
+++ /dev/null
@@ -1,64 +0,0 @@
--------------------------------------------------------------------------
--- Project: MIPS System controller
--- This file: 
---
--- Copyright (C) 2008 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-use work.async_types.all;
-
-package async_defs is
-
-	constant ts_flash : async_timespec_t :=
-	(
-		ncyc_access				=> 1,
-		ncyc_pulse_rd			=> 12,
-		ncyc_pulse_wr			=> 7,
-		ncyc_cs_hold			=> 1,
-		ncyc_release			=> 1,
-		ncyc_pulse_rst			=> 8,
-		pol_cs					=> '1',
-		pol_oe					=> '0',
-		pol_we					=> '0',
-		pol_be					=> '0',
-		pol_rst					=> '0'
-	);
-
-	constant ts_usb : async_timespec_t :=
-	(
-		ncyc_access				=> 1,
-		ncyc_pulse_rd			=> 6,
-		ncyc_pulse_wr			=> 6,
-		ncyc_cs_hold			=> 1,
-		ncyc_release			=> 6,
-		ncyc_pulse_rst			=> 8,
-		pol_cs					=> '0',
-		pol_oe					=> '0',
-		pol_we					=> '0',
-		pol_be					=> '0',
-		pol_rst					=> '0'
-	);
-
-	----------------------------------------------------------------------------------------------
-	
-end async_defs;
diff --git a/projects/mips_sys/src/tb_mips_sys.vhd b/projects/mips_sys/src/tb_mips_sys.vhd
deleted file mode 100644
index 610db8f..0000000
--- a/projects/mips_sys/src/tb_mips_sys.vhd
+++ /dev/null
@@ -1,339 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: testbench for system test using Xilinx ML-402
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library work;
-use work.mips_types.all;
-use work.sdram_config.all;
-use work.sdram_types.all;
-
-ENTITY tb_mips_sys IS
-END tb_mips_sys;
-
-ARCHITECTURE behavior OF tb_mips_sys IS 
-
-	constant CLK_PERIOD			: time := 10 ns;
-	constant AC97_CLK_PERIOD	: time := 83 ns;
-	signal sys_rst_n_in : std_logic := '0';
-	signal sys_clk_in : std_logic := '1';
-	signal dip  : unsigned(7 downto 0) := (others => '0');
-	signal btn  : unsigned(4 downto 0) := (others => '0');
-	signal led : unsigned(8 downto 0);
-	signal sys_rx : std_logic := '1';
-	signal sys_tx : std_logic;
-	
-	signal sys_lcd_d			: unsigned(3 downto 0);
-	signal sys_lcd_e			: std_logic;
-	signal sys_lcd_rs			: std_logic;
-	signal sys_lcd_rw			: std_logic;
-
-	signal refresh        : boolean:= true;
-
-	signal sys_sdr_clk_p		: std_logic;    -- ddr_sdram_clock
-	signal sys_sdr_clk_n		: std_logic;    -- /ddr_sdram_clock
-	signal sys_sdr_cke_q		: std_logic;    -- clock enable
-	signal sys_sdr_cs_qn		: std_logic;    -- /chip select
-	signal sys_sdr_ras_qn		: std_logic;    -- /ras
-	signal sys_sdr_cas_qn		: std_logic;    -- /cas
-	signal sys_sdr_we_qn		: std_logic;    -- /write enable
-	signal sys_sdr_dm_q			: unsigned(DDR_DM_WIDTH-1 downto 0);     -- data mask bits, set to "00"
-	signal sys_sdr_dqs_q		: unsigned(DDR_DQS_WIDTH-1 downto 0);    -- data strobe, only for write
-	signal sys_sdr_ba_q			: unsigned(DDR_BANK_WIDTH-1 downto 0);   -- bank select
-	signal sys_sdr_a_q			: unsigned(DDR_ADDR_WIDTH-1 downto 0);   -- address bus 
-	signal sys_sdr_data			: unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus
-
-	signal sys_error			: unsigned(1 downto 0); -- indicates DCM Errors
-	signal sys_sdr_clk_fb		: std_logic;
-
-	signal sys_usb_d			: unsigned(15 downto 0) := (others => '0');
-	signal sys_usb_a			: unsigned(1 downto 0);
-	signal sys_usb_csn			: std_logic;
-	signal sys_usb_wrn			: std_logic;
-	signal sys_usb_rdn			: std_logic;
-	signal sys_usb_rstn			: std_logic;
-	signal sys_usb_int			: std_logic := '0';
-	
-	signal sys_flash_ssram_d	: word_t;
-	signal sys_flash_ssram_a	: unsigned(24 downto 0);
-	signal sys_flash_ssram_we_n	: std_logic;
-	signal sys_flash_ssram_oe_n	: std_logic;
-
-	signal sys_flash_ce			: std_logic;
-	signal sys_flash_ac97_rstn	: std_logic;
-	signal sys_flash_byten		: std_logic;
-
-	signal sys_ssram_clk_fb		: std_logic;
-	signal sys_ssram_clk		: std_logic;
-	signal sys_ssram_cke_n		: std_logic;
-	signal sys_ssram_ce_n		: std_logic;
-	signal sys_ssram_bw_n		: unsigned(3 downto 0);
-	signal sys_ssram_dp			: unsigned(3 downto 0);
-	signal sys_ssram_adv		: std_logic;
-	signal sys_ssram_mode		: std_logic;
-	signal sys_ssram_zz			: std_logic;
-
-	SIGNAL sys_ac97_bit_clk		:  std_logic := '0';
-	SIGNAL sys_ac97_sdata_out	:  std_logic;
-	SIGNAL sys_ac97_ssync		:  std_logic;
-	SIGNAL sys_ac97_sdata_in	:  std_logic;
-
-	signal flash_reg			: word_t;
-
-	type flash_data_t is array (natural range 0 to 2**16-1) of word_t;
-	signal flash_data : flash_data_t;
-
-	signal	ac_frame_reg		: unsigned(255 downto 0) := (others => '0');
-	signal	ac_left				: unsigned(17 downto 0) := X"0000" & "00";
-	signal	ac_right			: unsigned(17 downto 0) := X"0000" & "01";
-	signal  ac_synced			:  std_logic;
-	
-BEGIN
-
-uut: entity work.mips_sys
---	GENERIC MAP
---	(
---		ddr_phaseshift => 90,
---		ddr_frequency_hz => 100E6
---	)
-	PORT MAP
-	(
-		sys_rst_n_in			=> sys_rst_n_in,
-		sys_clk_in				=> sys_clk_in,
-		sys_btn					=> btn,
-		sys_dip					=> dip,
-		sys_led					=> led,
-
-		sys_rx					=> sys_rx,
-		sys_tx					=> sys_tx,
-
-		sys_lcd_d				=> sys_lcd_d,
-		sys_lcd_e				=> sys_lcd_e,
-		sys_lcd_rs				=> sys_lcd_rs,
-		sys_lcd_rw				=> sys_lcd_rw,
-
-		sys_sdr_clk_p			=> sys_sdr_clk_p,
-		sys_sdr_clk_n			=> sys_sdr_clk_n,
-		sys_sdr_cke_q			=> sys_sdr_cke_q,
-		sys_sdr_clk_fb			=> sys_sdr_clk_fb,
-		sys_sdr_cs_qn			=> sys_sdr_cs_qn,
-		sys_sdr_ras_qn			=> sys_sdr_ras_qn,
-		sys_sdr_cas_qn			=> sys_sdr_cas_qn,
-		sys_sdr_we_qn			=> sys_sdr_we_qn,
-		sys_sdr_dm_q			=> sys_sdr_dm_q,
-		sys_sdr_dqs_q			=> sys_sdr_dqs_q,
-		sys_sdr_ba_q			=> sys_sdr_ba_q,
-		sys_sdr_a_q				=> sys_sdr_a_q,
-		sys_sdr_data			=> sys_sdr_data,
-
-		sys_usb_d				=> sys_usb_d,
-		sys_usb_a				=> sys_usb_a,
-		sys_usb_csn				=> sys_usb_csn,
-		sys_usb_wrn				=> sys_usb_wrn,
-		sys_usb_rdn				=> sys_usb_rdn,
-		sys_usb_rstn			=> sys_usb_rstn,
-		sys_usb_int				=> sys_usb_int,
-
-		sys_flash_ssram_d		=> sys_flash_ssram_d,
-		sys_flash_ssram_a		=> sys_flash_ssram_a,
-		sys_flash_ssram_we_n	=> sys_flash_ssram_we_n,
-		sys_flash_ssram_oe_n	=> sys_flash_ssram_oe_n,
-		sys_flash_ce			=> sys_flash_ce,
-		sys_flash_ac97_rstn		=> sys_flash_ac97_rstn,
-		sys_flash_byten			=> sys_flash_byten,
-
-		sys_ssram_clk_fb		=> sys_ssram_clk_fb,
-		sys_ssram_clk			=> sys_ssram_clk,
-		sys_ssram_cke_n			=> sys_ssram_cke_n,
-		sys_ssram_ce_n			=> sys_ssram_ce_n,
-		sys_ssram_bw_n			=> sys_ssram_bw_n,
-		sys_ssram_dp			=> sys_ssram_dp,
-		sys_ssram_adv			=> sys_ssram_adv,
-		sys_ssram_mode			=> sys_ssram_mode,
-		sys_ssram_zz			=> sys_ssram_zz,
-
-		sys_ac97_bit_clk		=> sys_ac97_bit_clk,
-		sys_ac97_sdata_out		=> sys_ac97_sdata_out,
-		sys_ac97_ssync			=> sys_ac97_ssync,
-		sys_ac97_sdata_in		=> sys_ac97_sdata_in,
-
-		sys_error 				=> sys_error
-	);
-
-inst_ssram : entity work.cy7c1354
-    PORT MAP 
-    (
-		Dq		=> STD_LOGIC_VECTOR(sys_flash_ssram_d),   	-- Data I/O
-		Dpq		=> STD_LOGIC_VECTOR(sys_ssram_dp),   	-- Data I/O
-		Addr	=> STD_LOGIC_VECTOR(sys_flash_ssram_a(18 downto 1)),   	-- Address
-		Mode	=> sys_ssram_mode, 	-- Burst Mode
-		Clk		=> sys_ssram_clk,      -- Clk
-		CEN_n	=> sys_ssram_cke_n,                                   -- CEN#
-		AdvLd_n	=> sys_ssram_adv,                                   -- Adv/Ld#
-		Bwa_n	=> sys_ssram_bw_n(0),                                   -- Bwa#
-		Bwb_n	=> sys_ssram_bw_n(1),                                   -- BWb#
-		Bwc_n	=> sys_ssram_bw_n(2),                                   -- Bwc#
-		Bwd_n	=> sys_ssram_bw_n(3),                                   -- BWd#
-		Rw_n	=> sys_flash_ssram_we_n,                                   -- RW#
-		Oe_n	=> sys_flash_ssram_oe_n,                                   -- OE#
-		Ce1_n	=> sys_ssram_ce_n,                                   -- CE1#
-		Ce2		=> '1',                                   -- CE2
-		Ce3_n	=> '0',                                   -- CE3#
-		Zz		=> sys_ssram_zz
-    );
-    
--- MICRON DDR SDRAM Simulation Model
-i_mt46v16m16_0 : entity work.mt46v16m16 
-      port map (
-         dq    => std_logic_vector(sys_sdr_data(15 downto 0)),
-         dqs   => std_logic_vector(sys_sdr_dqs_q(1 downto 0)),
-         addr  => std_logic_vector(sys_sdr_a_q),
-         ba    => std_logic_vector(sys_sdr_ba_q),
-         clk   => sys_sdr_clk_p,
-         clk_n => sys_sdr_clk_n,
-         cke   => sys_sdr_cke_q,
-         cs_n  => sys_sdr_cs_qn,
-         ras_n => sys_sdr_ras_qn,
-         cas_n => sys_sdr_cas_qn,
-         we_n  => sys_sdr_we_qn,
-         dm    => std_logic_vector(sys_sdr_dm_q(1 downto 0))
-         );
-
--- MICRON DDR SDRAM Simulation Model
-i_mt46v16m16_1 : entity work.mt46v16m16 
-      port map (
-         dq    => std_logic_vector(sys_sdr_data(31 downto 16)),
-         dqs   => std_logic_vector(sys_sdr_dqs_q(3 downto 2)),
-         addr  => std_logic_vector(sys_sdr_a_q),
-         ba    => std_logic_vector(sys_sdr_ba_q),
-         clk   => sys_sdr_clk_p,
-         clk_n => sys_sdr_clk_n,
-         cke   => sys_sdr_cke_q,
-         cs_n  => sys_sdr_cs_qn,
-         ras_n => sys_sdr_ras_qn,
-         cas_n => sys_sdr_cas_qn,
-         we_n  => sys_sdr_we_qn,
-         dm    => std_logic_vector(sys_sdr_dm_q(3 downto 2))
-         );
-
-	sys_sdr_clk_fb		<= sys_sdr_clk_p after 2300 ps;
-	sys_ssram_clk_fb	<= sys_ssram_clk after 0.5 ns;
-	
-	refresh <= true when falling_edge(sys_sdr_ras_qn) and falling_edge(sys_sdr_cas_qn) and sys_sdr_we_qn='1' else false;
-
-	sys_usb_d	<= X"1234" after 20 ns when sys_usb_csn = '0' and sys_usb_rdn = '0' else (others => 'Z') after 5 ns;
-	
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		sys_clk_in <= not sys_clk_in;
-	end process;
-
-
-	sys_ac97_sdata_in <= ac_frame_reg(ac_frame_reg'left); --sys_ac97_sdata_out;
-
-ac97_data_gen :
-	PROCESS(sys_ac97_bit_clk)
-	begin
-		if rising_edge(sys_ac97_bit_clk) then
-			ac_frame_reg <= ac_frame_reg(ac_frame_reg'left-1 downto 0) & '0';
-			if sys_flash_ac97_rstn = '0' then
-				ac_synced	<= '0';
-			elsif sys_ac97_ssync = '1' then
-				if ac_synced = '0' then
-					ac_frame_reg <= X"F800_00000_00000" & ac_left & "00" & ac_right & "00" & X"00000_00000_00000_00000_00000_00000_00000_00000";
-					ac_left <= ac_left + 2;
-					ac_right <= ac_right + 2;
-					ac_synced	<= '1';
-				end if;	
-			else	
-				ac_synced	<= '0';
-			end if;
-		end if;	
-	END PROCESS;
-
-ac97_clk_gen : PROCESS
-	begin
-		if (sys_flash_ac97_rstn = '0') then
-			sys_ac97_bit_clk <= '0';
-			wait until sys_flash_ac97_rstn = '1';
-			wait for 150 us;
-		end if;	
-		wait for AC97_CLK_PERIOD/2;
-		sys_ac97_bit_clk <= not sys_ac97_bit_clk;
-	END PROCESS;
-
-FLASH_READ: process(sys_rst_n_in, sys_flash_ce, sys_flash_ssram_oe_n, sys_flash_ssram_a)
-	type file_t is file of integer;
-	file load_flash : file_t open read_mode is "test_ac97.flash.bin";
-	variable instr : integer;
-	variable index : natural;
-	variable temp : signed(31 downto 0);
-	begin
-		if sys_rst_n_in = '0' then
-			index := 0;
-			while not endfile(load_flash) loop
-				read(load_flash, instr);
-				temp	:= to_signed(instr, word_t'length);
-				flash_data(index) <= unsigned(temp);
-				index := index + 1;
-			end loop;
-		else
-	 		sys_flash_ssram_d <= (others => 'Z') after 10 ns;
-			if sys_flash_ssram_oe_n = '0' and sys_flash_ce = '1' then
-				index := to_integer(sys_flash_ssram_a(24 downto 1));
-				sys_flash_ssram_d <= flash_data(index) after 10 ns;
-			end if;	
-		end if;	
-	end process;
-
-FLASH_WRITE: process(sys_flash_ce, sys_flash_ssram_we_n, sys_flash_ssram_d)
-	begin
-		if rising_edge(sys_flash_ssram_we_n) and sys_flash_ce = '1' then
-			flash_reg <= sys_flash_ssram_d;
-		end if;
-	end process;
-		
-STIMULUS: process
-
-	begin
-
-		wait for 3*CLK_PERIOD;
-		sys_rst_n_in <= '1';
-		wait for 200000*CLK_PERIOD;
-		
-		loop
-		wait for 251*CLK_PERIOD;
-		btn(4)		<= '1';			
-		wait for 311*CLK_PERIOD;
-		btn(4)		<= '0';			
-		end loop;
-		wait; 
-	
-	end process;
-	
-END;
diff --git a/projects/mips_sys/tools/insrom.rb b/projects/mips_sys/tools/insrom.rb
deleted file mode 100644
index fdbf1ed..0000000
--- a/projects/mips_sys/tools/insrom.rb
+++ /dev/null
@@ -1,46 +0,0 @@
-#!/usr/bin/env ruby
-
-# ----------------------------------------------------------------------
-# Project: JIPS, a portable 32-bit RISC CPU written in VHDL
-# This file: Insertion of code fragments into templates
-#
-# Copyright (C) 2008 J. Ahrensfeld
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-# 
-# For questions and ideas, please contact the author at jens@jayfield.org
-#
-# ---------------------------------------------------------------------
-
-arg = $*
-rom_filename = arg[0].to_s
-tpl_filename = arg[1].to_s
-
-subst_pattern = "ROM_INSERT_HERE"
-
-# --------------------------------------------------------
-# Open file
-# --------------------------------------------------------
-romfile = File.open(rom_filename, "r")
-tplfile = File.open(tpl_filename, "r")
-re = Regexp.new(subst_pattern)
-
-while (line = tplfile.gets)
-	puts line
-	line.scan(re).each do |word|
-		romfile.each do |raw_line|
-			puts raw_line
-		end	
-	end
-end
diff --git a/projects/mips_sys/tools/irom.vhd.tpl b/projects/mips_sys/tools/irom.vhd.tpl
deleted file mode 100644
index 5ffd6d7..0000000
--- a/projects/mips_sys/tools/irom.vhd.tpl
+++ /dev/null
@@ -1,29 +0,0 @@
--------------------------------------------------------------------------
--- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2008 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
--- ROM_INSERT_HERE
-
diff --git a/projects/mips_sys/tools/irom_ld.vhd.tpl b/projects/mips_sys/tools/irom_ld.vhd.tpl
deleted file mode 100644
index 3bd3afb..0000000
--- a/projects/mips_sys/tools/irom_ld.vhd.tpl
+++ /dev/null
@@ -1,147 +0,0 @@
--------------------------------------------------------------------------
--- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
--- This file: loadable ROM
---
--- Copyright (C) 2008 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-ENTITY irom IS
-	Port (
-		clk			: in  STD_LOGIC;
-		addr		: in  inst_addr_t;
-		dout		: out inst_t
-	);
-	
-END irom;
-
-ARCHITECTURE loadable OF irom IS 
-
-	-- JASM_ROM_INSERT_HERE
-
-	signal jtag_ld_clk		: STD_LOGIC;
-	signal jtag_ld_we		: STD_LOGIC;
-	signal jtag_ld_addr		: unsigned (15 downto 0);
-	signal jtag_ld_dout		: unsigned (31 downto 0);
-	signal jtag_ld_din		: unsigned (31 downto 0);
-	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
-	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
-	signal user_regi, user_rego : unsigned (47 downto 0);
-	constant id : unsigned (47 downto 0) := X"DEAD" & X"BEEF" & "X"BABE";
-
-begin
-
---------------------------------------------------------------------------
--- Virtex-4: JTAG Loader
---------------------------------------------------------------------------
-	i00_BUFG : BUFG
-	port map
-	(
-		O => bs_clk1,
-        I => bs_clk0
-	);
-	
-	i01_BUFG : BUFG
-	port map
-	(
-		O => bs_update1,
-        I => bs_update0
-	);
-
-	BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 
-	generic map
-	(
-		JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
-	)
-	port map 
-	(
-		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
-		DRCK => bs_clk0,       -- Data register output for USER functions
-		RESET => bs_rst,       -- Reset output from TAP controller
-		SEL => bs_sel,         -- USER active output
-		SHIFT => bs_shift,     -- SHIFT output from TAP controller
-		TDI => bs_tdi,        -- TDI output from TAP controller
-		UPDATE => bs_update0,   -- UPDATE output from TAP controller
-		TDO => bs_tdo         -- Data input for USER function
-	);
-
-	jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);
-	jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);
-	jtag_ld_clk <= bs_update1;
-	jtag_ld_we <= bs_sel;
-	
-sipo:
-	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
-	begin
-		if bs_rst = '1' then
-			user_regi <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
-			end if;
-		end if;
-	end process;	
-
-piso:
-	process (bs_rst, bs_clk1, bs_shift, user_rego)
-	begin
-		bs_tdo <= user_rego(0);
-		if bs_rst = '1' then
-			user_rego <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
-			else
-				user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;	
---				user_rego <= id;	
-			end if;
-		end if;
-	end process;	
-	
-PROM_WRITE: 
-	process(jtag_ld_clk, jtag_ld_we)
-	begin
-		if rising_edge(jtag_ld_clk) then
-			if jtag_ld_we = '1' then
-				imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
-			else	
-				jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
-			end if;
-		end if;	
-	end process;
-
---------------------------------------------------------------------------
--- ROM Read/Write
---------------------------------------------------------------------------
-PROM_READ: 
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			dout <= imem_rom(to_integer(addr));
-		end if;
-	end process;
-
---------------------------------------------------------------------------
-end loadable;
diff --git a/projects/mips_sys/tools/make b/projects/mips_sys/tools/make
deleted file mode 100644
index e7f598f..0000000
--- a/projects/mips_sys/tools/make
+++ /dev/null
@@ -1,50 +0,0 @@
-#!/bin/sh
-
-# ----------------------------------------------------------------------
-# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-# This file: rom-file generation for cpu_core
-#
-# Copyright (C) 2007 J. Ahrensfeld
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-# 
-# For questions and ideas, please contact the author at jens@jayfield.org
-#
-# ---------------------------------------------------------------------
-
-TARGET=$2
-DSTDIR=$1
-
-JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools
-
-$JASM_HOME/jasm.rb $TARGET.jsm
-
-irom_tcl_snippet="$TARGET.irom.tcl.snip"
-irom_vhdl_snippet="$TARGET.irom.vhdl.snip"
-irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip"
-xrom_tcl_snippet="$TARGET.xrom.tcl.snip"
-xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip"
-xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip"
-
-$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl
-$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl
-
-$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl
-$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl
-
-cat $irom_tcl_snippet > $TARGET.tcl.snip.snip
-cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip
-$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl
-
-rm -f *.snip
diff --git a/projects/mips_sys/tools/rom.tcl.tpl b/projects/mips_sys/tools/rom.tcl.tpl
deleted file mode 100644
index 9f5c0dc..0000000
--- a/projects/mips_sys/tools/rom.tcl.tpl
+++ /dev/null
@@ -1,61 +0,0 @@
-# ----------------------------------------------------------------------
-# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-# This file: The ROM file for upload to target over JTAG 
-#
-# Copyright (C) 2007 J. Ahrensfeld
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-# 
-# For questions and ideas, please contact the author at jens@jayfield.org
-#
-# ---------------------------------------------------------------------
-
-# ---------------------------------------------------------------------
-# For Chipscope 9.1
-# ---------------------------------------------------------------------
-# Source JTAG/TCL frame work
-cd $env(CHIPSCOPE)\\bin\\nt
-source csejtag.tcl
-
-namespace import ::chipscope::*
-
-# Platform USB Cable
-set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
-# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
-
-# Create session
-set handle [::chipscope::csejtag_session create 0]
-
-# Open JTAG and lock
-set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
-set lock_result [::chipscope::csejtag_target lock $handle 1000]
-
-set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
-
-# Get Device ID
-set devtype "Virtex-4SX"
-set devid 2
-set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
-set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
-
-set CSE_OP $CSEJTAG_SHIFT_READWRITE
-set CSE_ES $CSEJTAG_RUN_TEST_IDLE
-
-# Write Program
-# JASM_ROM_INSERT_HERE
-
-::chipscope::csejtag_target unlock $handle
-::chipscope::csejtag_target close $handle
-::chipscope::csejtag_session destroy $handle
-exit
diff --git a/projects/mips_sys/tools/src/flashgen.c b/projects/mips_sys/tools/src/flashgen.c
deleted file mode 100644
index 4b75814..0000000
--- a/projects/mips_sys/tools/src/flashgen.c
+++ /dev/null
@@ -1,117 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
-
-#define INT8    char
-#define INT16   short
-#define INT32   long
-#define UINT8   unsigned char
-#define UINT16  unsigned short
-#define UINT32  unsigned long
-#define INT     int
-#define UINT    unsigned int
-#define FLOAT32 float
-#define FLOAT64 double
-
-#define SDRAM_BASE			0x40000000
-#define	FLASH_OFFSET		0x00000000
-
-// --------------------------------------------------------------
-typedef struct _sflash_img_hdr_t
-{
-	UINT8 magic[4];
-	UINT32 target_addr;
-	UINT32 img_offset;
-	UINT32 img_size;
-	UINT32 hdr_next;
-	UINT8 img_name[128];
-	UINT8 res[108];
-
-} flash_img_hdr_t;
-
-// --------------------------------------------------------------
-void basename(char *pSrc, char *pDst)
-{
-	int i, size;
-
-	size = strlen(pSrc);
-
-	while(pSrc[size] != '.')
-		size--;
-
-	for (i=0; i < size; i++)
-		pDst[i] = pSrc[i];
-
-	pDst[i] = 0;
-
-}
-
-// --------------------------------------------------------------
-int main(int argc, char *argv[])
-{
-	char *pFilenameIn;
-	char name_flash[1024];
-	char name_prj[1024];
-	char *pBuf;
-	flash_img_hdr_t img_hdr = {0};
-
-	FILE *pFile;
-	int filesize;
-	long start, end;
-	int i;
-
-	if (argc < 2)
-	{
-		fprintf(stderr, "Usage: flashgen <input file>\n");
-		return 1;
-	}
-
-	pFilenameIn = argv[1];
-	pFile = fopen(pFilenameIn, "rb");
-	if (!pFile)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
-		return 1;
-	}
-
-	basename(pFilenameIn, name_prj);
-	sprintf(name_flash, "%s.flash.bin", name_prj);
-
-	// determine filesize
-	fseek(pFile, 0, SEEK_SET);
-	start = ftell(pFile);
-	fseek(pFile, 0, SEEK_END);
-	end = ftell(pFile);
-	fseek(pFile, 0, SEEK_SET);
-	filesize = (end-start);
-
-	pBuf = (char*)malloc(filesize);
-	fread(pBuf, 1, filesize, pFile);
-
-	fclose(pFile);
-
-	pFile = fopen(name_flash, "wb");
-	if (!pFile)
-	{
-		fprintf(stderr, "Error opening file %s\n", name_flash);
-		return 1;
-	}
-
-	img_hdr.magic[0] = 'J';
-	img_hdr.magic[1] = 'F';
-	img_hdr.magic[2] = 'I';
-	img_hdr.magic[3] = '1';
-	img_hdr.target_addr = SDRAM_BASE;
-	img_hdr.img_size = filesize;
-	img_hdr.img_offset = FLASH_OFFSET + sizeof(flash_img_hdr_t);
-	img_hdr.hdr_next = FLASH_OFFSET;
-
-	fwrite(&img_hdr, sizeof(flash_img_hdr_t), 1, pFile);
-	fwrite(pBuf, 1, filesize, pFile);
-
-	fclose(pFile);
-
-	return 0;
-}
-
diff --git a/projects/mips_sys/tools/src/ramgen.c b/projects/mips_sys/tools/src/ramgen.c
deleted file mode 100644
index 8f61118..0000000
--- a/projects/mips_sys/tools/src/ramgen.c
+++ /dev/null
@@ -1,385 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
-
-#define ARCH_NAME			"data"
-#define ENT_NAME			"ram"
-#define JTAG_ADDR_WIDTH		16
-
-// --------------------------------------------------------------
-void basename(char *pSrc, char *pDst)
-{
-	int i, size;
-
-	size = strlen(pSrc);
-
-	while(pSrc[size] != '.')
-		size--;
-
-	for (i=0; i < size; i++)
-		pDst[i] = pSrc[i];
-
-	pDst[i] = 0;
-
-}
-
-int SaveRAM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
-{
-	FILE *pFileIn, *pFileOut;
-	long start, end;
-	int i, word, filesize, romsize;
-
-	pFileIn = fopen(pFilenameIn, "rb");
-	if (!pFileIn)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
-		return 1;
-	}
-
-	pFileOut = fopen(pFilenameOut, "wb");
-	if (!pFileOut)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
-		return 1;
-	}
-
-	fseek(pFileIn, 0, SEEK_SET);
-	start = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_END);
-	end = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_SET);
-
-	filesize = (end-start);
-	romsize = (int)pow(2, nbits_addr+2);
-
-	// -------------------------------------------------------------------------
-	// Header
-
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "LIBRARY IEEE;\n");
-	fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
-	fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
-	fprintf(pFileOut, "\tPort\n");
-	fprintf(pFileOut, "\t(\n");
-	fprintf(pFileOut, "\t\tclk\t\t: in  STD_LOGIC;\n");
-	fprintf(pFileOut, "\t\tce\t\t: in  STD_LOGIC;\n");
-	fprintf(pFileOut, "\t\twe\t\t: in  unsigned(%d downto 0);\n", nbits_data/8-1);
-	fprintf(pFileOut, "\t\taddr\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\t\tdin\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
-	fprintf(pFileOut, "\t);\n");
-	fprintf(pFileOut, "END %s;\n", ENT_NAME);
-	fprintf(pFileOut, "\n");
-
-
-	fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "\tconstant depth : natural := %d;\n", romsize/4);
-	fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
-
-	fprintf(pFileOut, "\tsignal sram : word_array_t :=\n");
-	fprintf(pFileOut, "\t(\n");
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// ROM part
-	// -------------------------------------------------------------------------
-	for (i=0; i < filesize; i += sizeof(int))
-	{
-		fread(&word, 1, sizeof(int), pFileIn);
-		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
-		if (i < (romsize-sizeof(int)))
-			fprintf(pFileOut, ", -- %8.8X\n", i);
-		else
-			fprintf(pFileOut, "  -- %8.8X\n", i);
-	}
-	word = 0;
-	for (; i < romsize; i += sizeof(int))
-	{
-		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
-		if (i < (romsize-sizeof(int)))
-			fprintf(pFileOut, ", -- %8.8X\n", i);
-		else
-			fprintf(pFileOut, "  -- %8.8X\n", i);
-	}
-	fprintf(pFileOut, "\t);\n");
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// Trailer
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "begin\n", ARCH_NAME);
-	fprintf(pFileOut, "\n");
-	fprintf(pFileOut, "RAM_RW:\n", ARCH_NAME);
-	fprintf(pFileOut, "\tprocess(clk)\n");
-	fprintf(pFileOut, "\tvariable index : natural range 0 to depth-1;\n");
-	fprintf(pFileOut, "\tbegin\n");
-	fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
-	fprintf(pFileOut, "\t\t\tindex := to_integer(addr(%d downto 2));\n", nbits_addr+1);
-	fprintf(pFileOut, "\t\t\tif we(0) = '1' then\n");
-	fprintf(pFileOut, "\t\t\t\tsram(index)(7 downto 0)\t\t<= din(7 downto 0);\n");
-	fprintf(pFileOut, "\t\t\tend if;\n");
-	fprintf(pFileOut, "\t\t\tif we(1) = '1' then\n");
-	fprintf(pFileOut, "\t\t\t\tsram(index)(15 downto 8)\t<= din(15 downto 8);\n");
-	fprintf(pFileOut, "\t\t\tend if;\n");
-	fprintf(pFileOut, "\t\t\tif we(2) = '1' then\n");
-	fprintf(pFileOut, "\t\t\t\tsram(index)(23 downto 16)\t<= din(23 downto 16);\n");
-	fprintf(pFileOut, "\t\t\tend if;\n");
-	fprintf(pFileOut, "\t\t\tif we(3) = '1' then\n");
-	fprintf(pFileOut, "\t\t\t\tsram(index)(31 downto 24)\t\t<= din(31 downto 24);\n");
-	fprintf(pFileOut, "\t\t\tend if;\n");
-	fprintf(pFileOut, "\t\t\tdout <= sram(index);\n");
-	fprintf(pFileOut, "\t\tend if;\n");
-	fprintf(pFileOut, "\tend process;\n");
-	fprintf(pFileOut, "\n");
-	fprintf(pFileOut, "end %s;\n", ARCH_NAME);
-
-	return 0;
-}
-
-int SaveRAM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
-{
-	FILE *pFileIn, *pFileOut;
-	long start, end;
-	int i, word, filesize, romsize;
-
-	char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n        I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n        I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0,       -- Data register output for USER functions\n\t\tRESET => bs_rst,       -- Reset output from TAP controller\n\t\tSEL => bs_sel,         -- USER active output\n\t\tSHIFT => bs_shift,     -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi,        -- TDI output from TAP controller\n\t\tUPDATE => bs_update0,   -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo         -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
-
-	pFileIn = fopen(pFilenameIn, "rb");
-	if (!pFileIn)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
-		return 1;
-	}
-
-	pFileOut = fopen(pFilenameOut, "wb");
-	if (!pFileOut)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
-		return 1;
-	}
-
-	fseek(pFileIn, 0, SEEK_SET);
-	start = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_END);
-	end = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_SET);
-
-	filesize = (end-start);
-	romsize = (int)pow(2, nbits_addr+2);
-
-	// -------------------------------------------------------------------------
-	// Header
-
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "LIBRARY IEEE;\n");
-	fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
-	fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "library UNISIM;\n");
-	fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
-	fprintf(pFileOut, "\tPort\n");
-	fprintf(pFileOut, "\t(\n");
-	fprintf(pFileOut, "\t\tclk\t\t: in  STD_LOGIC;\n");
-	fprintf(pFileOut, "\t\tce\t\t: in  STD_LOGIC;\n");
-	fprintf(pFileOut, "\t\taddr\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
-	fprintf(pFileOut, "\t);\n");
-	fprintf(pFileOut, "END %s;\n", ENT_NAME);
-	fprintf(pFileOut, "\n");
-
-
-	fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
-
-	fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
-	fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
-	fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
-	fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
-	fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
-	fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
-	fprintf(pFileOut, "\t(\n");
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// ROM part
-	// -------------------------------------------------------------------------
-	for (i=0; i < filesize; i += sizeof(int))
-	{
-		fread(&word, 1, sizeof(int), pFileIn);
-		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
-		if (i < (romsize-sizeof(int)))
-			fprintf(pFileOut, ", -- %8.8X\n", i);
-		else
-			fprintf(pFileOut, "  -- %8.8X\n", i);
-	}
-	word = 0;
-	for (; i < romsize; i += sizeof(int))
-	{
-		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
-		if (i < (romsize-sizeof(int)))
-			fprintf(pFileOut, ", -- %8.8X\n", i);
-		else
-			fprintf(pFileOut, "  -- %8.8X\n", i);
-	}
-	fprintf(pFileOut, "\t);\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "begin\n", ARCH_NAME);
-
-	fprintf(pFileOut, "\n");
-	fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
-	fprintf(pFileOut, "\tprocess(clk)\n");
-	fprintf(pFileOut, "\tbegin\n");
-	fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
-	fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
-	fprintf(pFileOut, "\t\tend if;\n");
-	fprintf(pFileOut, "\tend process;\n");
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// Trailer
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "\n");
-	fputs(tpl, pFileOut);
-
-	fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
-	fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
-	fprintf(pFileOut, "\tbegin\n");
-	fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
-	fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
-	fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
-	fprintf(pFileOut, "\t\t\telse\n");
-	fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
-	fprintf(pFileOut, "\t\t\tend if;\n");
-	fprintf(pFileOut, "\t\tend if;\n");
-	fprintf(pFileOut, "\tend process;\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "end %s;\n", ARCH_NAME);
-	return 0;
-}
-
-int SaveRAM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
-{
-	FILE *pFileIn, *pFileOut;
-	long start, end;
-	int i, word, word_addr, filesize, romsize;
-	char binstr_addr[33];
-	char binstr_data[33];
-
-	char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
-
-	pFileIn = fopen(pFilenameIn, "rb");
-	if (!pFileIn)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
-		return 1;
-	}
-
-	pFileOut = fopen(pFilenameOut, "wb");
-	if (!pFileOut)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
-		return 1;
-	}
-
-	fseek(pFileIn, 0, SEEK_SET);
-	start = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_END);
-	end = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_SET);
-
-	filesize = (end-start);
-	romsize = (int)pow(2, nbits_addr+2);
-
-	// -------------------------------------------------------------------------
-	// Header
-
-	// -------------------------------------------------------------------------
-	fputs(tpl, pFileOut);
-
-	// -------------------------------------------------------------------------
-	// ROM part
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
-	fprintf(pFileOut, "# ---------------------------------------------------------------\n");
-	fprintf(pFileOut, "# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA\n");
-	fprintf(pFileOut, "# User 2\n");
-	fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n");
-
-	word_addr = 0;
-	for (i=0; i < filesize; i += sizeof(int))
-	{
-		fread(&word, 1, sizeof(int), pFileIn);
-		fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
-		word_addr++;
-	}
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// Trailer
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
-	fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
-	fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
-	fprintf(pFileOut, "exit\n");
-
-	return 0;
-}
-
-int main(int argc, char *argv[])
-{
-	char *pFilenameIn;
-	char name_prj[1024];
-	char name_rom_tcl[1024];
-	char name_rom[1024];
-	char name_rom_v4ld[1024];
-
-	FILE *pFileIn;
-	int filesize, romsize, nbits_addr, nbits_data;
-	long start, end;
-	int word, i;
-
-	if (argc < 2)
-	{
-		fprintf(stderr, "Usage: ramgen <input file> <num. word address bits>\n");
-		return 1;
-	}
-
-	pFilenameIn = argv[1];
-	if (argc == 3)
-		nbits_addr = atoi(argv[2]);
-
-
-	basename(pFilenameIn, name_prj);
-	sprintf(name_rom, "%s.vhd", name_prj);
-	sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
-	sprintf(name_rom_tcl, "%s.tcl", name_prj);
-
-	SaveRAM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
-//	SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
-	SaveRAM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
-
-
-	return 0;
-}
-
diff --git a/projects/mips_sys/tools/src/romgen.c b/projects/mips_sys/tools/src/romgen.c
deleted file mode 100644
index a59e705..0000000
--- a/projects/mips_sys/tools/src/romgen.c
+++ /dev/null
@@ -1,368 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
-
-#define ARCH_NAME			"data"
-#define ENT_NAME			"rom"
-#define JTAG_ADDR_WIDTH		16
-
-// --------------------------------------------------------------
-void basename(char *pSrc, char *pDst)
-{
-	int i, size;
-
-	size = strlen(pSrc);
-
-	while(pSrc[size] != '.')
-		size--;
-
-	for (i=0; i < size; i++)
-		pDst[i] = pSrc[i];
-
-	pDst[i] = 0;
-
-}
-
-int SaveROM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
-{
-	FILE *pFileIn, *pFileOut;
-	long start, end;
-	int i, word, filesize, romsize;
-
-	pFileIn = fopen(pFilenameIn, "rb");
-	if (!pFileIn)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
-		return 1;
-	}
-
-	pFileOut = fopen(pFilenameOut, "wb");
-	if (!pFileOut)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
-		return 1;
-	}
-
-	fseek(pFileIn, 0, SEEK_SET);
-	start = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_END);
-	end = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_SET);
-
-	filesize = (end-start);
-	romsize = (int)pow(2, nbits_addr+2);
-
-	// -------------------------------------------------------------------------
-	// Header
-
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "LIBRARY IEEE;\n");
-	fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
-	fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
-	fprintf(pFileOut, "\tPort\n");
-	fprintf(pFileOut, "\t(\n");
-	fprintf(pFileOut, "\t\tclk\t\t: in  STD_LOGIC;\n");
-	fprintf(pFileOut, "\t\tce\t\t: in  STD_LOGIC;\n");
-	fprintf(pFileOut, "\t\taddr\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
-	fprintf(pFileOut, "\t);\n");
-	fprintf(pFileOut, "END %s;\n", ENT_NAME);
-	fprintf(pFileOut, "\n");
-
-
-	fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
-
-	fprintf(pFileOut, "\tconstant word_array : word_array_t :=\n");
-	fprintf(pFileOut, "\t(\n");
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// ROM part
-	// -------------------------------------------------------------------------
-	for (i=0; i < filesize; i += sizeof(int))
-	{
-		fread(&word, 1, sizeof(int), pFileIn);
-		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
-		if (i < (romsize-sizeof(int)))
-			fprintf(pFileOut, ", -- %8.8X\n", i);
-		else
-			fprintf(pFileOut, "  -- %8.8X\n", i);
-	}
-	word = 0;
-	for (; i < romsize; i += sizeof(int))
-	{
-		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
-		if (i < (romsize-sizeof(int)))
-			fprintf(pFileOut, ", -- %8.8X\n", i);
-		else
-			fprintf(pFileOut, "  -- %8.8X\n", i);
-	}
-	fprintf(pFileOut, "\t);\n");
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// Trailer
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "begin\n", ARCH_NAME);
-	fprintf(pFileOut, "\n");
-	fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
-	fprintf(pFileOut, "\tprocess(clk)\n");
-	fprintf(pFileOut, "\tbegin\n");
-	fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
-	fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
-	fprintf(pFileOut, "\t\tend if;\n");
-	fprintf(pFileOut, "\tend process;\n");
-	fprintf(pFileOut, "\n");
-	fprintf(pFileOut, "end %s;\n", ARCH_NAME);
-
-	return 0;
-}
-
-int SaveROM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
-{
-	FILE *pFileIn, *pFileOut;
-	long start, end;
-	int i, word, filesize, romsize;
-
-	char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n        I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n        I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0,       -- Data register output for USER functions\n\t\tRESET => bs_rst,       -- Reset output from TAP controller\n\t\tSEL => bs_sel,         -- USER active output\n\t\tSHIFT => bs_shift,     -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi,        -- TDI output from TAP controller\n\t\tUPDATE => bs_update0,   -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo         -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
-
-	pFileIn = fopen(pFilenameIn, "rb");
-	if (!pFileIn)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
-		return 1;
-	}
-
-	pFileOut = fopen(pFilenameOut, "wb");
-	if (!pFileOut)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
-		return 1;
-	}
-
-	fseek(pFileIn, 0, SEEK_SET);
-	start = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_END);
-	end = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_SET);
-
-	filesize = (end-start);
-	romsize = (int)pow(2, nbits_addr+2);
-
-	// -------------------------------------------------------------------------
-	// Header
-
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "LIBRARY IEEE;\n");
-	fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
-	fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "library UNISIM;\n");
-	fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
-	fprintf(pFileOut, "\tPort\n");
-	fprintf(pFileOut, "\t(\n");
-	fprintf(pFileOut, "\t\tclk\t\t: in  STD_LOGIC;\n");
-	fprintf(pFileOut, "\t\tce\t\t: in  STD_LOGIC;\n");
-	fprintf(pFileOut, "\t\taddr\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
-	fprintf(pFileOut, "\t);\n");
-	fprintf(pFileOut, "END %s;\n", ENT_NAME);
-	fprintf(pFileOut, "\n");
-
-
-	fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
-
-	fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
-	fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
-	fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
-	fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
-	fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
-	fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
-	fprintf(pFileOut, "\t(\n");
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// ROM part
-	// -------------------------------------------------------------------------
-	for (i=0; i < filesize; i += sizeof(int))
-	{
-		fread(&word, 1, sizeof(int), pFileIn);
-		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
-		if (i < (romsize-sizeof(int)))
-			fprintf(pFileOut, ", -- %8.8X\n", i);
-		else
-			fprintf(pFileOut, "  -- %8.8X\n", i);
-	}
-	word = 0;
-	for (; i < romsize; i += sizeof(int))
-	{
-		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
-		if (i < (romsize-sizeof(int)))
-			fprintf(pFileOut, ", -- %8.8X\n", i);
-		else
-			fprintf(pFileOut, "  -- %8.8X\n", i);
-	}
-	fprintf(pFileOut, "\t);\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "begin\n", ARCH_NAME);
-
-	fprintf(pFileOut, "\n");
-	fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
-	fprintf(pFileOut, "\tprocess(clk)\n");
-	fprintf(pFileOut, "\tbegin\n");
-	fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
-	fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
-	fprintf(pFileOut, "\t\tend if;\n");
-	fprintf(pFileOut, "\tend process;\n");
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// Trailer
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "\n");
-	fputs(tpl, pFileOut);
-
-	fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
-	fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
-	fprintf(pFileOut, "\tbegin\n");
-	fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
-	fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
-	fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
-	fprintf(pFileOut, "\t\t\telse\n");
-	fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
-	fprintf(pFileOut, "\t\t\tend if;\n");
-	fprintf(pFileOut, "\t\tend if;\n");
-	fprintf(pFileOut, "\tend process;\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "end %s;\n", ARCH_NAME);
-	return 0;
-}
-
-int SaveROM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
-{
-	FILE *pFileIn, *pFileOut;
-	long start, end;
-	int i, word, word_addr, filesize, romsize;
-	char binstr_addr[33];
-	char binstr_data[33];
-
-	char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
-
-	pFileIn = fopen(pFilenameIn, "rb");
-	if (!pFileIn)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
-		return 1;
-	}
-
-	pFileOut = fopen(pFilenameOut, "wb");
-	if (!pFileOut)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
-		return 1;
-	}
-
-	fseek(pFileIn, 0, SEEK_SET);
-	start = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_END);
-	end = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_SET);
-
-	filesize = (end-start);
-	romsize = (int)pow(2, nbits_addr+2);
-
-	// -------------------------------------------------------------------------
-	// Header
-
-	// -------------------------------------------------------------------------
-	fputs(tpl, pFileOut);
-
-	// -------------------------------------------------------------------------
-	// ROM part
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
-	fprintf(pFileOut, "# ---------------------------------------------------------------\n");
-	fprintf(pFileOut, "# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA\n");
-	fprintf(pFileOut, "# User 1\n");
-	fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n");
-
-	word_addr = 0;
-	for (i=0; i < filesize; i += sizeof(int))
-	{
-		fread(&word, 1, sizeof(int), pFileIn);
-		fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
-		word_addr++;
-	}
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// Trailer
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
-	fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
-	fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
-	fprintf(pFileOut, "exit\n");
-
-	return 0;
-}
-
-int main(int argc, char *argv[])
-{
-	char *pFilenameIn;
-	char name_prj[1024];
-	char name_rom[1024];
-	char name_rom_v4ld[1024];
-	char name_rom_tcl[1024];
-
-	FILE *pFileIn;
-	int filesize, romsize, nbits_addr, nbits_data;
-	long start, end;
-	int word, i;
-
-	if (argc < 2)
-	{
-		fprintf(stderr, "Usage: romgen <input file> <num. word address bits>\n");
-		return 1;
-	}
-
-	pFilenameIn = argv[1];
-	if (argc == 3)
-		nbits_addr = atoi(argv[2]);
-
-
-	basename(pFilenameIn, name_prj);
-	sprintf(name_rom, "%s.vhd", name_prj);
-	sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
-	sprintf(name_rom_tcl, "%s.tcl", name_prj);
-
-	SaveROM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
-	SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
-	SaveROM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
-
-
-	return 0;
-}
-