diff --git a/lib/emac/src/sipo.vhd b/lib/emac/src/sipo.vhd
index 19c91c4..044b91a 100644
--- a/lib/emac/src/sipo.vhd
+++ b/lib/emac/src/sipo.vhd
@@ -60,7 +60,7 @@ end process;
 process(clk)
 begin
 	if rising_edge(clk) then
-		din_vld_r	<= din_vld;
+		din_vld_r	<= din_vld and din_en;
 		if rst = '1' then
 			out_en <= '0';
 		elsif out_en = '0' then	
@@ -87,15 +87,15 @@ begin
 	if rising_edge(clk) then
 		if rst = '1' or pre_fin = '1' then
 			if (msb_first) then
-				shift_cnt_pipe	<= (shift_cnt_pipe'left downto 1 => '0') & din_vld;
+				shift_cnt_pipe	<= (shift_cnt_pipe'left downto 1 => '0') & (din_en and din_vld);
 			else
-				shift_cnt_pipe	<= din_vld & (shift_cnt_pipe'left downto 1 => '0');
+				shift_cnt_pipe	<= (din_en and din_vld) & (shift_cnt_pipe'left downto 1 => '0');
 			end if;
 		elsif din_vld = '1' or abort = '1' then
 			if (msb_first) then
-				shift_cnt_pipe	<= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0)  & din_vld;
+				shift_cnt_pipe	<= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0)  & din_en;
 			else
-				shift_cnt_pipe	<= din_vld & shift_cnt_pipe(shift_cnt_pipe'left downto 1);
+				shift_cnt_pipe	<= din_en & shift_cnt_pipe(shift_cnt_pipe'left downto 1);
 			end if;
 		end if;
 	end if;
@@ -104,7 +104,7 @@ end process;
 process(clk)
 begin
 	if rising_edge(clk) then
-		if din_vld = '1' or abort = '1' then
+		if (din_en and din_vld) = '1' or abort = '1' then
 			if (msb_first) then
 				shift_pipe		<= shift_pipe(shift_pipe'left-data_width_in downto 0) & din;
 			else