diff --git a/lib/CPUs/MIPS/ghdl/tb_mips_top.make b/lib/CPUs/MIPS/ghdl/tb_mips_top.make
index 0caa4b8..f9f52f1 100644
--- a/lib/CPUs/MIPS/ghdl/tb_mips_top.make
+++ b/lib/CPUs/MIPS/ghdl/tb_mips_top.make
@@ -16,18 +16,18 @@ SRCS += ../../../uart/src/sim/uart.vhd
 SRCS += ../../../uart/src/uart_wb.vhd
 
 # GPIO
-SRCS += ../../../misc/gpio_wb.vhd
+SRCS += ../../../JBUS/gpio/src/gpio_wb.vhd
 
 # Async port
-SRCS += ../../../misc/async_types.vhd
-SRCS += ../../../misc/async_port_wb.vhd
+SRCS += ../../../JBUS/async_port/src/async_types.vhd
+SRCS += ../../../JBUS/async_port/src/async_port_wb.vhd
 SRCS += ../src/async_defs.vhd
 
 # ROM
 #SRCS += Z:/work/repos/mips/src/bootloader/build/ml402/eb/bootloader.elf.ROM.vhd
 #SRCS += Z:/work/repos/mips/src/bootloader/build/denano/eb/bootloader.elf.ROM.vhd
 SRCS += ../src/bootloader_flash.ROM.vhd
-SRCS += ../../../misc/rom_wb.vhd
+SRCS += ../../../JBUS/memory/src/rom_wb.vhd
 
 # MIPS
 SRCS += $(MIPS_CORE_SRCS)
diff --git a/lib/JBUS/busmaster/ghdl/tb_busmaster_async.make b/lib/JBUS/busmaster/ghdl/tb_busmaster_async.make
index 0190889..93cba06 100644
--- a/lib/JBUS/busmaster/ghdl/tb_busmaster_async.make
+++ b/lib/JBUS/busmaster/ghdl/tb_busmaster_async.make
@@ -1,14 +1,14 @@
-include ../../../lib/FIFO/ghdl/fifo_async.inc
+include ../../../../lib/FIFO/ghdl/fifo_async.inc
 
-ROOT_PATH := ../../..
+ROOT_PATH := ../../../..
 LIB_PATH := $(ROOT_PATH)/lib
-MOD_PATH := $(LIB_PATH)/JBUS
+MOD_PATH := $(LIB_PATH)/JBUS/busmaster
 
 SRCS += $(LIB_PATH)/misc/utils_pkg.vhd
 SRCS += $(FIFO_ASYNC_SRCS)
-SRCS += $(MOD_PATH)/src/busmaster/busmaster_types.vhd
-SRCS += $(MOD_PATH)/src/busmaster/busmaster_async.vhd
-SRCS += $(MOD_PATH)/src/busmaster/tb_busmaster_async.vhd
+SRCS += $(MOD_PATH)/src/busmaster_types.vhd
+SRCS += $(MOD_PATH)/src/busmaster_async.vhd
+SRCS += $(MOD_PATH)/src/tb_busmaster_async.vhd
 
 # Compile
 TARGET := tb_busmaster_async
diff --git a/lib/JBUS/busmaster/ghdl/tb_busmaster_sync.make b/lib/JBUS/busmaster/ghdl/tb_busmaster_sync.make
index fbbecb9..1695d29 100644
--- a/lib/JBUS/busmaster/ghdl/tb_busmaster_sync.make
+++ b/lib/JBUS/busmaster/ghdl/tb_busmaster_sync.make
@@ -1,14 +1,14 @@
-include ../../../lib/FIFO/ghdl/fifo_sync.inc
+include ../../../../lib/FIFO/ghdl/fifo_sync.inc
 
-ROOT_PATH := ../../..
+ROOT_PATH := ../../../..
 LIB_PATH := $(ROOT_PATH)/lib
-MOD_PATH := $(LIB_PATH)/JBUS
+MOD_PATH := $(LIB_PATH)/JBUS/busmaster
 
 SRCS += $(LIB_PATH)/misc/utils_pkg.vhd
 SRCS += $(FIFO_SYNC_SRCS)
-SRCS += $(MOD_PATH)/src/busmaster/busmaster_types.vhd
-SRCS += $(MOD_PATH)/src/busmaster/busmaster_sync.vhd
-SRCS += $(MOD_PATH)/src/busmaster/tb_busmaster_sync.vhd
+SRCS += $(MOD_PATH)/src/busmaster_types.vhd
+SRCS += $(MOD_PATH)/src/busmaster_sync.vhd
+SRCS += $(MOD_PATH)/src/tb_busmaster_sync.vhd
 
 # Compile
 TARGET := tb_busmaster_sync
diff --git a/lib/JBUS/dmac/ghdl/tb_dmac_sync.make b/lib/JBUS/dmac/ghdl/tb_dmac_sync.make
index f1e6754..b274130 100644
--- a/lib/JBUS/dmac/ghdl/tb_dmac_sync.make
+++ b/lib/JBUS/dmac/ghdl/tb_dmac_sync.make
@@ -1,15 +1,15 @@
-include ../../../lib/FIFO/ghdl/fifo_sync.inc
+include ../../../../lib/FIFO/ghdl/fifo_sync.inc
 
-ROOT_PATH := ../../..
+ROOT_PATH := ../../../..
 LIB_PATH := $(ROOT_PATH)/lib
 MOD_PATH := $(LIB_PATH)/JBUS
 
 SRCS += $(LIB_PATH)/misc/utils_pkg.vhd
 SRCS += $(FIFO_SYNC_SRCS)
-SRCS += $(MOD_PATH)/src/busmaster/busmaster_types.vhd
-SRCS += $(MOD_PATH)/src/busmaster/busmaster_sync.vhd
-SRCS += $(MOD_PATH)/src/dmac/dmac.vhd
-SRCS += $(MOD_PATH)/src/dmac/tb_dmac.vhd
+SRCS += $(MOD_PATH)/busmaster/src/busmaster_types.vhd
+SRCS += $(MOD_PATH)/busmaster/src/busmaster_sync.vhd
+SRCS += $(MOD_PATH)/dmac/src/dmac.vhd
+SRCS += $(MOD_PATH)/dmac/src/tb_dmac.vhd
 
 # Compile
 TARGET := tb_dmac_sync
diff --git a/lib/JBUS/memory/ghdl/tb_ram_wb.make b/lib/JBUS/memory/ghdl/tb_ram_wb.make
index 0ef15b6..94c99a9 100644
--- a/lib/JBUS/memory/ghdl/tb_ram_wb.make
+++ b/lib/JBUS/memory/ghdl/tb_ram_wb.make
@@ -1,11 +1,11 @@
-ROOT_PATH := ../../..
+ROOT_PATH := ../../../..
 LIB_PATH := $(ROOT_PATH)/lib
-MOD_PATH := $(LIB_PATH)/JBUS
+MOD_PATH := $(LIB_PATH)/JBUS/memory
 
 SRCS += $(LIB_PATH)/misc/utils_pkg.vhd
 SRCS += $(LIB_PATH)/rams/sim/dpram_1w1r1c_ra.vhd
-SRCS += $(MOD_PATH)/src/memory/ram_wb.vhd
-SRCS += $(MOD_PATH)/src/memory/tb_ram_wb.vhd
+SRCS += $(MOD_PATH)/src/ram_wb.vhd
+SRCS += $(MOD_PATH)/src/tb_ram_wb.vhd
 
 # Compile
 TARGET := tb_ram_wb
diff --git a/lib/JBUS/memory/ghdl/tb_rom_wb.make b/lib/JBUS/memory/ghdl/tb_rom_wb.make
index daf2fe9..c4e0c6f 100644
--- a/lib/JBUS/memory/ghdl/tb_rom_wb.make
+++ b/lib/JBUS/memory/ghdl/tb_rom_wb.make
@@ -1,10 +1,10 @@
-ROOT_PATH := ../../..
+ROOT_PATH := ../../../..
 LIB_PATH := $(ROOT_PATH)/lib
-MOD_PATH := $(LIB_PATH)/JBUS
+MOD_PATH := $(LIB_PATH)/JBUS/memory
 
-SRCS += $(MOD_PATH)/src/memory/rom_sim.vhd
-SRCS += $(MOD_PATH)/src/memory/rom_wb.vhd
-SRCS += $(MOD_PATH)/src/memory/tb_rom_wb.vhd
+SRCS += $(MOD_PATH)/src/rom_sim.vhd
+SRCS += $(MOD_PATH)/src/rom_wb.vhd
+SRCS += $(MOD_PATH)/src/tb_rom_wb.vhd
 
 # Compile
 TARGET := tb_rom_wb