From 46e1bd322c34a09ba9657d3d9b0c54c0340bf22e Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sat, 24 Oct 2015 07:02:37 +0000 Subject: [PATCH] - fixed fir_stage_sys git-svn-id: http://moon:8086/svn/vhdl/trunk@1318 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/filter/sim/tb_fir_stage_sys.fdo | 2 - lib/filter/sim/tb_fir_stage_sys.wdo | 68 +++++++++++++++++------------ lib/filter/src/fir_stage_sys.vhd | 50 ++++++++------------- lib/filter/src/tb_fir_stage_sys.vhd | 50 ++++++++++++++------- 4 files changed, 93 insertions(+), 77 deletions(-) diff --git a/lib/filter/sim/tb_fir_stage_sys.fdo b/lib/filter/sim/tb_fir_stage_sys.fdo index b2417c3..c167efe 100644 --- a/lib/filter/sim/tb_fir_stage_sys.fdo +++ b/lib/filter/sim/tb_fir_stage_sys.fdo @@ -1,5 +1,3 @@ -vmap ieee_proposed ../../../Common/sim/ieee_proposed - vlib work vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd" vcom -explicit -93 "../../../lib/fixed/fixed_util_pkg.vhd" diff --git a/lib/filter/sim/tb_fir_stage_sys.wdo b/lib/filter/sim/tb_fir_stage_sys.wdo index 21e822e..80f42e2 100644 --- a/lib/filter/sim/tb_fir_stage_sys.wdo +++ b/lib/filter/sim/tb_fir_stage_sys.wdo @@ -1,28 +1,40 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_fir_stage_sys/clk -add wave -noupdate -divider Input -add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/x_in -add wave -noupdate -format Literal /tb_fir_stage_sys/xi -add wave -noupdate -divider Output -add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/y_out -add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_fir_stage_sys/yo -add wave -noupdate -divider {Stage signals} -add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/x -add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/y -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {1060000 ps} 0} -configure wave -namecolwidth 140 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {706931 ps} {1268317 ps} +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -format Logic /tb_fir_stage_sys/clk +add wave -noupdate -divider Input +add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/x_in +add wave -noupdate -format Literal /tb_fir_stage_sys/xi +add wave -noupdate -divider Output +add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/y_out +add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_fir_stage_sys/yo +add wave -noupdate -format Literal /tb_fir_stage_sys/hr +add wave -noupdate -divider {Stage signals} +add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/x +add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/y +add wave -noupdate -divider d +add wave -noupdate -format Literal /tb_fir_stage_sys/uut_first_stage_sys/x_in +add wave -noupdate -format Literal /tb_fir_stage_sys/uut_first_stage_sys/y_in +add wave -noupdate -format Literal /tb_fir_stage_sys/uut_first_stage_sys/h_in +add wave -noupdate -format Literal /tb_fir_stage_sys/uut_first_stage_sys/x_out +add wave -noupdate -format Literal /tb_fir_stage_sys/uut_first_stage_sys/y_out +add wave -noupdate -format Literal /tb_fir_stage_sys/uut_first_stage_sys/yin +add wave -noupdate -format Literal /tb_fir_stage_sys/uut_first_stage_sys/prod +add wave -noupdate -format Logic /tb_fir_stage_sys/uut_first_stage_sys/vld_out +add wave -noupdate -format Logic /tb_fir_stage_sys/uut_first_stage_sys/ce +add wave -noupdate -format Literal /tb_fir_stage_sys/uut_first_stage_sys/vld +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {954217 ps} 0} {{Cursor 2} {0 ps} 0} {{Cursor 3} {148250000 ps} 0} +configure wave -namecolwidth 140 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +update +WaveRestoreZoom {0 ps} {2100 ns} diff --git a/lib/filter/src/fir_stage_sys.vhd b/lib/filter/src/fir_stage_sys.vhd index af0f74a..6021526 100644 --- a/lib/filter/src/fir_stage_sys.vhd +++ b/lib/filter/src/fir_stage_sys.vhd @@ -41,18 +41,19 @@ Generic nbits_in : integer := 12; nbits_in_frac : integer := 12; nbits_out : integer := 12; - nbits_out_frac : integer := 12; - pipe_latency : integer := 4 + nbits_out_frac : integer := 12 ); Port ( + rst : in std_logic; clk : in std_logic; ce : in std_logic; x_in : in sfixed; y_in : in sfixed; h_in : in sfixed; x_out : out sfixed; - y_out : out sfixed + y_out : out sfixed; + vld_out : out std_logic ); end fir_stage_sys; @@ -63,44 +64,31 @@ constant min_pipe_lat : integer := 4; subtype in_t is sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); subtype out_t is sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); -type input_pipe_t is array (pipe_latency-2 downto 0) of in_t; -type coef_pipe_t is array (pipe_latency-2 downto 0) of in_t; - -signal yin : in_t; -signal prod : out_t; +signal yin : in_t; +signal prod : out_t; +signal x_reg : out_t; +signal y_reg : out_t; +signal vld : unsigned(1 downto 0); ------------------------------------------------------------ begin - assert pipe_latency >= min_pipe_lat report "Pipe latency must be greater than " & natural'image(min_pipe_lat-1) & "!" severity failure; - yin <= resize(y_in, yin); - ------------------------------------------------------------- - proc_pipe_reg: process(clk) - variable h_pipe : coef_pipe_t; - variable x_pipe : input_pipe_t; - begin - if rising_edge(clk) then - if ce = '1' then - x_pipe := x_pipe(x_pipe'left-1 downto 0) & resize(x_in, x_pipe(0)); - h_pipe := h_pipe(h_pipe'left-1 downto 0) & resize(h_in, h_pipe(0)); - prod <= resize(x_pipe(x_pipe'left) * h_pipe(h_pipe'left), prod, fixed_wrap, fixed_truncate); - end if; - end if; - end process; + vld_out <= vld(vld'left); + y_out <= y_reg; ------------------------------------------------------------ proc_out_reg: process(clk) - variable yout : out_t; - variable xout : in_t; begin if rising_edge(clk) then - if ce = '1' then - yout := resize(yin + prod, yout, fixed_wrap, fixed_truncate); - y_out <= yout; - xout := resize(x_in, xout, fixed_wrap, fixed_truncate); - x_out <= xout; + if rst = '1' then + vld <= (others => '0'); + elsif ce = '1' then + vld <= vld(vld'left-1 downto 0) & '1'; + prod <= resize(x_in * h_in, prod, fixed_wrap, fixed_truncate); + x_reg <= resize(x_in, x_reg, fixed_wrap, fixed_truncate); + y_reg <= resize(yin + prod, y_reg, fixed_wrap, fixed_truncate); + x_out <= x_reg; end if; end if; end process; diff --git a/lib/filter/src/tb_fir_stage_sys.vhd b/lib/filter/src/tb_fir_stage_sys.vhd index b0afe32..ef7d37e 100644 --- a/lib/filter/src/tb_fir_stage_sys.vhd +++ b/lib/filter/src/tb_fir_stage_sys.vhd @@ -51,19 +51,19 @@ ARCHITECTURE behavior OF tb_fir_stage_sys IS nbits_in_frac : integer; nbits_out : integer; nbits_out_frac : integer; - input_latency : integer; - coef_latency : integer; pipe_latency : integer ); PORT ( + rst : in std_logic; clk : in std_logic; ce : in std_logic; x_in : in sfixed; y_in : in sfixed; h_in : in sfixed; x_out : out sfixed; - y_out : out sfixed + y_out : out sfixed; + vld_out : out std_logic ); END COMPONENT; @@ -74,18 +74,22 @@ ARCHITECTURE behavior OF tb_fir_stage_sys IS constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac); --Inputs - SIGNAL ce : std_logic := '1'; + SIGNAL rst : std_logic := '1'; + SIGNAL ce : std_logic := '1'; SIGNAL clk : std_logic := '0'; SIGNAL x_in : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); --Outputs SIGNAL x_out : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); SIGNAL y_out : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); + SIGNAL vld_out : std_logic; SIGNAL x : stages_t(0 to ntaps-2); SIGNAL y : stages_t(0 to ntaps-2); + SIGNAL vld : unsigned(0 to ntaps-2); SIGNAL fileout_enable : std_logic := '1'; + signal hr : real_array_t(ntaps-1 downto 0); -- Test coefficients function to_sfixed(x_real : real_array_t) return stages_t is @@ -98,7 +102,17 @@ ARCHITECTURE behavior OF tb_fir_stage_sys IS return res; end to_sfixed; - constant h : stages_t(0 to ntaps-1) := to_sfixed(FilterCoef_Lowpass(ntaps, 0.25, 1.0)); + function to_real(x_fixed : stages_t) return real_array_t is + variable res : real_array_t(x_fixed'range); + begin + for i in x_fixed'range loop + res(i) := to_real(x_fixed(i)); + end loop; + + return res; + end to_real; + + signal h : stages_t(0 to ntaps-1) := to_sfixed(FilterCoef_Lowpass(ntaps, 0.25, 1.0)); SIGNAL xi, yo : real := 0.0; @@ -106,6 +120,7 @@ BEGIN xi <= to_real(x_in); yo <= to_real(y_out); + hr <= to_real(h); ---------------------------------------- -- Instantiate the Unit Under Test (UUT) @@ -117,19 +132,19 @@ BEGIN nbits_in_frac => nbits_in_frac, nbits_out => nbits_stages, nbits_out_frac => nbits_stages_frac, - input_latency => 1, - coef_latency => 1, pipe_latency => 2 ) PORT MAP ( + rst => rst, clk => clk, ce => ce, x_in => x_in, y_in => zero_in, h_in => h(ntaps-1), x_out => x(0), - y_out => y(0) + y_out => y(0), + vld_out => vld(0) ); ---------------------------------------- @@ -142,19 +157,19 @@ BEGIN nbits_in_frac => nbits_stages_frac, nbits_out => nbits_stages, nbits_out_frac => nbits_stages_frac, - input_latency => 2, - coef_latency => 1, pipe_latency => 2 ) PORT MAP ( + rst => rst, clk => clk, - ce => ce, + ce => vld(i-1), x_in => x(i-1), y_in => y(i-1), h_in => h(ntaps-i-1), x_out => x(i), - y_out => y(i) + y_out => y(i), + vld_out => vld(i) ); end generate; @@ -166,19 +181,19 @@ BEGIN nbits_in_frac => nbits_stages_frac, nbits_out => nbits_out, nbits_out_frac => nbits_out_frac, - input_latency => 2, - coef_latency => 1, pipe_latency => 2 ) PORT MAP ( + rst => rst, clk => clk, - ce => ce, + ce => vld(ntaps-2), x_in => x(ntaps-2), y_in => y(ntaps-2), h_in => h(0), x_out => x_out, - y_out => y_out + y_out => y_out, + vld_out => vld_out ); ---------------------------------------- @@ -196,6 +211,9 @@ BEGIN -- Wait 100 ns for global reset to finish wait for 4*PERIOD; + rst <= '0'; + + wait until rising_edge(clk); x_in <= to_sfixed(0.0, x_in); wait for 40*PERIOD;