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- removed explicit tag_ram_read

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- remove state 'rd_cache'
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git-svn-id: http://moon:8086/svn/vhdl/trunk@340 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-02-11 10:32:19 +00:00
parent 905094be8b
commit 44ef835b7a
2 changed files with 9 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/CPUs/MIPS/src/core/dcache.vhd
+4 -10
View File
@@ -127,7 +127,7 @@ END COMPONENT;
return result; return result;
end to_tram_data; end to_tram_data;
type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_wait, mem_data, upd_cache, rd_cache); type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_wait, mem_data, upd_cache);
signal s, sn : cache_state_t; signal s, sn : cache_state_t;
signal cache_busy : std_logic; signal cache_busy : std_logic;
@@ -159,7 +159,6 @@ END COMPONENT;
signal tram_dout : tram_data_t; signal tram_dout : tram_data_t;
signal tram_addr_wr : unsigned(cache_index_width-1 downto 0); signal tram_addr_wr : unsigned(cache_index_width-1 downto 0);
signal tram_din : tram_data_t; signal tram_din : tram_data_t;
signal tram_re : std_logic;
signal tram_we : std_logic; signal tram_we : std_logic;
signal fill_count : natural range 0 to 2**word_index_width-1; signal fill_count : natural range 0 to 2**word_index_width-1;
@@ -255,7 +254,7 @@ inst_tag_ram : dpram_1w1r
clka => CLK_I, clka => CLK_I,
clkb => CLK_I, clkb => CLK_I,
en_a => '1', en_a => '1',
en_b => tram_re, en_b => '1',
we_a => tram_we, we_a => tram_we,
addr_a => tram_addr_wr, addr_a => tram_addr_wr,
addr_b => tram_addr_rd, addr_b => tram_addr_rd,
@@ -327,13 +326,13 @@ cache_state:
request_count_rst <= '0'; request_count_rst <= '0';
CYC_O <= '0'; CYC_O <= '0';
STB_O <= '0'; STB_O <= '0';
tram_re <= '0';
was_miss <= '0'; was_miss <= '0';
cache_fill <= '0'; cache_fill <= '0';
tram_addr_wr <= to_unsigned(flush_index_count, cache_index_width); tram_addr_wr <= to_unsigned(flush_index_count, cache_index_width);
cache_entry_in.tv_p <= (others => '0'); cache_entry_in.tv_p <= (others => '0');
cache_entry_in.tag <= tag_index_reg; cache_entry_in.tag <= tag_index_reg;
cache_entry_in.valid <= '0'; cache_entry_in.valid <= '0';
sn <= s; sn <= s;
case s is case s is
@@ -342,7 +341,6 @@ cache_state:
when ready => when ready =>
cache_busy <= '0'; cache_busy <= '0';
cpu_reg_en <= '1'; cpu_reg_en <= '1';
tram_re <= cpu_en;
if cpu_en2 = '1' then if cpu_en2 = '1' then
if cache_hit = '0' and cpu_we_reg = '0' then if cache_hit = '0' and cpu_we_reg = '0' then
sn <= mem_request; sn <= mem_request;
@@ -361,7 +359,6 @@ cache_state:
sn <= ready; sn <= ready;
if cpu_en = '1' then if cpu_en = '1' then
cpu_reg_en <= '1'; cpu_reg_en <= '1';
tram_re <= '1';
end if; end if;
end if; end if;
when mem_request => when mem_request =>
@@ -393,11 +390,8 @@ cache_state:
tram_addr_wr <= cache_index_reg; tram_addr_wr <= cache_index_reg;
tram_we <= '1'; tram_we <= '1';
cache_entry_in.valid <= '1'; cache_entry_in.valid <= '1';
sn <= rd_cache;
when rd_cache =>
tram_re <= '1';
was_miss <= '1'; was_miss <= '1';
sn <= ready; sn <= ready;
when others => when others =>
sn <= ready; sn <= ready;
lib/CPUs/MIPS/src/core/icache.vhd
+5 -10
View File
@@ -101,7 +101,7 @@ END COMPONENT;
return result; return result;
end to_tag_ram_data; end to_tag_ram_data;
type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_wait, mem_data, upd_cache, rd_cache); type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_wait, mem_data, upd_cache);
signal s, sn : cache_state_t; signal s, sn : cache_state_t;
signal cache_busy : std_logic; signal cache_busy : std_logic;
@@ -165,7 +165,7 @@ inst_tag_ram : dpram_1w1r
clka => CLK_I, clka => CLK_I,
clkb => CLK_I, clkb => CLK_I,
en_a => '1', en_a => '1',
en_b => tag_ram_re, en_b => '1',
we_a => tag_ram_we, we_a => tag_ram_we,
addr_a => tag_ram_addr_wr, addr_a => tag_ram_addr_wr,
addr_b => tag_ram_addr_rd, addr_b => tag_ram_addr_rd,
@@ -230,13 +230,13 @@ cache_state:
CYC_O <= '0'; CYC_O <= '0';
STB_O <= '0'; STB_O <= '0';
data_ram_re <= '0'; data_ram_re <= '0';
tag_ram_re <= '0';
was_miss <= '0'; was_miss <= '0';
data_write <= '0'; data_write <= '0';
tag_ram_addr_wr <= to_unsigned(cache_index_count, cache_index_width); tag_ram_addr_wr <= to_unsigned(cache_index_count, cache_index_width);
cache_entry_in.tv_p <= (others => '0'); cache_entry_in.tv_p <= (others => '0');
cache_entry_in.tag <= tag_index_reg; cache_entry_in.tag <= tag_index_reg;
cache_entry_in.valid <= '0'; cache_entry_in.valid <= '0';
sn <= s; sn <= s;
case s is case s is
@@ -253,7 +253,6 @@ cache_state:
elsif cpu_en = '1' then elsif cpu_en = '1' then
cpu_reg_en <= '1'; cpu_reg_en <= '1';
data_ram_re <= '1'; data_ram_re <= '1';
tag_ram_re <= '1';
end if; end if;
end if; end if;
when flush => when flush =>
@@ -267,7 +266,6 @@ cache_state:
if cpu_en = '1' then if cpu_en = '1' then
cpu_reg_en <= '1'; cpu_reg_en <= '1';
data_ram_re <= '1'; data_ram_re <= '1';
tag_ram_re <= '1';
end if; end if;
end if; end if;
when mem_request => when mem_request =>
@@ -299,13 +297,10 @@ cache_state:
tag_ram_addr_wr <= cache_index_reg; tag_ram_addr_wr <= cache_index_reg;
tag_ram_we <= '1'; tag_ram_we <= '1';
cache_entry_in.valid <= '1'; cache_entry_in.valid <= '1';
sn <= rd_cache;
when rd_cache =>
tag_ram_re <= '1';
data_ram_re <= '1'; data_ram_re <= '1';
was_miss <= '1'; was_miss <= '1';
sn <= ready; sn <= ready;
when others => when others =>
sn <= ready; sn <= ready;
end case; end case;