From 44743f9de870aca040059cfc6cbc912795b6d1f8 Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Wed, 24 Mar 2021 13:53:25 +0000
Subject: [PATCH] - added

git-svn-id: http://moon:8086/svn/vhdl/trunk@1519 cc03376c-175c-47c8-b038-4cd826a8556b
---
 ...rl_frontend.make => tb_ctrl_ddr_wb32.make} |  0
 .../ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb64.gtkw   | 35 +++++++++++++++++++
 .../ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb64.make   | 33 +++++++++++++++++
 3 files changed, 68 insertions(+)
 rename lib/SDRAM/ddr_sdr_v1_5/ghdl/{tb_sdram_ctrl_frontend.make => tb_ctrl_ddr_wb32.make} (100%)
 create mode 100644 lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb64.gtkw
 create mode 100644 lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb64.make

diff --git a/lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_sdram_ctrl_frontend.make b/lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb32.make
similarity index 100%
rename from lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_sdram_ctrl_frontend.make
rename to lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb32.make
diff --git a/lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb64.gtkw b/lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb64.gtkw
new file mode 100644
index 0000000..4eaa2db
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb64.gtkw
@@ -0,0 +1,35 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Wed Mar 24 13:52:01 2021
+[*]
+[dumpfile] "/home/jens/work/vhdl/trunk/lib/SDRAM/ddr_sdr_v1_5/ghdl/build/tb_ctrl_ddr_wb64/tb_ctrl_ddr_wb64.vcd"
+[dumpfile_mtime] "Wed Mar 24 13:50:19 2021"
+[dumpfile_size] 117402616
+[savefile] "/home/jens/work/vhdl/trunk/lib/SDRAM/ddr_sdr_v1_5/ghdl/build/tb_ctrl_ddr_wb64/tb_ctrl_ddr_wb64.gtkw"
+[timestart] 0
+[size] 1856 1136
+[pos] -2 -2
+*-34.925323 79900000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] tb_ctrl_ddr_wb64.
+[treeopen] tb_ctrl_ddr_wb64.uut.
+[sst_width] 233
+[signals_width] 347
+[sst_expanded] 1
+[sst_vpaned_height] 331
+@28
+tb_ctrl_ddr_wb64.uut.inst_sdram_phy.clk
+tb_ctrl_ddr_wb64.uut.inst_sdram_phy.rst
+@22
+tb_ctrl_ddr_wb64.uut.inst_sdram_phy.data_r[63:0]
+tb_ctrl_ddr_wb64.uut.inst_sdram_phy.data_reg_r[63:0]
+tb_ctrl_ddr_wb64.uut.inst_sdram_phy.drive270[31:0]
+@28
+tb_ctrl_ddr_wb64.uut.inst_sdram_phy.part_clk_n
+tb_ctrl_ddr_wb64.uut.inst_sdram_phy.part_clk_p
+tb_ctrl_ddr_wb64.uut.inst_sdram_phy.part_cs_n
+@23
+tb_ctrl_ddr_wb64.uut.inst_sdram_phy.part_data[31:0]
+@22
+tb_ctrl_ddr_wb64.uut.inst_sdram_phy.wr_data[31:0]
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb64.make b/lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb64.make
new file mode 100644
index 0000000..db1b87f
--- /dev/null
+++ b/lib/SDRAM/ddr_sdr_v1_5/ghdl/tb_ctrl_ddr_wb64.make
@@ -0,0 +1,33 @@
+include ../../../../lib/FIFO/ghdl/fifo_sync.inc
+include ../../../../lib/FIFO/ghdl/fifo_async.inc
+
+ROOT_PATH := ../../../..
+LIB_PATH := $(ROOT_PATH)/lib
+MOD_PATH := $(LIB_PATH)/SDRAM/ddr_sdr_v1_5
+
+SRCS += $(LIB_PATH)/misc/utils_pkg.vhd
+SRCS += $(LIB_PATH)/models/memory/sdram/mt46v16m16/mt46v16m16.vhd
+SRCS += $(FIFO_SYNC_SRCS)
+SRCS += $(FIFO_ASYNC_SRCS)
+SRCS += $(MOD_PATH)/src/sdram_const.vhd
+SRCS += $(MOD_PATH)/src/sdram_config_mt46v16m16.vhd
+SRCS += $(MOD_PATH)/src/sdram_types.vhd
+SRCS += $(MOD_PATH)/src/sdram_cmd.vhd
+SRCS += $(MOD_PATH)/src/sdram_ctrl.vhd
+SRCS += $(MOD_PATH)/src/ddr_clk_virtex4.vhd
+SRCS += $(MOD_PATH)/src/ddr_phy_virtex4.vhd
+SRCS += $(MOD_PATH)/src/sdram_ctrl_top.vhd
+SRCS += $(MOD_PATH)/src/sdram_ctrl_frontend_wb64.vhd
+SRCS += $(MOD_PATH)/src/ctrl_ddr_wb64.vhd
+SRCS += $(MOD_PATH)/src/tb_ctrl_ddr_wb64.vhd
+
+# Compile
+TARGET := tb_ctrl_ddr_wb64
+ENTITY := tb_ctrl_ddr_wb64
+WITH_VCD := y
+RUN_TIME := 200us
+
+GHDL_OPTS := -P$(ROOT_PATH)/Common/sim/build/unisim/unisim -fsynopsys -fexplicit
+
+include $(ROOT_PATH)/Common/make/ghdl.mk
+