From 44551d28fd65cf8ced83299f7a75dfa121ecbcf9 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Mon, 25 May 2015 08:13:37 +0000 Subject: [PATCH] - fixed git-svn-id: http://moon:8086/svn/vhdl/trunk@1226 cc03376c-175c-47c8-b038-4cd826a8556b --- projects/mips_sys/src/mips_sys.vhd | 3 --- projects/mips_sys/src/mips_sys_sim.vhd | 3 --- projects/mips_sys/src/sdram_config.vhd | 19 ++++--------------- projects/mips_sys/src/sdram_config_sim.vhd | 15 ++------------- 4 files changed, 6 insertions(+), 34 deletions(-) diff --git a/projects/mips_sys/src/mips_sys.vhd b/projects/mips_sys/src/mips_sys.vhd index 6c69059..6fd4926 100644 --- a/projects/mips_sys/src/mips_sys.vhd +++ b/projects/mips_sys/src/mips_sys.vhd @@ -486,8 +486,6 @@ ARCHITECTURE behavior OF mips_sys IS signal debug : unsigned(1 downto 0); - -- DDR SDRAM - constant BURST_LEN : natural := 2; constant vga_freq : real := real(tsvga.f_pxl_clk)/1.0E6; type mem_area_t is (mem_dead, mem_flash, mem_usb, mem_rom, mem_gpio, mem_uart0, mem_uart1, mem_ps2_0, mem_ps2_1, mem_sdram, mem_vga, mem_ac97, mem_emac); @@ -930,7 +928,6 @@ inst_clockgen_vga : entity work.clockgen inst_sdram_ctrl_wb64 : entity work.ctrl_ddr_wb64 GENERIC MAP ( - BURST_LEN => BURST_LEN, F_SYSCLK => sys_freq_in, F_SDRCLK => sys_freq_in, FIFO_DEPTH => 5 diff --git a/projects/mips_sys/src/mips_sys_sim.vhd b/projects/mips_sys/src/mips_sys_sim.vhd index 4f83a5c..58f9a65 100644 --- a/projects/mips_sys/src/mips_sys_sim.vhd +++ b/projects/mips_sys/src/mips_sys_sim.vhd @@ -316,8 +316,6 @@ ARCHITECTURE behavior OF mips_sys IS signal debug : unsigned(1 downto 0); - -- DDR SDRAM - constant BURST_LEN : natural := 2; constant topad : time := 3 ns; constant vga_freq : real := real(tsvga.f_pxl_clk)/1.0E6; @@ -843,7 +841,6 @@ inst_clocken_vga : entity work.clockgen inst_sdram_ctrl_wb64 : entity work.ctrl_ddr_wb64 GENERIC MAP ( - BURST_LEN => BURST_LEN, F_SYSCLK => sys_freq_in, F_SDRCLK => sys_freq_in, FIFO_DEPTH => 5 diff --git a/projects/mips_sys/src/sdram_config.vhd b/projects/mips_sys/src/sdram_config.vhd index fe869f6..97a709f 100644 --- a/projects/mips_sys/src/sdram_config.vhd +++ b/projects/mips_sys/src/sdram_config.vhd @@ -27,6 +27,7 @@ USE IEEE.NUMERIC_STD.ALL; package sdram_config is + constant DATA_RATE_FACTOR : positive := 2; -- DDR => twice part data width constant PART_DATA_WIDTH : positive := 32; -- External DDR-SDRAM Module data bus width constant PART_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module constant PART_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM @@ -35,27 +36,15 @@ package sdram_config is constant PART_DQS_WIDTH : positive := PART_DATA_WIDTH / 8; -- Number of data strobe lines constant PART_DM_WIDTH : positive := PART_DATA_WIDTH / 8; -- Number of Data Mask Lines - constant BUS_DATA_WIDTH : positive := 2*PART_DATA_WIDTH; -- DDR => twice part data width - constant BUS_DM_WIDTH : positive := 2*PART_DM_WIDTH; -- DDR => twice part data width + constant BUS_DATA_WIDTH : positive := DATA_RATE_FACTOR*PART_DATA_WIDTH; -- DDR => twice part data width + constant BUS_DM_WIDTH : positive := DATA_RATE_FACTOR*PART_DM_WIDTH; -- DDR => twice part data width - constant LMR_REG_BASE : natural := 0; - constant LMR_REG_EXTENDED : natural := 1; - constant LMR_OP_NORMAL : natural := 0; - constant LMR_OP_RES_DLL : natural := 2; - constant LMR_BT_SEQ : natural := 0; - constant LMR_BT_ILVD : natural := 1; - constant LMR_BL2 : natural := 1; - constant LMR_BL4 : natural := 2; - constant LMR_BL8 : natural := 3; - constant LMR_CL2 : natural := 2; - constant LMR_CL3 : natural := 3; - constant LMR_CL2_5 : natural := 6; - -- DDR SDRAM Hardware defined constants constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet) constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet) constant ENABLE_PRE_ALL : std_logic := '1'; constant ENABLE_AUTO_PRE : std_logic := '0'; + constant LMR_BL_CURR : natural := LMR_BL2; -- DDR-SDR TIMING constants ------------------------------------------------------------------ -- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh diff --git a/projects/mips_sys/src/sdram_config_sim.vhd b/projects/mips_sys/src/sdram_config_sim.vhd index 95b6adc..cf18d70 100644 --- a/projects/mips_sys/src/sdram_config_sim.vhd +++ b/projects/mips_sys/src/sdram_config_sim.vhd @@ -27,6 +27,7 @@ USE IEEE.NUMERIC_STD.ALL; package sdram_config is + constant DATA_RATE_FACTOR : positive := 2; -- DDR => twice part data width constant PART_DATA_WIDTH : positive := 32; -- External DDR-SDRAM Module data bus width constant PART_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module constant PART_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM @@ -38,24 +39,12 @@ package sdram_config is constant BUS_DATA_WIDTH : positive := 2*PART_DATA_WIDTH; -- DDR => twice part data width constant BUS_DM_WIDTH : positive := 2*PART_DM_WIDTH; -- DDR => twice part data width - constant LMR_REG_BASE : natural := 0; - constant LMR_REG_EXTENDED : natural := 1; - constant LMR_OP_NORMAL : natural := 0; - constant LMR_OP_RES_DLL : natural := 2; - constant LMR_BT_SEQ : natural := 0; - constant LMR_BT_ILVD : natural := 1; - constant LMR_BL2 : natural := 1; - constant LMR_BL4 : natural := 2; - constant LMR_BL8 : natural := 3; - constant LMR_CL2 : natural := 2; - constant LMR_CL3 : natural := 3; - constant LMR_CL2_5 : natural := 6; - -- DDR SDRAM Hardware defined constants constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet) constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet) constant ENABLE_PRE_ALL : std_logic := '1'; constant ENABLE_AUTO_PRE : std_logic := '0'; + constant LMR_BL_CURR : natural := LMR_BL2; -- DDR-SDR TIMING constants ------------------------------------------------------------------ -- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh