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- prpared for testing of 100mbps and 1000mbps

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git-svn-id: http://moon:8086/svn/vhdl/trunk@886 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-04-08 19:04:39 +00:00
parent 0737dc8c74
commit 43f11d43a9
1 changed files with 70 additions and 6 deletions
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lib/emac/src/tb_emac_top_jb.vhd
+70 -6
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@@ -32,7 +32,7 @@ END tb_emac_top_jb;
ARCHITECTURE behavior OF tb_emac_top_jb IS ARCHITECTURE behavior OF tb_emac_top_jb IS
constant CLK_PERIOD : time := 10 ns; constant CLK_PERIOD : time := 10 ns;
constant MII_CLK_PERIOD : time := 38.7 ns; constant MII_CLK_PERIOD : time := 7.7 ns;
signal CLK : std_logic := '1'; signal CLK : std_logic := '1';
signal RST : std_logic := '1'; signal RST : std_logic := '1';
@@ -74,7 +74,7 @@ ARCHITECTURE behavior OF tb_emac_top_jb IS
signal pktgen_tx_en : std_logic; signal pktgen_tx_en : std_logic;
signal pktgen_tx_er : std_logic; signal pktgen_tx_er : std_logic;
signal pktgen_en : std_logic := '0'; signal pktgen_en : std_logic := '0';
signal pktgen_gigabit : std_logic := '0';
signal dat_o_cnt_en : std_logic := '0'; signal dat_o_cnt_en : std_logic := '0';
signal dat_o_cnt_rst : std_logic := '1'; signal dat_o_cnt_rst : std_logic := '1';
signal dat_o_cnt : natural; signal dat_o_cnt : natural;
@@ -131,8 +131,6 @@ inst_pkt_gen : entity work.pkt_gen
GENERIC MAP GENERIC MAP
( (
f_sysclk => 100.0, f_sysclk => 100.0,
PKT_DLY_MIN => 1.0E-6,
PKT_DLY_MAX => 5.0E-6,
PKT_SIZE_MIN => 64, PKT_SIZE_MIN => 64,
PKT_SIZE_MAX => 1512 PKT_SIZE_MAX => 1512
@@ -142,6 +140,7 @@ inst_pkt_gen : entity work.pkt_gen
clk => CLK, clk => CLK,
rst => RST, rst => RST,
en => pktgen_en, en => pktgen_en,
gigabit_en => pktgen_gigabit,
mii_tx_clk => mii_tx_clk_board, mii_tx_clk => mii_tx_clk_board,
mii_tx_en => pktgen_tx_en, mii_tx_en => pktgen_tx_en,
mii_tx_er => pktgen_tx_er, mii_tx_er => pktgen_tx_er,
@@ -197,6 +196,66 @@ DAT_O_count_register:
-- Master -- Master
STIMULUS: process STIMULUS: process
procedure emac_tx_reset_100mbps is
begin
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"8000_0000";
STB_I <= '1';
WE_I <= '1';
ADDR_I <= TX_STATUS_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
WE_I <= '0';
end procedure emac_tx_reset_100mbps;
procedure emac_rx_reset_100mbps is
begin
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"8000_0000";
STB_I <= '1';
WE_I <= '1';
ADDR_I <= RX_STATUS_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
WE_I <= '0';
end procedure emac_rx_reset_100mbps;
procedure emac_tx_reset_1000mbps is
begin
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"C000_0000";
STB_I <= '1';
WE_I <= '1';
ADDR_I <= TX_STATUS_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
WE_I <= '0';
end procedure emac_tx_reset_1000mbps;
procedure emac_rx_reset_1000mbps is
begin
CYC_I <= '1';
wait until rising_edge(CLK) and SRDY_O = '1';
DAT_I <= X"C000_0000";
STB_I <= '1';
WE_I <= '1';
ADDR_I <= RX_STATUS_REG_ADDR;
wait until rising_edge(CLK) and SRDY_O = '1';
STB_I <= '0';
WE_I <= '0';
end procedure emac_rx_reset_1000mbps;
procedure emac_alloc (size : natural) is procedure emac_alloc (size : natural) is
begin begin
@@ -443,7 +502,12 @@ STIMULUS: process
wait for 6*MII_CLK_PERIOD; wait for 6*MII_CLK_PERIOD;
RST <= '0'; RST <= '0';
wait for 60*CLK_PERIOD; wait for 60*CLK_PERIOD;
emac_rx_reset_1000mbps;
emac_tx_reset_1000mbps;
pktgen_gigabit <= '1';
wait for 60*CLK_PERIOD;
emac_alloc (1004); emac_alloc (1004);
emac_alloc (1004); emac_alloc (1004);
emac_alloc (1004); emac_alloc (1004);
@@ -572,7 +636,7 @@ STIMULUS: process
pktgen_en <= '1'; pktgen_en <= '1';
pkt_count <= 0; pkt_count <= 0;
for i in 1 to 500 loop for i in 1 to 500 loop
wait for 50 us; wait for 1 us;
emac_read (0); emac_read (0);
emac_free; emac_free;
pkt_count <= pkt_count + 1; pkt_count <= pkt_count + 1;