diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.wdo b/lib/CPUs/MIPS/sim/tb_mips_top.wdo new file mode 100644 index 0000000..12b16c3 --- /dev/null +++ b/lib/CPUs/MIPS/sim/tb_mips_top.wdo @@ -0,0 +1,223 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider {TOP interface} +add wave -noupdate -format Logic /tb_mips_top/nmi +add wave -noupdate -format Logic /tb_mips_top/rst +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal /tb_mips_top/debug +add wave -noupdate -format Logic /tb_mips_top/stb_o +add wave -noupdate -format Logic /tb_mips_top/ack_i +add wave -noupdate -format Logic /tb_mips_top/srdy_i +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_i +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_o +add wave -noupdate -format Logic /tb_mips_top/we_o +add wave -noupdate -format Literal /tb_mips_top/sel_o +add wave -noupdate -format Logic /tb_mips_top/cyc_o +add wave -noupdate -format Logic /tb_mips_top/mrdy_o +add wave -noupdate -format Literal /tb_mips_top/int +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_shifter/dout +add wave -noupdate -format Logic /tb_mips_top/uut/biu_rst +add wave -noupdate -format Logic /tb_mips_top/uut/cpu_rst +add wave -noupdate -format Logic /tb_mips_top/uut/cpu_run +add wave -noupdate -divider BIU +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/bout_fifo_din +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/bout_fifo_dout +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_re +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_we +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_full +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_empty +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_rdy +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/bus_timeout_cnt +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bus_timeout +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_imem_err +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_imem_rdy +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_imem_en +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/cpu_imem_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/cpu_imem_din +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_dmem_err +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_dmem_rdy +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_dmem_en +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_dmem_we +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/cpu_dmem_be +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/cpu_dmem_dout +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/cpu_dmem_din +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/cpu_dmem_addr +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bus_idle +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/busy +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/dmem_be +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/bin_fifo_din +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/bin_fifo_dout +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bin_fifo_re +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bin_fifo_we +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bin_fifo_full +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bin_fifo_empty +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/write_fifo_din +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/write_fifo_dout +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_re +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_we +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_full +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_empty +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/read_cycle +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/dcached +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/dcache_en2 +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/dcache_en +add wave -noupdate -divider {External components} +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi_0 +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo_0 +add wave -noupdate -format Logic /tb_mips_top/inst_uart/tx_complete +add wave -noupdate -format Logic /tb_mips_top/inst_uart/tx_empty +add wave -noupdate -format Literal /tb_mips_top/inst_uart/uart_status_port +add wave -noupdate -format Logic /tb_mips_top/rx +add wave -noupdate -format Logic /tb_mips_top/tx +add wave -noupdate -divider {Interrupt Timer} +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/timer_cnt +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/timer_cmp +add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_en +add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_inten +add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_irq +add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_ovl +add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_irq_ack +add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_cmp_we +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/reg_data_wr +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal /tb_mips_top/mem_area +add wave -noupdate -format Literal /tb_mips_top/inst_flash_port/s +add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/ack +add wave -noupdate -format Logic /tb_mips_top/stb_o +add wave -noupdate -format Logic /tb_mips_top/srdy_i +add wave -noupdate -format Logic /tb_mips_top/we_o +add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/we_i_r +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_flash_port/addr_i_r +add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/page_mode_en +add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/rdy +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_a +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_d +add wave -noupdate -format Logic /tb_mips_top/ack_i +add wave -noupdate -format Logic /tb_mips_top/flash_cs_n +add wave -noupdate -format Logic /tb_mips_top/flash_we_n +add wave -noupdate -format Logic /tb_mips_top/flash_oe_n +add wave -noupdate -format Literal /tb_mips_top/flash_be_n +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_a +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_d +add wave -noupdate -format Logic /tb_mips_top/ack_i +add wave -noupdate -format Logic /tb_mips_top/sram_cs_n +add wave -noupdate -format Literal /tb_mips_top/sram_wr_n +add wave -noupdate -format Logic /tb_mips_top/sram_oe_n +add wave -noupdate -format Literal /tb_mips_top/sram_be_n +add wave -noupdate -format Logic /tb_mips_top/inst_sram_port/page_mode_en_r +add wave -noupdate -format Logic /tb_mips_top/inst_sram_port/do_page_read +add wave -noupdate -format Logic /tb_mips_top/inst_sram_port/rdy +add wave -noupdate -format Literal /tb_mips_top/inst_sram_port/s +add wave -noupdate -divider ALU +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu +add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/sdu +add wave -noupdate -divider PC +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Logic -radix hexadecimal /tb_mips_top/uut/inst_pipeline/ex_stage.ctrl.branch +add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/branch_ce +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/pc +add wave -noupdate -divider COP0 +add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/ir_en +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/ir +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/test_reg +add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/test_reg_we +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/icache_info +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/dcache_info +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/cop_pipe_id +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/cop_pipe_ex +add wave -noupdate -format Literal /tb_mips_top/uut/inst_cop/ctrl_in +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_en +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_dout +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_busy +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/ctrl_out +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/epc +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/cause +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/status +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/badvaddr +add wave -noupdate -format Literal /tb_mips_top/uut/inst_cop/eflags +add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/status_save +add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/status_rest +add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/stat_reg_we +add wave -noupdate -format Literal /tb_mips_top/uut/inst_cop/exc_state +add wave -noupdate -divider Pipestages +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/id_stage +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/ex_stage +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Logic -label .stall_all /tb_mips_top/uut/inst_pipeline/sdu.stall_all +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage +add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/rst +add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/cpu_run +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_reg_dual/reg_mem +add wave -noupdate -divider I-Cache +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/ctrl +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_en +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_busy +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/tag_match +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_dout +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/request_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/fill_addr +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/request_count +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/flush_count +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/fill_count +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/s +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cache_entry_out +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/data_ram_we +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/tag_ram_we +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/ram +add wave -noupdate -divider D-Cache +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/mrdy_o +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_en +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_busy +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_be +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_we +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_hit_we +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/instant_raw +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_din +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_dout +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_data_reg +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/request_addr +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/request_count +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/fill_addr +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/fill_count +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/flush_count +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_hit +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tag_match +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/s +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/dat_i +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_in +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_out +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_data_reg +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_be_reg +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_we_reg +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_din +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_we +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {Cursor {5877623 ps} 0} +configure wave -namecolwidth 188 +configure wave -valuecolwidth 154 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 100 +configure wave -griddelta 40 +configure wave -timeline 1 +update +WaveRestoreZoom {5846736 ps} {5910641 ps} diff --git a/lib/CPUs/MIPS/src/bootloader.dis b/lib/CPUs/MIPS/src/bootloader.dis new file mode 100644 index 0000000..40da0e3 --- /dev/null +++ b/lib/CPUs/MIPS/src/bootloader.dis @@ -0,0 +1,1467 @@ + +bootloader.elf: file format elf32-bigmips + + +Disassembly of section .init: + +bfc00000 <__entry>: +bfc00000: 3c1d8000 lui sp,0x8000 +bfc00004: 27bdeff0 addiu sp,sp,-4112 +bfc00008: 3c1a1040 lui k0,0x1040 +bfc0000c: 375a000c ori k0,k0,0xc +bfc00010: 409a6000 mtc0 k0,c0_sr +bfc00014: 241a0000 li k0,0 +bfc00018: 409a6800 mtc0 k0,c0_cause +bfc0001c: 401a7800 mfc0 k0,c0_prid +bfc00020: 00000000 nop +bfc00024: 409af800 mtc0 k0,$31 +bfc00028: 42000020 c0 0x20 +bfc0002c: 42000022 c0 0x22 +bfc00030: 3c1abfc0 lui k0,0xbfc0 +bfc00034: 275a005c addiu k0,k0,92 +bfc00038: 0340f809 jalr k0 +bfc0003c: 00000000 nop +bfc00040: 3c1abfc0 lui k0,0xbfc0 +bfc00044: 275a114c addiu k0,k0,4428 +bfc00048: 0340f809 jalr k0 +bfc0004c: 00000000 nop + +bfc00050 <_terminate>: +bfc00050: 00000000 nop +bfc00054: 0bf00014 j bfc00050 <_terminate> +bfc00058: 00000000 nop + +bfc0005c <_init>: +bfc0005c: 3c1aa001 275a0008 241b000d af5b0000 <...'Z..$....[.. +bfc0006c: 03e00008 .... + +Disassembly of section .ktext: + +bfc00180 <_exc_handler>: +bfc00180: 401a6800 mfc0 k0,c0_cause +bfc00184: 3c1bc000 lui k1,0xc000 +bfc00188: 001ad082 srl k0,k0,0x2 +bfc0018c: 335a000f andi k0,k0,0xf +bfc00190: 035bd025 or k0,k0,k1 +bfc00194: 3c1ba000 lui k1,0xa000 +bfc00198: 277b0000 addiu k1,k1,0 +bfc0019c: af7a0000 sw k0,0(k1) +bfc001a0: 401a6800 mfc0 k0,c0_cause +bfc001a4: 00000000 nop +bfc001a8: 001ad202 srl k0,k0,0x8 +bfc001ac: 335a00ff andi k0,k0,0xff +bfc001b0: 1740fffb bnez k0,bfc001a0 <_exc_handler+0x20> +bfc001b4: 00000000 nop +bfc001b8: 401a7000 mfc0 k0,c0_epc +bfc001bc: 00000000 nop +bfc001c0: 03400008 jr k0 +bfc001c4: 42000010 rfe + +Disassembly of section .text: + +bfc001c8 : +bfc001c8: 40026000 mfc0 v0,c0_sr +bfc001cc: 03e00008 jr ra +bfc001d0: 00000000 nop + +bfc001d4 : +bfc001d4: 40846000 mtc0 a0,c0_sr +bfc001d8: 03e00008 jr ra +bfc001dc: 00000000 nop + +bfc001e0 : +bfc001e0: 40026800 mfc0 v0,c0_cause +bfc001e4: 03e00008 jr ra +bfc001e8: 00000000 nop + +bfc001ec : +bfc001ec: 40846800 mtc0 a0,c0_cause +bfc001f0: 03e00008 jr ra +bfc001f4: 00000000 nop + +bfc001f8 : +bfc001f8: 40027800 mfc0 v0,c0_prid +bfc001fc: 03e00008 jr ra +bfc00200: 00000000 nop + +bfc00204 : +bfc00204: 3c02a001 lui v0,0xa001 +bfc00208: 34430004 ori v1,v0,0x4 +bfc0020c: 8c620000 lw v0,0(v1) +bfc00210: 00000000 nop +bfc00214: 30420010 andi v0,v0,0x10 +bfc00218: 1040fffc beqz v0,bfc0020c +bfc0021c: 3c02a001 lui v0,0xa001 +bfc00220: 8c420000 lw v0,0(v0) +bfc00224: 00000000 nop +bfc00228: 00021600 sll v0,v0,0x18 +bfc0022c: 03e00008 jr ra +bfc00230: 00021603 sra v0,v0,0x18 + +bfc00234 : +bfc00234: 00042600 sll a0,a0,0x18 +bfc00238: 3c02a001 lui v0,0xa001 +bfc0023c: 00042603 sra a0,a0,0x18 +bfc00240: 34430004 ori v1,v0,0x4 +bfc00244: 8c620000 lw v0,0(v1) +bfc00248: 00000000 nop +bfc0024c: 30420002 andi v0,v0,0x2 +bfc00250: 1440fffc bnez v0,bfc00244 +bfc00254: 3c02a001 lui v0,0xa001 +bfc00258: ac440000 sw a0,0(v0) +bfc0025c: 03e00008 jr ra +bfc00260: 00000000 nop + +bfc00264 <_putchar>: +bfc00264: 00042600 sll a0,a0,0x18 +bfc00268: 00042603 sra a0,a0,0x18 +bfc0026c: 2402000a li v0,10 +bfc00270: 1482000a bne a0,v0,bfc0029c <_putchar+0x38> +bfc00274: 3c02a001 lui v0,0xa001 +bfc00278: 34430004 ori v1,v0,0x4 +bfc0027c: 8c620000 lw v0,0(v1) +bfc00280: 00000000 nop +bfc00284: 30420002 andi v0,v0,0x2 +bfc00288: 1440fffc bnez v0,bfc0027c <_putchar+0x18> +bfc0028c: 3c02a001 lui v0,0xa001 +bfc00290: 2403000d li v1,13 +bfc00294: ac430000 sw v1,0(v0) +bfc00298: 3c02a001 lui v0,0xa001 +bfc0029c: 34430004 ori v1,v0,0x4 +bfc002a0: 8c620000 lw v0,0(v1) +bfc002a4: 00000000 nop +bfc002a8: 30420002 andi v0,v0,0x2 +bfc002ac: 1440fffc bnez v0,bfc002a0 <_putchar+0x3c> +bfc002b0: 3c02a001 lui v0,0xa001 +bfc002b4: ac440000 sw a0,0(v0) +bfc002b8: 03e00008 jr ra +bfc002bc: 00000000 nop + +bfc002c0 : +bfc002c0: 3c02a001 lui v0,0xa001 +bfc002c4: 34470004 ori a3,v0,0x4 +bfc002c8: 00802821 move a1,a0 +bfc002cc: 2409000a li t1,10 +bfc002d0: 3c06a001 lui a2,0xa001 +bfc002d4: 0bf000c6 j bfc00318 +bfc002d8: 2408000d li t0,13 +bfc002dc: 14690007 bne v1,t1,bfc002fc +bfc002e0: 00000000 nop +bfc002e4: 8ce20000 lw v0,0(a3) +bfc002e8: 00000000 nop +bfc002ec: 30420002 andi v0,v0,0x2 +bfc002f0: 1440fffc bnez v0,bfc002e4 +bfc002f4: 00000000 nop +bfc002f8: acc80000 sw t0,0(a2) +bfc002fc: 8ce20000 lw v0,0(a3) +bfc00300: 00000000 nop +bfc00304: 30420002 andi v0,v0,0x2 +bfc00308: 1440fffc bnez v0,bfc002fc +bfc0030c: 00000000 nop +bfc00310: acc30000 sw v1,0(a2) +bfc00314: 24a50001 addiu a1,a1,1 +bfc00318: 80a30000 lb v1,0(a1) +bfc0031c: 00000000 nop +bfc00320: 1460ffee bnez v1,bfc002dc +bfc00324: 00a41023 subu v0,a1,a0 +bfc00328: 03e00008 jr ra +bfc0032c: 00000000 nop + +bfc00330 : +bfc00330: 00042600 sll a0,a0,0x18 +bfc00334: 3c02a001 lui v0,0xa001 +bfc00338: 00042603 sra a0,a0,0x18 +bfc0033c: 344a0004 ori t2,v0,0x4 +bfc00340: 00003821 move a3,zero +bfc00344: 3c09a001 lui t1,0xa001 +bfc00348: 24080002 li t0,2 +bfc0034c: 308200ff andi v0,a0,0xff +bfc00350: 00022902 srl a1,v0,0x4 +bfc00354: 00041100 sll v0,a0,0x4 +bfc00358: 00022600 sll a0,v0,0x18 +bfc0035c: 2ca3000a sltiu v1,a1,10 +bfc00360: 00042603 sra a0,a0,0x18 +bfc00364: 14600002 bnez v1,bfc00370 +bfc00368: 24a60030 addiu a2,a1,48 +bfc0036c: 24a60037 addiu a2,a1,55 +bfc00370: 8d420000 lw v0,0(t2) +bfc00374: 00000000 nop +bfc00378: 30420002 andi v0,v0,0x2 +bfc0037c: 1440fffc bnez v0,bfc00370 +bfc00380: 00061600 sll v0,a2,0x18 +bfc00384: 00021603 sra v0,v0,0x18 +bfc00388: 24e70001 addiu a3,a3,1 +bfc0038c: ad220000 sw v0,0(t1) +bfc00390: 14e8ffef bne a3,t0,bfc00350 +bfc00394: 308200ff andi v0,a0,0xff +bfc00398: 03e00008 jr ra +bfc0039c: 00000000 nop + +bfc003a0 : +bfc003a0: 27bdffe0 addiu sp,sp,-32 +bfc003a4: afb20018 sw s2,24(sp) +bfc003a8: afb10014 sw s1,20(sp) +bfc003ac: afb00010 sw s0,16(sp) +bfc003b0: afbf001c sw ra,28(sp) +bfc003b4: 00808821 move s1,a0 +bfc003b8: 00008021 move s0,zero +bfc003bc: 24120004 li s2,4 +bfc003c0: 00112603 sra a0,s1,0x18 +bfc003c4: 0ff000cc jal bfc00330 +bfc003c8: 26100001 addiu s0,s0,1 +bfc003cc: 1612fffc bne s0,s2,bfc003c0 +bfc003d0: 00118a00 sll s1,s1,0x8 +bfc003d4: 8fbf001c lw ra,28(sp) +bfc003d8: 8fb20018 lw s2,24(sp) +bfc003dc: 8fb10014 lw s1,20(sp) +bfc003e0: 8fb00010 lw s0,16(sp) +bfc003e4: 03e00008 jr ra +bfc003e8: 27bd0020 addiu sp,sp,32 + +bfc003ec : +bfc003ec: 27bdffc8 addiu sp,sp,-56 +bfc003f0: afb60028 sw s6,40(sp) +bfc003f4: afbf0034 sw ra,52(sp) +bfc003f8: afbe0030 sw s8,48(sp) +bfc003fc: afb7002c sw s7,44(sp) +bfc00400: afb50024 sw s5,36(sp) +bfc00404: afb40020 sw s4,32(sp) +bfc00408: afb3001c sw s3,28(sp) +bfc0040c: afb20018 sw s2,24(sp) +bfc00410: afb10014 sw s1,20(sp) +bfc00414: afb00010 sw s0,16(sp) +bfc00418: 00801021 move v0,a0 +bfc0041c: 10a00002 beqz a1,bfc00428 +bfc00420: 00c0b021 move s6,a2 +bfc00424: 00002021 move a0,zero +bfc00428: 00409821 move s3,v0 +bfc0042c: 3c02a001 lui v0,0xa001 +bfc00430: 00e09021 move s2,a3 +bfc00434: 0080a821 move s5,a0 +bfc00438: 345e0004 ori s8,v0,0x4 +bfc0043c: 00e0a021 move s4,a3 +bfc00440: 3c17a001 lui s7,0xa001 +bfc00444: 0ff000e8 jal bfc003a0 +bfc00448: 02a02021 move a0,s5 +bfc0044c: 3c04bfc0 lui a0,0xbfc0 +bfc00450: 0ff000b0 jal bfc002c0 +bfc00454: 2484169c addiu a0,a0,5788 +bfc00458: 02608821 move s1,s3 +bfc0045c: 0bf00128 j bfc004a0 +bfc00460: 00008021 move s0,zero +bfc00464: 12400009 beqz s2,bfc0048c +bfc00468: 00000000 nop +bfc0046c: 82240000 lb a0,0(s1) +bfc00470: 0ff000cc jal bfc00330 +bfc00474: 2652ffff addiu s2,s2,-1 +bfc00478: 3c04bfc0 lui a0,0xbfc0 +bfc0047c: 0ff000b0 jal bfc002c0 +bfc00480: 24841774 addiu a0,a0,6004 +bfc00484: 0bf00128 j bfc004a0 +bfc00488: 26310001 addiu s1,s1,1 +bfc0048c: 3c04bfc0 lui a0,0xbfc0 +bfc00490: 0ff000b0 jal bfc002c0 +bfc00494: 248416a0 addiu a0,a0,5792 +bfc00498: 0bf0012c j bfc004b0 +bfc0049c: 3c04bfc0 lui a0,0xbfc0 +bfc004a0: 0216102a slt v0,s0,s6 +bfc004a4: 1440ffef bnez v0,bfc00464 +bfc004a8: 26100001 addiu s0,s0,1 +bfc004ac: 3c04bfc0 lui a0,0xbfc0 +bfc004b0: 0ff000b0 jal bfc002c0 +bfc004b4: 248416a0 addiu a0,a0,5792 +bfc004b8: 02602821 move a1,s3 +bfc004bc: 0bf00155 j bfc00554 +bfc004c0: 00002021 move a0,zero +bfc004c4: 1280001e beqz s4,bfc00540 +bfc004c8: 00000000 nop +bfc004cc: 90a30000 lbu v1,0(a1) +bfc004d0: 00000000 nop +bfc004d4: 2462ffe0 addiu v0,v1,-32 +bfc004d8: 304200ff andi v0,v0,0xff +bfc004dc: 2c420060 sltiu v0,v0,96 +bfc004e0: 14400003 bnez v0,bfc004f0 +bfc004e4: 00031e00 sll v1,v1,0x18 +bfc004e8: 2403002e li v1,46 +bfc004ec: 00031e00 sll v1,v1,0x18 +bfc004f0: 00031e03 sra v1,v1,0x18 +bfc004f4: 2402000a li v0,10 +bfc004f8: 14620007 bne v1,v0,bfc00518 +bfc004fc: 00000000 nop +bfc00500: 8fc20000 lw v0,0(s8) +bfc00504: 00000000 nop +bfc00508: 30420002 andi v0,v0,0x2 +bfc0050c: 1440fffc bnez v0,bfc00500 +bfc00510: 2402000d li v0,13 +bfc00514: aee20000 sw v0,0(s7) +bfc00518: 8fc20000 lw v0,0(s8) +bfc0051c: 00000000 nop +bfc00520: 30420002 andi v0,v0,0x2 +bfc00524: 1440fffc bnez v0,bfc00518 +bfc00528: 00000000 nop +bfc0052c: aee30000 sw v1,0(s7) +bfc00530: 2694ffff addiu s4,s4,-1 +bfc00534: 24840001 addiu a0,a0,1 +bfc00538: 0bf00155 j bfc00554 +bfc0053c: 24a50001 addiu a1,a1,1 +bfc00540: 3c04bfc0 lui a0,0xbfc0 +bfc00544: 0ff000b0 jal bfc002c0 +bfc00548: 24841774 addiu a0,a0,6004 +bfc0054c: 0bf00159 j bfc00564 +bfc00550: 3c04bfc0 lui a0,0xbfc0 +bfc00554: 0096102a slt v0,a0,s6 +bfc00558: 1440ffda bnez v0,bfc004c4 +bfc0055c: 00000000 nop +bfc00560: 3c04bfc0 lui a0,0xbfc0 +bfc00564: 0ff000b0 jal bfc002c0 +bfc00568: 248416c8 addiu a0,a0,5832 +bfc0056c: 02b6a821 addu s5,s5,s6 +bfc00570: 1640ffb4 bnez s2,bfc00444 +bfc00574: 02769821 addu s3,s3,s6 +bfc00578: 8fbf0034 lw ra,52(sp) +bfc0057c: 8fbe0030 lw s8,48(sp) +bfc00580: 8fb7002c lw s7,44(sp) +bfc00584: 8fb60028 lw s6,40(sp) +bfc00588: 8fb50024 lw s5,36(sp) +bfc0058c: 8fb40020 lw s4,32(sp) +bfc00590: 8fb3001c lw s3,28(sp) +bfc00594: 8fb20018 lw s2,24(sp) +bfc00598: 8fb10014 lw s1,20(sp) +bfc0059c: 8fb00010 lw s0,16(sp) +bfc005a0: 03e00008 jr ra +bfc005a4: 27bd0038 addiu sp,sp,56 + +bfc005a8 : +bfc005a8: 00c03821 move a3,a2 +bfc005ac: 00a03021 move a2,a1 +bfc005b0: 0bf000fb j bfc003ec +bfc005b4: 24050001 li a1,1 + +bfc005b8 : +bfc005b8: 8c840000 lw a0,0(a0) +bfc005bc: 3c020070 lui v0,0x70 +bfc005c0: 34420070 ori v0,v0,0x70 +bfc005c4: 3c0300ff lui v1,0xff +bfc005c8: ac820000 sw v0,0(a0) +bfc005cc: 346300ff ori v1,v1,0xff +bfc005d0: 8c820000 lw v0,0(a0) +bfc005d4: ac830000 sw v1,0(a0) +bfc005d8: 03e00008 jr ra +bfc005dc: 00000000 nop + +bfc005e0 : +bfc005e0: 27bdfff8 addiu sp,sp,-8 +bfc005e4: ac850000 sw a1,0(a0) +bfc005e8: 24820008 addiu v0,a0,8 +bfc005ec: 0bf0017f j bfc005fc +bfc005f0: 24830020 addiu v1,a0,32 +bfc005f4: a0400000 sb zero,0(v0) +bfc005f8: 24420001 addiu v0,v0,1 +bfc005fc: 1443fffd bne v0,v1,bfc005f4 +bfc00600: 00000000 nop +bfc00604: 24020001 li v0,1 +bfc00608: ac820004 sw v0,4(a0) +bfc0060c: 03e00008 jr ra +bfc00610: 27bd0008 addiu sp,sp,8 + +bfc00614 : +bfc00614: 8c870000 lw a3,0(a0) +bfc00618: 3c020098 lui v0,0x98 +bfc0061c: 34420098 ori v0,v0,0x98 +bfc00620: ace20000 sw v0,0(a3) +bfc00624: 3c0200ff lui v0,0xff +bfc00628: 344200ff ori v0,v0,0xff +bfc0062c: ace20000 sw v0,0(a3) +bfc00630: 3c020090 lui v0,0x90 +bfc00634: 34420090 ori v0,v0,0x90 +bfc00638: ace20000 sw v0,0(a3) +bfc0063c: 00804021 move t0,a0 +bfc00640: 94e4009c lhu a0,156(a3) +bfc00644: 24030002 li v1,2 +bfc00648: 24020020 li v0,32 +bfc0064c: ad030008 sw v1,8(t0) +bfc00650: ad03001c sw v1,28(t0) +bfc00654: ad020018 sw v0,24(t0) +bfc00658: 3084ffff andi a0,a0,0xffff +bfc0065c: 0bf0019d j bfc00674 +bfc00660: 00001821 move v1,zero +bfc00664: 8d020008 lw v0,8(t0) +bfc00668: 00000000 nop +bfc0066c: 00021040 sll v0,v0,0x1 +bfc00670: ad020008 sw v0,8(t0) +bfc00674: 0064102b sltu v0,v1,a0 +bfc00678: 1440fffa bnez v0,bfc00664 +bfc0067c: 24630001 addiu v1,v1,1 +bfc00680: 94e200ac lhu v0,172(a3) +bfc00684: 94e300a8 lhu v1,168(a3) +bfc00688: 3042ffff andi v0,v0,0xffff +bfc0068c: 8d04001c lw a0,28(t0) +bfc00690: 3063ffff andi v1,v1,0xffff +bfc00694: 00021200 sll v0,v0,0x8 +bfc00698: 00432825 or a1,v0,v1 +bfc0069c: ad040014 sw a0,20(t0) +bfc006a0: 0bf001ae j bfc006b8 +bfc006a4: 00001821 move v1,zero +bfc006a8: 8d020014 lw v0,20(t0) +bfc006ac: 00000000 nop +bfc006b0: 00021040 sll v0,v0,0x1 +bfc006b4: ad020014 sw v0,20(t0) +bfc006b8: 0065102b sltu v0,v1,a1 +bfc006bc: 1440fffa bnez v0,bfc006a8 +bfc006c0: 24630001 addiu v1,v1,1 +bfc006c4: 94e300b8 lhu v1,184(a3) +bfc006c8: 94e600b4 lhu a2,180(a3) +bfc006cc: 94e200c0 lhu v0,192(a3) +bfc006d0: 94e400bc lhu a0,188(a3) +bfc006d4: 8d05001c lw a1,28(t0) +bfc006d8: 3042ffff andi v0,v0,0xffff +bfc006dc: 3084ffff andi a0,a0,0xffff +bfc006e0: 00021200 sll v0,v0,0x8 +bfc006e4: 00441025 or v0,v0,a0 +bfc006e8: 00052a00 sll a1,a1,0x8 +bfc006ec: 00a20018 mult a1,v0 +bfc006f0: 3063ffff andi v1,v1,0xffff +bfc006f4: 30c6ffff andi a2,a2,0xffff +bfc006f8: 00031a00 sll v1,v1,0x8 +bfc006fc: 00661825 or v1,v1,a2 +bfc00700: 24630001 addiu v1,v1,1 +bfc00704: ad030010 sw v1,16(t0) +bfc00708: 3c0300ff lui v1,0xff +bfc0070c: 346300ff ori v1,v1,0xff +bfc00710: 00001021 move v0,zero +bfc00714: 00002812 mflo a1 +bfc00718: ad05000c sw a1,12(t0) +bfc0071c: ace30000 sw v1,0(a3) +bfc00720: 03e00008 jr ra +bfc00724: 00000000 nop + +bfc00728 : +bfc00728: 8c820008 lw v0,8(a0) +bfc0072c: 8c860000 lw a2,0(a0) +bfc00730: 00021082 srl v0,v0,0x2 +bfc00734: 00a2102b sltu v0,a1,v0 +bfc00738: 14400004 bnez v0,bfc0074c +bfc0073c: 3c030090 lui v1,0x90 +bfc00740: 3c028010 lui v0,0x8010 +bfc00744: 03e00008 jr ra +bfc00748: 34420002 ori v0,v0,0x2 +bfc0074c: 8c820010 lw v0,16(a0) +bfc00750: 00000000 nop +bfc00754: 2442ffff addiu v0,v0,-1 +bfc00758: 00021400 sll v0,v0,0x10 +bfc0075c: 00a21024 and v0,a1,v0 +bfc00760: 24420002 addiu v0,v0,2 +bfc00764: 34630090 ori v1,v1,0x90 +bfc00768: 00021080 sll v0,v0,0x2 +bfc0076c: acc30000 sw v1,0(a2) +bfc00770: 00c21021 addu v0,a2,v0 +bfc00774: 8c430000 lw v1,0(v0) +bfc00778: 3c020001 lui v0,0x1 +bfc0077c: 34420001 ori v0,v0,0x1 +bfc00780: 00621824 and v1,v1,v0 +bfc00784: 3c0200ff lui v0,0xff +bfc00788: 344200ff ori v0,v0,0xff +bfc0078c: acc20000 sw v0,0(a2) +bfc00790: 03e00008 jr ra +bfc00794: 0003102b sltu v0,zero,v1 + +bfc00798 : +bfc00798: 8c820008 lw v0,8(a0) +bfc0079c: 00a01821 move v1,a1 +bfc007a0: 00021082 srl v0,v0,0x2 +bfc007a4: 00a2102b sltu v0,a1,v0 +bfc007a8: 8c850000 lw a1,0(a0) +bfc007ac: 14400003 bnez v0,bfc007bc +bfc007b0: 3c028010 lui v0,0x8010 +bfc007b4: 0bf0020c j bfc00830 +bfc007b8: 34430002 ori v1,v0,0x2 +bfc007bc: 8c820010 lw v0,16(a0) +bfc007c0: 00000000 nop +bfc007c4: 2442ffff addiu v0,v0,-1 +bfc007c8: 00021400 sll v0,v0,0x10 +bfc007cc: 00621024 and v0,v1,v0 +bfc007d0: 00021080 sll v0,v0,0x2 +bfc007d4: 00a22021 addu a0,a1,v0 +bfc007d8: 3c020020 lui v0,0x20 +bfc007dc: 34420020 ori v0,v0,0x20 +bfc007e0: ac820000 sw v0,0(a0) +bfc007e4: 3c0200d0 lui v0,0xd0 +bfc007e8: 344200d0 ori v0,v0,0xd0 +bfc007ec: ac820000 sw v0,0(a0) +bfc007f0: 3c020080 lui v0,0x80 +bfc007f4: 34430080 ori v1,v0,0x80 +bfc007f8: 8c860000 lw a2,0(a0) +bfc007fc: 00000000 nop +bfc00800: 00c31024 and v0,a2,v1 +bfc00804: 1443fffc bne v0,v1,bfc007f8 +bfc00808: 3c02002a lui v0,0x2a +bfc0080c: 3442002a ori v0,v0,0x2a +bfc00810: 00c21024 and v0,a2,v0 +bfc00814: 10400003 beqz v0,bfc00824 +bfc00818: 00001821 move v1,zero +bfc0081c: 3c029010 lui v0,0x9010 +bfc00820: 00c21825 or v1,a2,v0 +bfc00824: 3c0200ff lui v0,0xff +bfc00828: 344200ff ori v0,v0,0xff +bfc0082c: ac820000 sw v0,0(a0) +bfc00830: 03e00008 jr ra +bfc00834: 00601021 move v0,v1 + +bfc00838 : +bfc00838: 8c820008 lw v0,8(a0) +bfc0083c: 00a01821 move v1,a1 +bfc00840: 00021082 srl v0,v0,0x2 +bfc00844: 00a2102b sltu v0,a1,v0 +bfc00848: 8c850000 lw a1,0(a0) +bfc0084c: 14400003 bnez v0,bfc0085c +bfc00850: 3c028010 lui v0,0x8010 +bfc00854: 0bf00234 j bfc008d0 +bfc00858: 34430002 ori v1,v0,0x2 +bfc0085c: 8c820010 lw v0,16(a0) +bfc00860: 00000000 nop +bfc00864: 2442ffff addiu v0,v0,-1 +bfc00868: 00021400 sll v0,v0,0x10 +bfc0086c: 00621024 and v0,v1,v0 +bfc00870: 00021080 sll v0,v0,0x2 +bfc00874: 00a22021 addu a0,a1,v0 +bfc00878: 3c020060 lui v0,0x60 +bfc0087c: 34420060 ori v0,v0,0x60 +bfc00880: ac820000 sw v0,0(a0) +bfc00884: 3c020001 lui v0,0x1 +bfc00888: 34420001 ori v0,v0,0x1 +bfc0088c: ac820000 sw v0,0(a0) +bfc00890: 3c020080 lui v0,0x80 +bfc00894: 34430080 ori v1,v0,0x80 +bfc00898: 8c860000 lw a2,0(a0) +bfc0089c: 00000000 nop +bfc008a0: 00c31024 and v0,a2,v1 +bfc008a4: 1443fffc bne v0,v1,bfc00898 +bfc008a8: 3c020038 lui v0,0x38 +bfc008ac: 34420038 ori v0,v0,0x38 +bfc008b0: 00c21024 and v0,a2,v0 +bfc008b4: 10400003 beqz v0,bfc008c4 +bfc008b8: 00001821 move v1,zero +bfc008bc: 3c029010 lui v0,0x9010 +bfc008c0: 00c21825 or v1,a2,v0 +bfc008c4: 3c0200ff lui v0,0xff +bfc008c8: 344200ff ori v0,v0,0xff +bfc008cc: ac820000 sw v0,0(a0) +bfc008d0: 03e00008 jr ra +bfc008d4: 00601021 move v0,v1 + +bfc008d8 : +bfc008d8: 8c820008 lw v0,8(a0) +bfc008dc: 00a01821 move v1,a1 +bfc008e0: 00021082 srl v0,v0,0x2 +bfc008e4: 00a2102b sltu v0,a1,v0 +bfc008e8: 8c850000 lw a1,0(a0) +bfc008ec: 14400003 bnez v0,bfc008fc +bfc008f0: 3c028010 lui v0,0x8010 +bfc008f4: 0bf0025c j bfc00970 +bfc008f8: 34430002 ori v1,v0,0x2 +bfc008fc: 8c820010 lw v0,16(a0) +bfc00900: 00000000 nop +bfc00904: 2442ffff addiu v0,v0,-1 +bfc00908: 00021400 sll v0,v0,0x10 +bfc0090c: 00621024 and v0,v1,v0 +bfc00910: 00021080 sll v0,v0,0x2 +bfc00914: 00a22021 addu a0,a1,v0 +bfc00918: 3c020060 lui v0,0x60 +bfc0091c: 34420060 ori v0,v0,0x60 +bfc00920: ac820000 sw v0,0(a0) +bfc00924: 3c0200d0 lui v0,0xd0 +bfc00928: 344200d0 ori v0,v0,0xd0 +bfc0092c: ac820000 sw v0,0(a0) +bfc00930: 3c020080 lui v0,0x80 +bfc00934: 34430080 ori v1,v0,0x80 +bfc00938: 8c860000 lw a2,0(a0) +bfc0093c: 00000000 nop +bfc00940: 00c31024 and v0,a2,v1 +bfc00944: 1443fffc bne v0,v1,bfc00938 +bfc00948: 3c020038 lui v0,0x38 +bfc0094c: 34420038 ori v0,v0,0x38 +bfc00950: 00c21024 and v0,a2,v0 +bfc00954: 10400003 beqz v0,bfc00964 +bfc00958: 00001821 move v1,zero +bfc0095c: 3c029010 lui v0,0x9010 +bfc00960: 00c21825 or v1,a2,v0 +bfc00964: 3c0200ff lui v0,0xff +bfc00968: 344200ff ori v0,v0,0xff +bfc0096c: ac820000 sw v0,0(a0) +bfc00970: 03e00008 jr ra +bfc00974: 00601021 move v0,v1 + +bfc00978 : +bfc00978: 8c820008 lw v0,8(a0) +bfc0097c: 8c840000 lw a0,0(a0) +bfc00980: 00021082 srl v0,v0,0x2 +bfc00984: 00a2102b sltu v0,a1,v0 +bfc00988: 14400003 bnez v0,bfc00998 +bfc0098c: 3c028010 lui v0,0x8010 +bfc00990: 0bf0027c j bfc009f0 +bfc00994: 34430002 ori v1,v0,0x2 +bfc00998: 00051080 sll v0,a1,0x2 +bfc0099c: 00822021 addu a0,a0,v0 +bfc009a0: 3c020040 lui v0,0x40 +bfc009a4: 34420040 ori v0,v0,0x40 +bfc009a8: ac820000 sw v0,0(a0) +bfc009ac: 3c020080 lui v0,0x80 +bfc009b0: ac860000 sw a2,0(a0) +bfc009b4: 34430080 ori v1,v0,0x80 +bfc009b8: 8c860000 lw a2,0(a0) +bfc009bc: 00000000 nop +bfc009c0: 00c31024 and v0,a2,v1 +bfc009c4: 1443fffc bne v0,v1,bfc009b8 +bfc009c8: 3c02001a lui v0,0x1a +bfc009cc: 3442001a ori v0,v0,0x1a +bfc009d0: 00c21024 and v0,a2,v0 +bfc009d4: 10400003 beqz v0,bfc009e4 +bfc009d8: 00001821 move v1,zero +bfc009dc: 3c029010 lui v0,0x9010 +bfc009e0: 00c21825 or v1,a2,v0 +bfc009e4: 3c0200ff lui v0,0xff +bfc009e8: 344200ff ori v0,v0,0xff +bfc009ec: ac820000 sw v0,0(a0) +bfc009f0: 03e00008 jr ra +bfc009f4: 00601021 move v0,v1 + +bfc009f8 : +bfc009f8: 8c820008 lw v0,8(a0) +bfc009fc: 27bdffe8 addiu sp,sp,-24 +bfc00a00: 00021082 srl v0,v0,0x2 +bfc00a04: 00a2102b sltu v0,a1,v0 +bfc00a08: afb40014 sw s4,20(sp) +bfc00a0c: afb30010 sw s3,16(sp) +bfc00a10: afb2000c sw s2,12(sp) +bfc00a14: afb10008 sw s1,8(sp) +bfc00a18: afb00004 sw s0,4(sp) +bfc00a1c: 0080c021 move t8,a0 +bfc00a20: 8c8e0000 lw t6,0(a0) +bfc00a24: 14400004 bnez v0,bfc00a38 +bfc00a28: 00c0a021 move s4,a2 +bfc00a2c: 3c028010 lui v0,0x8010 +bfc00a30: 0bf002e3 j bfc00b8c +bfc00a34: 34440002 ori a0,v0,0x2 +bfc00a38: 8c820010 lw v0,16(a0) +bfc00a3c: 00006821 move t5,zero +bfc00a40: 2442ffff addiu v0,v0,-1 +bfc00a44: 0002cc00 sll t9,v0,0x10 +bfc00a48: 3c0200e8 lui v0,0xe8 +bfc00a4c: 345300e8 ori s3,v0,0xe8 +bfc00a50: 3c020080 lui v0,0x80 +bfc00a54: 344f0080 ori t7,v0,0x80 +bfc00a58: 3c02001a lui v0,0x1a +bfc00a5c: 3446001a ori a2,v0,0x1a +bfc00a60: 3c0200d0 lui v0,0xd0 +bfc00a64: 345200d0 ori s2,v0,0xd0 +bfc00a68: 3c0200ff lui v0,0xff +bfc00a6c: 345100ff ori s1,v0,0xff +bfc00a70: 0bf002e1 j bfc00b84 +bfc00a74: 3c100001 lui s0,0x1 +bfc00a78: 01851023 subu v0,t4,a1 +bfc00a7c: 00505021 addu t2,v0,s0 +bfc00a80: 00ea102b sltu v0,a3,t2 +bfc00a84: 10400002 beqz v0,bfc00a90 +bfc00a88: 000c1080 sll v0,t4,0x2 +bfc00a8c: 00e05021 move t2,a3 +bfc00a90: 0bf002d7 j bfc00b5c +bfc00a94: 01c25821 addu t3,t6,v0 +bfc00a98: ad730000 sw s3,0(t3) +bfc00a9c: 8d630000 lw v1,0(t3) +bfc00aa0: 00000000 nop +bfc00aa4: 006f1024 and v0,v1,t7 +bfc00aa8: 144ffffc bne v0,t7,bfc00a9c +bfc00aac: 00661024 and v0,v1,a2 +bfc00ab0: 14400026 bnez v0,bfc00b4c +bfc00ab4: 3c029010 lui v0,0x9010 +bfc00ab8: 8f020014 lw v0,20(t8) +bfc00abc: 00000000 nop +bfc00ac0: 00021882 srl v1,v0,0x2 +bfc00ac4: 006a102b sltu v0,v1,t2 +bfc00ac8: 10400002 beqz v0,bfc00ad4 +bfc00acc: 01404021 move t0,t2 +bfc00ad0: 00604021 move t0,v1 +bfc00ad4: 2503ffff addiu v1,t0,-1 +bfc00ad8: 00031400 sll v0,v1,0x10 +bfc00adc: 00431025 or v0,v0,v1 +bfc00ae0: 00052080 sll a0,a1,0x2 +bfc00ae4: 000d1880 sll v1,t5,0x2 +bfc00ae8: 02834821 addu t1,s4,v1 +bfc00aec: ad620000 sw v0,0(t3) +bfc00af0: 01c42021 addu a0,t6,a0 +bfc00af4: 0bf002c3 j bfc00b0c +bfc00af8: 00001821 move v1,zero +bfc00afc: 8d220000 lw v0,0(t1) +bfc00b00: 25290004 addiu t1,t1,4 +bfc00b04: ac820000 sw v0,0(a0) +bfc00b08: 24840004 addiu a0,a0,4 +bfc00b0c: 0068102b sltu v0,v1,t0 +bfc00b10: 1440fffa bnez v0,bfc00afc +bfc00b14: 24630001 addiu v1,v1,1 +bfc00b18: 01a86821 addu t5,t5,t0 +bfc00b1c: 00a82821 addu a1,a1,t0 +bfc00b20: 00e83823 subu a3,a3,t0 +bfc00b24: ad720000 sw s2,0(t3) +bfc00b28: 8d630000 lw v1,0(t3) +bfc00b2c: 00000000 nop +bfc00b30: 006f1024 and v0,v1,t7 +bfc00b34: 144ffffc bne v0,t7,bfc00b28 +bfc00b38: 00661024 and v0,v1,a2 +bfc00b3c: 10400005 beqz v0,bfc00b54 +bfc00b40: 01485023 subu t2,t2,t0 +bfc00b44: 01485021 addu t2,t2,t0 +bfc00b48: 3c029010 lui v0,0x9010 +bfc00b4c: 0bf002d9 j bfc00b64 +bfc00b50: 00622025 or a0,v1,v0 +bfc00b54: ad710000 sw s1,0(t3) +bfc00b58: 00002021 move a0,zero +bfc00b5c: 1540ffce bnez t2,bfc00a98 +bfc00b60: 00000000 nop +bfc00b64: 04810007 bgez a0,bfc00b84 +bfc00b68: 000c1880 sll v1,t4,0x2 +bfc00b6c: 3c0200ff lui v0,0xff +bfc00b70: 01c31821 addu v1,t6,v1 +bfc00b74: 344200ff ori v0,v0,0xff +bfc00b78: ac620000 sw v0,0(v1) +bfc00b7c: 0bf002e4 j bfc00b90 +bfc00b80: 00801021 move v0,a0 +bfc00b84: 14e0ffbc bnez a3,bfc00a78 +bfc00b88: 00b96024 and t4,a1,t9 +bfc00b8c: 00801021 move v0,a0 +bfc00b90: 8fb40014 lw s4,20(sp) +bfc00b94: 8fb30010 lw s3,16(sp) +bfc00b98: 8fb2000c lw s2,12(sp) +bfc00b9c: 8fb10008 lw s1,8(sp) +bfc00ba0: 8fb00004 lw s0,4(sp) +bfc00ba4: 03e00008 jr ra +bfc00ba8: 27bd0018 addiu sp,sp,24 + +bfc00bac : +bfc00bac: 27bdffe0 addiu sp,sp,-32 +bfc00bb0: afbf001c sw ra,28(sp) +bfc00bb4: ac850000 sw a1,0(a0) +bfc00bb8: 24820008 addiu v0,a0,8 +bfc00bbc: 0bf002f3 j bfc00bcc +bfc00bc0: 24830020 addiu v1,a0,32 +bfc00bc4: a0400000 sb zero,0(v0) +bfc00bc8: 24420001 addiu v0,v0,1 +bfc00bcc: 1443fffd bne v0,v1,bfc00bc4 +bfc00bd0: 00000000 nop +bfc00bd4: 3c021234 lui v0,0x1234 +bfc00bd8: 34425678 ori v0,v0,0x5678 +bfc00bdc: 00021e02 srl v1,v0,0x18 +bfc00be0: afa20010 sw v0,16(sp) +bfc00be4: 24020012 li v0,18 +bfc00be8: 14620003 bne v1,v0,bfc00bf8 +bfc00bec: ac800004 sw zero,4(a0) +bfc00bf0: 24020001 li v0,1 +bfc00bf4: ac820004 sw v0,4(a0) +bfc00bf8: 0ff00185 jal bfc00614 +bfc00bfc: 00000000 nop +bfc00c00: 8fbf001c lw ra,28(sp) +bfc00c04: 00000000 nop +bfc00c08: 03e00008 jr ra +bfc00c0c: 27bd0020 addiu sp,sp,32 + +bfc00c10 : +bfc00c10: 27bdffd8 addiu sp,sp,-40 +bfc00c14: 30c20003 andi v0,a2,0x3 +bfc00c18: afb2001c sw s2,28(sp) +bfc00c1c: afbf0024 sw ra,36(sp) +bfc00c20: afb30020 sw s3,32(sp) +bfc00c24: afb10018 sw s1,24(sp) +bfc00c28: afb00014 sw s0,20(sp) +bfc00c2c: 10400004 beqz v0,bfc00c40 +bfc00c30: 00809021 move s2,a0 +bfc00c34: 00061082 srl v0,a2,0x2 +bfc00c38: 24420001 addiu v0,v0,1 +bfc00c3c: 00023080 sll a2,v0,0x2 +bfc00c40: 00c59821 addu s3,a2,a1 +bfc00c44: 0bf00324 j bfc00c90 +bfc00c48: 00a08821 move s1,a1 +bfc00c4c: 0ff001ca jal bfc00728 +bfc00c50: 00000000 nop +bfc00c54: 02402021 move a0,s2 +bfc00c58: 10400005 beqz v0,bfc00c70 +bfc00c5c: 02002821 move a1,s0 +bfc00c60: 0ff00236 jal bfc008d8 +bfc00c64: 00000000 nop +bfc00c68: 04400011 bltz v0,bfc00cb0 +bfc00c6c: 00401821 move v1,v0 +bfc00c70: 02002821 move a1,s0 +bfc00c74: 0ff001e6 jal bfc00798 +bfc00c78: 02402021 move a0,s2 +bfc00c7c: 0440000c bltz v0,bfc00cb0 +bfc00c80: 00401821 move v1,v0 +bfc00c84: 8e42000c lw v0,12(s2) +bfc00c88: 00000000 nop +bfc00c8c: 02228821 addu s1,s1,v0 +bfc00c90: 001117c3 sra v0,s1,0x1f +bfc00c94: 00021782 srl v0,v0,0x1e +bfc00c98: 00511021 addu v0,v0,s1 +bfc00c9c: 00028083 sra s0,v0,0x2 +bfc00ca0: 0233102b sltu v0,s1,s3 +bfc00ca4: 02402021 move a0,s2 +bfc00ca8: 1440ffe8 bnez v0,bfc00c4c +bfc00cac: 02002821 move a1,s0 +bfc00cb0: 8fbf0024 lw ra,36(sp) +bfc00cb4: 00601021 move v0,v1 +bfc00cb8: 8fb30020 lw s3,32(sp) +bfc00cbc: 8fb2001c lw s2,28(sp) +bfc00cc0: 8fb10018 lw s1,24(sp) +bfc00cc4: 8fb00014 lw s0,20(sp) +bfc00cc8: 03e00008 jr ra +bfc00ccc: 27bd0028 addiu sp,sp,40 + +bfc00cd0 : +bfc00cd0: 30e20003 andi v0,a3,0x3 +bfc00cd4: 10400003 beqz v0,bfc00ce4 +bfc00cd8: 00071082 srl v0,a3,0x2 +bfc00cdc: 24420001 addiu v0,v0,1 +bfc00ce0: 00023880 sll a3,v0,0x2 +bfc00ce4: 00052882 srl a1,a1,0x2 +bfc00ce8: 0bf0027e j bfc009f8 +bfc00cec: 00073882 srl a3,a3,0x2 + +bfc00cf0 : +bfc00cf0: 8c820000 lw v0,0(a0) +bfc00cf4: 00002021 move a0,zero +bfc00cf8: 0bf00347 j bfc00d1c +bfc00cfc: 00454021 addu t0,v0,a1 +bfc00d00: 90630000 lbu v1,0(v1) +bfc00d04: 90a20000 lbu v0,0(a1) +bfc00d08: 00000000 nop +bfc00d0c: 10620003 beq v1,v0,bfc00d1c +bfc00d10: 3c028010 lui v0,0x8010 +bfc00d14: 03e00008 jr ra +bfc00d18: 34420003 ori v0,v0,0x3 +bfc00d1c: 0087102b sltu v0,a0,a3 +bfc00d20: 01041821 addu v1,t0,a0 +bfc00d24: 00c42821 addu a1,a2,a0 +bfc00d28: 1440fff5 bnez v0,bfc00d00 +bfc00d2c: 24840001 addiu a0,a0,1 +bfc00d30: 03e00008 jr ra +bfc00d34: 00000000 nop + +bfc00d38 : +bfc00d38: 8c82000c lw v0,12(a0) +bfc00d3c: 00000000 nop +bfc00d40: 14400002 bnez v0,bfc00d4c +bfc00d44: 00a2001b divu zero,a1,v0 +bfc00d48: 0007000d break 0x7 +bfc00d4c: 00001010 mfhi v0 +bfc00d50: 0002102b sltu v0,zero,v0 +bfc00d54: 00002812 mflo a1 +bfc00d58: 03e00008 jr ra +bfc00d5c: 00a21021 addu v0,a1,v0 + +bfc00d60 : +bfc00d60: 8c830010 lw v1,16(a0) +bfc00d64: 00000000 nop +bfc00d68: 00a3102b sltu v0,a1,v1 +bfc00d6c: 14400002 bnez v0,bfc00d78 +bfc00d70: 00000000 nop +bfc00d74: 2465ffff addiu a1,v1,-1 +bfc00d78: 8c82000c lw v0,12(a0) +bfc00d7c: 00000000 nop +bfc00d80: 00a20018 mult a1,v0 +bfc00d84: 00001012 mflo v0 +bfc00d88: 03e00008 jr ra +bfc00d8c: 00000000 nop + +bfc00d90 : +bfc00d90: 27bdffe8 addiu sp,sp,-24 +bfc00d94: afbf0014 sw ra,20(sp) +bfc00d98: afb00010 sw s0,16(sp) +bfc00d9c: 0ff0034e jal bfc00d38 +bfc00da0: 00808021 move s0,a0 +bfc00da4: 8e03000c lw v1,12(s0) +bfc00da8: 8fbf0014 lw ra,20(sp) +bfc00dac: 00430018 mult v0,v1 +bfc00db0: 8fb00010 lw s0,16(sp) +bfc00db4: 00001012 mflo v0 +bfc00db8: 03e00008 jr ra +bfc00dbc: 27bd0018 addiu sp,sp,24 + +bfc00dc0 : +bfc00dc0: 90830000 lbu v1,0(a0) +bfc00dc4: 00000000 nop +bfc00dc8: 2c620041 sltiu v0,v1,65 +bfc00dcc: 14400002 bnez v0,bfc00dd8 +bfc00dd0: 2462ffd0 addiu v0,v1,-48 +bfc00dd4: 2462ffc9 addiu v0,v1,-55 +bfc00dd8: 90840001 lbu a0,1(a0) +bfc00ddc: 304200ff andi v0,v0,0xff +bfc00de0: 304300ff andi v1,v0,0xff +bfc00de4: 2c820041 sltiu v0,a0,65 +bfc00de8: 14400003 bnez v0,bfc00df8 +bfc00dec: 00000000 nop +bfc00df0: 0bf0037f j bfc00dfc +bfc00df4: 2482ffc9 addiu v0,a0,-55 +bfc00df8: 2482ffd0 addiu v0,a0,-48 +bfc00dfc: 304400ff andi a0,v0,0xff +bfc00e00: 00031100 sll v0,v1,0x4 +bfc00e04: 00821025 or v0,a0,v0 +bfc00e08: 03e00008 jr ra +bfc00e0c: 304200ff andi v0,v0,0xff + +bfc00e10 : +bfc00e10: 10c00094 beqz a2,bfc01064 +bfc00e14: 00805021 move t2,a0 +bfc00e18: 24020003 li v0,3 +bfc00e1c: ac820008 sw v0,8(a0) +bfc00e20: 90a40001 lbu a0,1(a1) +bfc00e24: 00000000 nop +bfc00e28: 2482ffcf addiu v0,a0,-49 +bfc00e2c: 304200ff andi v0,v0,0xff +bfc00e30: 2c420003 sltiu v0,v0,3 +bfc00e34: 10400005 beqz v0,bfc00e4c +bfc00e38: 2482ffc9 addiu v0,a0,-55 +bfc00e3c: 24020002 li v0,2 +bfc00e40: ad420008 sw v0,8(t2) +bfc00e44: 0bf003a1 j bfc00e84 +bfc00e48: 2489ffd1 addiu t1,a0,-47 +bfc00e4c: 304200ff andi v0,v0,0xff +bfc00e50: 2c420003 sltiu v0,v0,3 +bfc00e54: 10400006 beqz v0,bfc00e70 +bfc00e58: 24020030 li v0,48 +bfc00e5c: 2402003b li v0,59 +bfc00e60: 00444823 subu t1,v0,a0 +bfc00e64: 24020004 li v0,4 +bfc00e68: 0bf003a1 j bfc00e84 +bfc00e6c: ad420008 sw v0,8(t2) +bfc00e70: 14820004 bne a0,v0,bfc00e84 +bfc00e74: 00004821 move t1,zero +bfc00e78: 24020001 li v0,1 +bfc00e7c: ad420008 sw v0,8(t2) +bfc00e80: 24090002 li t1,2 +bfc00e84: 90a30002 lbu v1,2(a1) +bfc00e88: 00000000 nop +bfc00e8c: 2c620041 sltiu v0,v1,65 +bfc00e90: 10400003 beqz v0,bfc00ea0 +bfc00e94: 24a40002 addiu a0,a1,2 +bfc00e98: 0bf003a9 j bfc00ea4 +bfc00e9c: 2462ffd0 addiu v0,v1,-48 +bfc00ea0: 2462ffc9 addiu v0,v1,-55 +bfc00ea4: 90830001 lbu v1,1(a0) +bfc00ea8: 304200ff andi v0,v0,0xff +bfc00eac: 304400ff andi a0,v0,0xff +bfc00eb0: 2c620041 sltiu v0,v1,65 +bfc00eb4: 10400002 beqz v0,bfc00ec0 +bfc00eb8: 2462ffc9 addiu v0,v1,-55 +bfc00ebc: 2462ffd0 addiu v0,v1,-48 +bfc00ec0: 304300ff andi v1,v0,0xff +bfc00ec4: 00041100 sll v0,a0,0x4 +bfc00ec8: 00621025 or v0,v1,v0 +bfc00ecc: 304200ff andi v0,v0,0xff +bfc00ed0: ad420004 sw v0,4(t2) +bfc00ed4: ad400000 sw zero,0(t2) +bfc00ed8: 00405821 move t3,v0 +bfc00edc: 00a03021 move a2,a1 +bfc00ee0: 0bf003d5 j bfc00f54 +bfc00ee4: 00003821 move a3,zero +bfc00ee8: 90c20004 lbu v0,4(a2) +bfc00eec: 00000000 nop +bfc00ef0: 2443ffc9 addiu v1,v0,-55 +bfc00ef4: 2444ffd0 addiu a0,v0,-48 +bfc00ef8: 2c420041 sltiu v0,v0,65 +bfc00efc: 10400002 beqz v0,bfc00f08 +bfc00f00: 306300ff andi v1,v1,0xff +bfc00f04: 308300ff andi v1,a0,0xff +bfc00f08: 90c20005 lbu v0,5(a2) +bfc00f0c: 306800ff andi t0,v1,0xff +bfc00f10: 2444ffc9 addiu a0,v0,-55 +bfc00f14: 2443ffd0 addiu v1,v0,-48 +bfc00f18: 2c420041 sltiu v0,v0,65 +bfc00f1c: 10400002 beqz v0,bfc00f28 +bfc00f20: 308400ff andi a0,a0,0xff +bfc00f24: 306400ff andi a0,v1,0xff +bfc00f28: 8d430000 lw v1,0(t2) +bfc00f2c: 00081100 sll v0,t0,0x4 +bfc00f30: 00821025 or v0,a0,v0 +bfc00f34: 304200ff andi v0,v0,0xff +bfc00f38: 00031a00 sll v1,v1,0x8 +bfc00f3c: 004b2021 addu a0,v0,t3 +bfc00f40: 00431025 or v0,v0,v1 +bfc00f44: ad420000 sw v0,0(t2) +bfc00f48: 308b00ff andi t3,a0,0xff +bfc00f4c: 24e70001 addiu a3,a3,1 +bfc00f50: 24c60002 addiu a2,a2,2 +bfc00f54: 00e9102a slt v0,a3,t1 +bfc00f58: 1440ffe3 bnez v0,bfc00ee8 +bfc00f5c: 25220002 addiu v0,t1,2 +bfc00f60: 8d440004 lw a0,4(t2) +bfc00f64: 00021040 sll v0,v0,0x1 +bfc00f68: 00091827 nor v1,zero,t1 +bfc00f6c: 00832021 addu a0,a0,v1 +bfc00f70: 00a21021 addu v0,a1,v0 +bfc00f74: ad440004 sw a0,4(t2) +bfc00f78: ad42000c sw v0,12(t2) +bfc00f7c: 0bf003f9 j bfc00fe4 +bfc00f80: 00003021 move a2,zero +bfc00f84: 90e20000 lbu v0,0(a3) +bfc00f88: 00000000 nop +bfc00f8c: 2444ffc9 addiu a0,v0,-55 +bfc00f90: 2445ffd0 addiu a1,v0,-48 +bfc00f94: 2c420041 sltiu v0,v0,65 +bfc00f98: 10400002 beqz v0,bfc00fa4 +bfc00f9c: 308400ff andi a0,a0,0xff +bfc00fa0: 30a400ff andi a0,a1,0xff +bfc00fa4: 90e20001 lbu v0,1(a3) +bfc00fa8: 308700ff andi a3,a0,0xff +bfc00fac: 2445ffc9 addiu a1,v0,-55 +bfc00fb0: 2444ffd0 addiu a0,v0,-48 +bfc00fb4: 2c420041 sltiu v0,v0,65 +bfc00fb8: 14400002 bnez v0,bfc00fc4 +bfc00fbc: 308400ff andi a0,a0,0xff +bfc00fc0: 30a400ff andi a0,a1,0xff +bfc00fc4: 00071100 sll v0,a3,0x4 +bfc00fc8: 00821025 or v0,a0,v0 +bfc00fcc: 304200ff andi v0,v0,0xff +bfc00fd0: 00661821 addu v1,v1,a2 +bfc00fd4: 004b2021 addu a0,v0,t3 +bfc00fd8: a0620000 sb v0,0(v1) +bfc00fdc: 308b00ff andi t3,a0,0xff +bfc00fe0: 24c60001 addiu a2,a2,1 +bfc00fe4: 8d420004 lw v0,4(t2) +bfc00fe8: 8d43000c lw v1,12(t2) +bfc00fec: 00062040 sll a0,a2,0x1 +bfc00ff0: 00c2102a slt v0,a2,v0 +bfc00ff4: 1440ffe3 bnez v0,bfc00f84 +bfc00ff8: 00643821 addu a3,v1,a0 +bfc00ffc: 90e40000 lbu a0,0(a3) +bfc01000: 00000000 nop +bfc01004: 2c820041 sltiu v0,a0,65 +bfc01008: 10400003 beqz v0,bfc01018 +bfc0100c: 00e01821 move v1,a3 +bfc01010: 0bf00407 j bfc0101c +bfc01014: 2482ffd0 addiu v0,a0,-48 +bfc01018: 2482ffc9 addiu v0,a0,-55 +bfc0101c: 90630001 lbu v1,1(v1) +bfc01020: 304200ff andi v0,v0,0xff +bfc01024: 304400ff andi a0,v0,0xff +bfc01028: 2c620041 sltiu v0,v1,65 +bfc0102c: 10400002 beqz v0,bfc01038 +bfc01030: 2462ffc9 addiu v0,v1,-55 +bfc01034: 2462ffd0 addiu v0,v1,-48 +bfc01038: 304200ff andi v0,v0,0xff +bfc0103c: 00041900 sll v1,a0,0x4 +bfc01040: 00431825 or v1,v0,v1 +bfc01044: 000b1027 nor v0,zero,t3 +bfc01048: 304200ff andi v0,v0,0xff +bfc0104c: 306300ff andi v1,v1,0xff +bfc01050: 14430004 bne v0,v1,bfc01064 +bfc01054: 00000000 nop +bfc01058: 8d420008 lw v0,8(t2) +bfc0105c: 03e00008 jr ra +bfc01060: 00000000 nop +bfc01064: 03e00008 jr ra +bfc01068: 00001021 move v0,zero + +bfc0106c : +bfc0106c: 00800008 jr a0 +bfc01070: 00000000 nop +bfc01074: 03e00008 jr ra +bfc01078: 00000000 nop + +bfc0107c : +bfc0107c: 3c1a1000 lui k0,0x1000 +bfc01080: 409a6000 mtc0 k0,c0_sr +bfc01084: 00800008 jr a0 +bfc01088: 42000010 rfe +bfc0108c: 03e00008 jr ra +bfc01090: 00000000 nop + +bfc01094 : +bfc01094: 401a6000 mfc0 k0,c0_sr +bfc01098: 3c1bffbf lui k1,0xffbf +bfc0109c: 377bffff ori k1,k1,0xffff +bfc010a0: 035bd024 and k0,k0,k1 +bfc010a4: 3c1b0200 lui k1,0x200 +bfc010a8: 035bd025 or k0,k0,k1 +bfc010ac: 409a6000 mtc0 k0,c0_sr +bfc010b0: 00800008 jr a0 +bfc010b4: 42000010 rfe +bfc010b8: 03e00008 jr ra +bfc010bc: 00000000 nop + +bfc010c0 : +bfc010c0: 27bdffd8 addiu sp,sp,-40 +bfc010c4: afb30020 sw s3,32(sp) +bfc010c8: afb10018 sw s1,24(sp) +bfc010cc: afb00014 sw s0,20(sp) +bfc010d0: afbf0024 sw ra,36(sp) +bfc010d4: afb2001c sw s2,28(sp) +bfc010d8: 00809821 move s3,a0 +bfc010dc: 24110073 li s1,115 +bfc010e0: 24100053 li s0,83 +bfc010e4: 0ff00081 jal bfc00204 +bfc010e8: 00000000 nop +bfc010ec: 14510005 bne v0,s1,bfc01104 +bfc010f0: 00000000 nop +bfc010f4: 00008021 move s0,zero +bfc010f8: 2412000a li s2,10 +bfc010fc: 0bf00449 j bfc01124 +bfc01100: 2411000d li s1,13 +bfc01104: 1450fff7 bne v0,s0,bfc010e4 +bfc01108: 00000000 nop +bfc0110c: 0bf0043e j bfc010f8 +bfc01110: 00008021 move s0,zero +bfc01114: 0ff00081 jal bfc00204 +bfc01118: a0620000 sb v0,0(v1) +bfc0111c: 10510003 beq v0,s1,bfc0112c +bfc01120: 26100001 addiu s0,s0,1 +bfc01124: 1452fffb bne v0,s2,bfc01114 +bfc01128: 02701821 addu v1,s3,s0 +bfc0112c: 8fbf0024 lw ra,36(sp) +bfc01130: 02001021 move v0,s0 +bfc01134: 8fb30020 lw s3,32(sp) +bfc01138: 8fb2001c lw s2,28(sp) +bfc0113c: 8fb10018 lw s1,24(sp) +bfc01140: 8fb00014 lw s0,20(sp) +bfc01144: 03e00008 jr ra +bfc01148: 27bd0028 addiu sp,sp,40 + +bfc0114c
: +bfc0114c: 27bdfd98 addiu sp,sp,-616 +bfc01150: 27a40140 addiu a0,sp,320 +bfc01154: 00002821 move a1,zero +bfc01158: 24060100 li a2,256 +bfc0115c: afb20248 sw s2,584(sp) +bfc01160: afb10244 sw s1,580(sp) +bfc01164: afb00240 sw s0,576(sp) +bfc01168: 3c11a000 lui s1,0xa000 +bfc0116c: afbf0264 sw ra,612(sp) +bfc01170: afbe0260 sw s8,608(sp) +bfc01174: afb7025c sw s7,604(sp) +bfc01178: afb60258 sw s6,600(sp) +bfc0117c: afb50254 sw s5,596(sp) +bfc01180: afb40250 sw s4,592(sp) +bfc01184: 0ff0056b jal bfc015ac +bfc01188: afb3024c sw s3,588(sp) +bfc0118c: 3c036000 lui v1,0x6000 +bfc01190: 36220004 ori v0,s1,0x4 +bfc01194: 3463b1ff ori v1,v1,0xb1ff +bfc01198: ac430000 sw v1,0(v0) +bfc0119c: 3c022000 lui v0,0x2000 +bfc011a0: 27b20020 addiu s2,sp,32 +bfc011a4: 34421000 ori v0,v0,0x1000 +bfc011a8: ae220000 sw v0,0(s1) +bfc011ac: 02402021 move a0,s2 +bfc011b0: 3c05a400 lui a1,0xa400 +bfc011b4: 8e300000 lw s0,0(s1) +bfc011b8: 0ff002eb jal bfc00bac +bfc011bc: 00000000 nop +bfc011c0: 04410004 bgez v0,bfc011d4 +bfc011c4: 00102c02 srl a1,s0,0x10 +bfc011c8: 3c04bfc0 lui a0,0xbfc0 +bfc011cc: 0bf00494 j bfc01250 +bfc011d0: 248416a4 addiu a0,a0,5796 +bfc011d4: 02402021 move a0,s2 +bfc011d8: 0ff00358 jal bfc00d60 +bfc011dc: 30a5007f andi a1,a1,0x7f +bfc011e0: 00409021 move s2,v0 +bfc011e4: 8e220000 lw v0,0(s1) +bfc011e8: 00000000 nop +bfc011ec: 00021602 srl v0,v0,0x18 +bfc011f0: 30420008 andi v0,v0,0x8 +bfc011f4: 14400044 bnez v0,bfc01308 +bfc011f8: 3c11bfc0 lui s1,0xbfc0 +bfc011fc: 0ff000b0 jal bfc002c0 +bfc01200: 26241758 addiu a0,s1,5976 +bfc01204: 3c02a400 lui v0,0xa400 +bfc01208: 02428021 addu s0,s2,v0 +bfc0120c: 8e030000 lw v1,0(s0) +bfc01210: 3c023149 lui v0,0x3149 +bfc01214: 3442464a ori v0,v0,0x464a +bfc01218: 10620011 beq v1,v0,bfc01260 +bfc0121c: 3c024a46 lui v0,0x4a46 +bfc01220: 34424931 ori v0,v0,0x4931 +bfc01224: 1062000e beq v1,v0,bfc01260 +bfc01228: 00000000 nop +bfc0122c: 0ff000b0 jal bfc002c0 +bfc01230: 26241758 addiu a0,s1,5976 +bfc01234: 3c04bfc0 lui a0,0xbfc0 +bfc01238: 0ff000b0 jal bfc002c0 +bfc0123c: 248416cc addiu a0,a0,5836 +bfc01240: 0ff000e8 jal bfc003a0 +bfc01244: 02402021 move a0,s2 +bfc01248: 3c04bfc0 lui a0,0xbfc0 +bfc0124c: 248416e4 addiu a0,a0,5860 +bfc01250: 0ff000b0 jal bfc002c0 +bfc01254: 00000000 nop +bfc01258: 0bf0055f j bfc0157c +bfc0125c: 24020001 li v0,1 +bfc01260: 3c04bfc0 lui a0,0xbfc0 +bfc01264: 0ff000b0 jal bfc002c0 +bfc01268: 248416f0 addiu a0,a0,5872 +bfc0126c: 0ff000e8 jal bfc003a0 +bfc01270: 02402021 move a0,s2 +bfc01274: 3c04bfc0 lui a0,0xbfc0 +bfc01278: 0ff000b0 jal bfc002c0 +bfc0127c: 24841714 addiu a0,a0,5908 +bfc01280: 8e02000c lw v0,12(s0) +bfc01284: 8e110004 lw s1,4(s0) +bfc01288: 00024082 srl t0,v0,0x2 +bfc0128c: 8e070008 lw a3,8(s0) +bfc01290: 00002021 move a0,zero +bfc01294: 0bf004aa j bfc012a8 +bfc01298: 00001821 move v1,zero +bfc0129c: 8cc20000 lw v0,0(a2) +bfc012a0: 00000000 nop +bfc012a4: aca20000 sw v0,0(a1) +bfc012a8: 0088102b sltu v0,a0,t0 +bfc012ac: 00673021 addu a2,v1,a3 +bfc012b0: 00712821 addu a1,v1,s1 +bfc012b4: 24840001 addiu a0,a0,1 +bfc012b8: 1440fff8 bnez v0,bfc0129c +bfc012bc: 24630004 addiu v1,v1,4 +bfc012c0: 3c04bfc0 lui a0,0xbfc0 +bfc012c4: 0ff000b0 jal bfc002c0 +bfc012c8: 2484171c addiu a0,a0,5916 +bfc012cc: 3c04bfc0 lui a0,0xbfc0 +bfc012d0: 0ff000b0 jal bfc002c0 +bfc012d4: 24841724 addiu a0,a0,5924 +bfc012d8: 8e040004 lw a0,4(s0) +bfc012dc: 0ff000e8 jal bfc003a0 +bfc012e0: 00000000 nop +bfc012e4: 3c04bfc0 lui a0,0xbfc0 +bfc012e8: 0ff000b0 jal bfc002c0 +bfc012ec: 24841758 addiu a0,a0,5976 +bfc012f0: 3c1a1000 lui k0,0x1000 +bfc012f4: 409a6000 mtc0 k0,c0_sr +bfc012f8: 02200008 jr s1 +bfc012fc: 42000010 rfe +bfc01300: 0bf0055f j bfc0157c +bfc01304: 00001021 move v0,zero +bfc01308: 0ff000b0 jal bfc002c0 +bfc0130c: 26241758 addiu a0,s1,5976 +bfc01310: 3c04bfc0 lui a0,0xbfc0 +bfc01314: 0ff000b0 jal bfc002c0 +bfc01318: 24841730 addiu a0,a0,5936 +bfc0131c: 3c024000 lui v0,0x4000 +bfc01320: 3c034010 lui v1,0x4010 +bfc01324: ac400000 sw zero,0(v0) +bfc01328: 24420004 addiu v0,v0,4 +bfc0132c: 1443fffd bne v0,v1,bfc01324 +bfc01330: 00009821 move s3,zero +bfc01334: 3c02bfc0 lui v0,0xbfc0 +bfc01338: 245516c8 addiu s5,v0,5832 +bfc0133c: 3c02bfc0 lui v0,0xbfc0 +bfc01340: 2456171c addiu s6,v0,5916 +bfc01344: 3c02bfc0 lui v0,0xbfc0 +bfc01348: 245e17d0 addiu s8,v0,6096 +bfc0134c: 3c02bfc0 lui v0,0xbfc0 +bfc01350: 245717f0 addiu s7,v0,6128 +bfc01354: 3c04bfc0 lui a0,0xbfc0 +bfc01358: 0ff000b0 jal bfc002c0 +bfc0135c: 24841750 addiu a0,a0,5968 +bfc01360: 3c14bfc0 lui s4,0xbfc0 +bfc01364: 27b00040 addiu s0,sp,64 +bfc01368: 0ff00430 jal bfc010c0 +bfc0136c: 02002021 move a0,s0 +bfc01370: 00403021 move a2,v0 +bfc01374: 02002821 move a1,s0 +bfc01378: 27a40010 addiu a0,sp,16 +bfc0137c: 0ff00384 jal bfc00e10 +bfc01380: 00408821 move s1,v0 +bfc01384: 00401821 move v1,v0 +bfc01388: 24020002 li v0,2 +bfc0138c: 10620005 beq v1,v0,bfc013a4 +bfc01390: 24020004 li v0,4 +bfc01394: 1462ffef bne v1,v0,bfc01354 +bfc01398: 00000000 nop +bfc0139c: 0bf004fe j bfc013f8 +bfc013a0: 3c04bfc0 lui a0,0xbfc0 +bfc013a4: 8fa50010 lw a1,16(sp) +bfc013a8: 8fa60014 lw a2,20(sp) +bfc013ac: 0bf004f3 j bfc013cc +bfc013b0: 00001821 move v1,zero +bfc013b4: 8fa2001c lw v0,28(sp) +bfc013b8: 00000000 nop +bfc013bc: 00431021 addu v0,v0,v1 +bfc013c0: 90420000 lbu v0,0(v0) +bfc013c4: 24630001 addiu v1,v1,1 +bfc013c8: a0820000 sb v0,0(a0) +bfc013cc: 8fa20014 lw v0,20(sp) +bfc013d0: 00000000 nop +bfc013d4: 0062102b sltu v0,v1,v0 +bfc013d8: 1440fff6 bnez v0,bfc013b4 +bfc013dc: 00652021 addu a0,v1,a1 +bfc013e0: 00c51821 addu v1,a2,a1 +bfc013e4: 0263102b sltu v0,s3,v1 +bfc013e8: 10400060 beqz v0,bfc0156c +bfc013ec: 02208021 move s0,s1 +bfc013f0: 0bf0055b j bfc0156c +bfc013f4: 00609821 move s3,v1 +bfc013f8: 0ff000b0 jal bfc002c0 +bfc013fc: 24841754 addiu a0,a0,5972 +bfc01400: 8fa60010 lw a2,16(sp) +bfc01404: 26470100 addiu a3,s2,256 +bfc01408: 02661823 subu v1,s3,a2 +bfc0140c: 27b10020 addiu s1,sp,32 +bfc01410: 3c024a46 lui v0,0x4a46 +bfc01414: 00e32821 addu a1,a3,v1 +bfc01418: 02202021 move a0,s1 +bfc0141c: 34424931 ori v0,v0,0x4931 +bfc01420: afa60144 sw a2,324(sp) +bfc01424: afa3014c sw v1,332(sp) +bfc01428: afa70148 sw a3,328(sp) +bfc0142c: 0ff00364 jal bfc00d90 +bfc01430: afa20140 sw v0,320(sp) +bfc01434: 3c04bfc0 lui a0,0xbfc0 +bfc01438: 2484175c addiu a0,a0,5980 +bfc0143c: 0ff000b0 jal bfc002c0 +bfc01440: afa20150 sw v0,336(sp) +bfc01444: 8fa4014c lw a0,332(sp) +bfc01448: 0ff000e8 jal bfc003a0 +bfc0144c: 00000000 nop +bfc01450: 0ff000b0 jal bfc002c0 +bfc01454: 02a02021 move a0,s5 +bfc01458: 3c04bfc0 lui a0,0xbfc0 +bfc0145c: 0ff000b0 jal bfc002c0 +bfc01460: 24841778 addiu a0,a0,6008 +bfc01464: 0ff000e8 jal bfc003a0 +bfc01468: 02402021 move a0,s2 +bfc0146c: 0ff000b0 jal bfc002c0 +bfc01470: 02a02021 move a0,s5 +bfc01474: 3c04bfc0 lui a0,0xbfc0 +bfc01478: 0ff000b0 jal bfc002c0 +bfc0147c: 24841794 addiu a0,a0,6036 +bfc01480: 8fa40150 lw a0,336(sp) +bfc01484: 0ff000e8 jal bfc003a0 +bfc01488: 00000000 nop +bfc0148c: 0ff000b0 jal bfc002c0 +bfc01490: 02a02021 move a0,s5 +bfc01494: 3c04bfc0 lui a0,0xbfc0 +bfc01498: 0ff000b0 jal bfc002c0 +bfc0149c: 248417b0 addiu a0,a0,6064 +bfc014a0: 8fa6014c lw a2,332(sp) +bfc014a4: 02202021 move a0,s1 +bfc014a8: 24c60100 addiu a2,a2,256 +bfc014ac: 0ff00304 jal bfc00c10 +bfc014b0: 02402821 move a1,s2 +bfc014b4: 0440001f bltz v0,bfc01534 +bfc014b8: 00408021 move s0,v0 +bfc014bc: 0ff000b0 jal bfc002c0 +bfc014c0: 02c02021 move a0,s6 +bfc014c4: 0ff000b0 jal bfc002c0 +bfc014c8: 03c02021 move a0,s8 +bfc014cc: 02202021 move a0,s1 +bfc014d0: 02402821 move a1,s2 +bfc014d4: 27a60140 addiu a2,sp,320 +bfc014d8: 0ff00334 jal bfc00cd0 +bfc014dc: 24070100 li a3,256 +bfc014e0: 04400014 bltz v0,bfc01534 +bfc014e4: 00408021 move s0,v0 +bfc014e8: 8fa50148 lw a1,328(sp) +bfc014ec: 8fa60144 lw a2,324(sp) +bfc014f0: 8fa7014c lw a3,332(sp) +bfc014f4: 0ff00334 jal bfc00cd0 +bfc014f8: 02202021 move a0,s1 +bfc014fc: 0440000d bltz v0,bfc01534 +bfc01500: 00408021 move s0,v0 +bfc01504: 0ff000b0 jal bfc002c0 +bfc01508: 02c02021 move a0,s6 +bfc0150c: 3c04bfc0 lui a0,0xbfc0 +bfc01510: 0ff000b0 jal bfc002c0 +bfc01514: 248417e0 addiu a0,a0,6112 +bfc01518: 8fa50148 lw a1,328(sp) +bfc0151c: 8fa60144 lw a2,324(sp) +bfc01520: 8fa7014c lw a3,332(sp) +bfc01524: 0ff0033c jal bfc00cf0 +bfc01528: 02202021 move a0,s1 +bfc0152c: 0441000a bgez v0,bfc01558 +bfc01530: 00408021 move s0,v0 +bfc01534: 0ff000b0 jal bfc002c0 +bfc01538: 268417c0 addiu a0,s4,6080 +bfc0153c: 0ff000e8 jal bfc003a0 +bfc01540: 02002021 move a0,s0 +bfc01544: 3c04bfc0 lui a0,0xbfc0 +bfc01548: 0ff000b0 jal bfc002c0 +bfc0154c: 248417cc addiu a0,a0,6092 +bfc01550: 0bf0055b j bfc0156c +bfc01554: 00000000 nop +bfc01558: 0ff000b0 jal bfc002c0 +bfc0155c: 02e02021 move a0,s7 +bfc01560: 3c02bfc0 lui v0,0xbfc0 +bfc01564: 00400008 jr v0 +bfc01568: 00000000 nop +bfc0156c: 0601ff7e bgez s0,bfc01368 +bfc01570: 27b00040 addiu s0,sp,64 +bfc01574: 0bf004d6 j bfc01358 +bfc01578: 3c04bfc0 lui a0,0xbfc0 +bfc0157c: 8fbf0264 lw ra,612(sp) +bfc01580: 8fbe0260 lw s8,608(sp) +bfc01584: 8fb7025c lw s7,604(sp) +bfc01588: 8fb60258 lw s6,600(sp) +bfc0158c: 8fb50254 lw s5,596(sp) +bfc01590: 8fb40250 lw s4,592(sp) +bfc01594: 8fb3024c lw s3,588(sp) +bfc01598: 8fb20248 lw s2,584(sp) +bfc0159c: 8fb10244 lw s1,580(sp) +bfc015a0: 8fb00240 lw s0,576(sp) +bfc015a4: 03e00008 jr ra +bfc015a8: 27bd0268 addiu sp,sp,616 + +bfc015ac : +bfc015ac: 2cc20010 sltiu v0,a2,16 +bfc015b0: 00804821 move t1,a0 +bfc015b4: 1440002d bnez v0,bfc0166c +bfc015b8: 00804021 move t0,a0 +bfc015bc: 30870003 andi a3,a0,0x3 +bfc015c0: 10e0000e beqz a3,bfc015fc +bfc015c4: 24820004 addiu v0,a0,4 +bfc015c8: 00052600 sll a0,a1,0x18 +bfc015cc: 00471023 subu v0,v0,a3 +bfc015d0: 00042603 sra a0,a0,0x18 +bfc015d4: 01201821 move v1,t1 +bfc015d8: a0640000 sb a0,0(v1) +bfc015dc: 24630001 addiu v1,v1,1 +bfc015e0: 1462fffd bne v1,v0,bfc015d8 +bfc015e4: 00000000 nop +bfc015e8: 00071027 nor v0,zero,a3 +bfc015ec: 24c3fffb addiu v1,a2,-5 +bfc015f0: 24440005 addiu a0,v0,5 +bfc015f4: 00623023 subu a2,v1,v0 +bfc015f8: 01244021 addu t0,t1,a0 +bfc015fc: 30a500ff andi a1,a1,0xff +bfc01600: 01003821 move a3,t0 +bfc01604: 10a00005 beqz a1,bfc0161c +bfc01608: 00a01821 move v1,a1 +bfc0160c: 00051200 sll v0,a1,0x8 +bfc01610: 00451025 or v0,v0,a1 +bfc01614: 00021c00 sll v1,v0,0x10 +bfc01618: 00621825 or v1,v1,v0 +bfc0161c: 000610c2 srl v0,a2,0x3 +bfc01620: 1040001c beqz v0,bfc01694 +bfc01624: 30c60007 andi a2,a2,0x7 +bfc01628: 01002021 move a0,t0 +bfc0162c: 00403821 move a3,v0 +bfc01630: 24e7ffff addiu a3,a3,-1 +bfc01634: ac830000 sw v1,0(a0) +bfc01638: ac830004 sw v1,4(a0) +bfc0163c: 14e0fffc bnez a3,bfc01630 +bfc01640: 24840008 addiu a0,a0,8 +bfc01644: 000210c0 sll v0,v0,0x3 +bfc01648: 01023821 addu a3,t0,v0 +bfc0164c: 00e02021 move a0,a3 +bfc01650: 2cc20004 sltiu v0,a2,4 +bfc01654: 14400005 bnez v0,bfc0166c +bfc01658: 00804021 move t0,a0 +bfc0165c: ace30000 sw v1,0(a3) +bfc01660: 24e40004 addiu a0,a3,4 +bfc01664: 24c6fffc addiu a2,a2,-4 +bfc01668: 00804021 move t0,a0 +bfc0166c: 10c00007 beqz a2,bfc0168c +bfc01670: 00000000 nop +bfc01674: 00051600 sll v0,a1,0x18 +bfc01678: 00021603 sra v0,v0,0x18 +bfc0167c: 24c6ffff addiu a2,a2,-1 +bfc01680: a1020000 sb v0,0(t0) +bfc01684: 14c0fffd bnez a2,bfc0167c +bfc01688: 25080001 addiu t0,t0,1 +bfc0168c: 03e00008 jr ra +bfc01690: 01201021 move v0,t1 +bfc01694: 0bf00594 j bfc01650 +bfc01698: 01002021 move a0,t0 diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.prj b/projects/mips_sys/ise101/mips_sys/mips_sys.prj deleted file mode 100644 index b8b35cd..0000000 --- a/projects/mips_sys/ise101/mips_sys/mips_sys.prj +++ /dev/null @@ -1,47 +0,0 @@ -vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd" -vhdl work "../../src/sdram_config.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/vga_types.vhd" -vhdl work "../../../../lib/FIFO/src/gray_counter.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/vga_sync.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd" -vhdl work "../../../../lib/misc/utils_pkg.vhd" -vhdl work "../../../../lib/misc/singleshot.vhd" -vhdl work "../../../../lib/misc/dpram_1w1r.vhd" -vhdl work "../../../../lib/FIFO/src/fifo_async_ctrl.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd" -vhdl work "../../../../lib/uart/kcuart_tx.vhd" -vhdl work "../../../../lib/uart/kcuart_rx.vhd" -vhdl work "../../../../lib/uart/bbfifo_16x8.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd" -vhdl work "../../../../lib/FIFO/src/fifo_sync_ctrl.vhd" -vhdl work "../../../../lib/FIFO/src/fifo_async.vhd" -vhdl work "../../../../lib/ac97_ctrl/src/core/ac_out.vhd" -vhdl work "../../../../lib/ac97_ctrl/src/core/ac_in.vhd" -vhdl work "../../src/bootloader.ROM_ld.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd" -vhdl work "../../../../lib/uart/uart_tx.vhd" -vhdl work "../../../../lib/uart/uart_rx.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" -vhdl work "../../../../lib/ps2_port/src/ps2_core.vhd" -vhdl work "../../../../lib/ps2_port/src/debounce.vhd" -vhdl work "../../../../lib/misc/async_types.vhd" -vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd" -vhdl work "../../../../lib/ac97_ctrl/src/core/ac_io.vhd" -vhdl work "../../src/clockgen_virtex4.vhd" -vhdl work "../../src/async_defs.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd" -vhdl work "../../../../lib/uart/uart_wb.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" -vhdl work "../../../../lib/ps2_port/src/ps2_wb.vhd" -vhdl work "../../../../lib/ps2_port/src/ps2_phy_virtex.vhd" -vhdl work "../../../../lib/misc/rom_wb.vhd" -vhdl work "../../../../lib/misc/lcd_port.vhd" -vhdl work "../../../../lib/misc/gpio_wb.vhd" -vhdl work "../../../../lib/misc/async_port_wb.vhd" -vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd" -vhdl work "../../../../lib/ac97_ctrl/src/core/ac97_wb.vhd" -vhdl work "../../src/mips_sys.vhd" diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.ut b/projects/mips_sys/ise101/mips_sys/mips_sys.ut deleted file mode 100644 index c22b05a..0000000 --- a/projects/mips_sys/ise101/mips_sys/mips_sys.ut +++ /dev/null @@ -1,33 +0,0 @@ --w --g DebugBitstream:No --g Binary:no --g CRC:Enable --g ConfigRate:4 --g CclkPin:PullUp --g M0Pin:PullUp --g M1Pin:PullUp --g M2Pin:PullUp --g ProgPin:PullUp --g DonePin:PullUp --g InitPin:Pullup --g CsPin:Pullup --g DinPin:Pullup --g BusyPin:Pullup --g RdWrPin:Pullup --g TckPin:PullUp --g TdiPin:PullUp --g TdoPin:PullUp --g TmsPin:PullUp --g UnusedPin:PullDown --g UserID:0xFFFFFFFF --g DCIUpdateMode:AsRequired --g StartUpClk:JtagClk --g DONE_cycle:4 --g GTS_cycle:5 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Match_cycle:Auto --g Security:None --g DonePipe:No --g DriveDone:No --g Encrypt:No diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.xst b/projects/mips_sys/ise101/mips_sys/mips_sys.xst deleted file mode 100644 index 8b21e6b..0000000 --- a/projects/mips_sys/ise101/mips_sys/mips_sys.xst +++ /dev/null @@ -1,62 +0,0 @@ -set -tmpdir "W:/vhdl/projects/mips_sys/ise101/mips_sys/xst/projnav.tmp" -set -xsthdpdir "W:/vhdl/projects/mips_sys/ise101/mips_sys/xst" -run --ifn mips_sys.prj --ifmt mixed --ofn mips_sys --ofmt NGC --p xc4vsx35-10-ff668 --top mips_sys --opt_mode Speed --opt_level 1 --power NO --iuc NO --lso mips_sys.lso --keep_hierarchy NO --netlist_hierarchy as_optimized --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --dsp_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --rom_style Auto --auto_bram_packing NO --mux_extract YES --resource_sharing NO --async_to_sync NO --use_dsp48 auto --iobuf YES --max_fanout 500 --bufg 32 --bufr 24 --register_duplication YES --register_balancing Yes --move_first_stage YES --move_last_stage YES --slice_packing YES --optimize_primitives NO --use_clock_enable Auto --use_sync_set Auto --use_sync_reset Auto --iob true --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj b/projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj deleted file mode 100644 index db0d3e8..0000000 --- a/projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj +++ /dev/null @@ -1,47 +0,0 @@ -vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd" -vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_types.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_sync.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd" -vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd" -vhdl work "W:\vhdl\lib\misc\singleshot.vhd" -vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\fifo_async_ctrl.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_timing.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\fonts\char_rom_fixedsys_8x16.vhd" -vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd" -vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd" -vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd" -vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_out.vhd" -vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_in.vhd" -vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd" -vhdl work "W:\vhdl\lib\uart\uart_tx.vhd" -vhdl work "W:\vhdl\lib\uart\uart_rx.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd" -vhdl work "W:\vhdl\lib\ps2_port\src\ps2_core.vhd" -vhdl work "W:\vhdl\lib\ps2_port\src\debounce.vhd" -vhdl work "W:\vhdl\lib\misc\async_types.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd" -vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_io.vhd" -vhdl work "W:\vhdl\projects\mips_sys\src\clockgen_virtex4.vhd" -vhdl work "W:\vhdl\projects\mips_sys\src\async_defs.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend64.vhd" -vhdl work "W:\vhdl\lib\uart\uart_wb.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd" -vhdl work "W:\vhdl\lib\ps2_port\src\ps2_wb.vhd" -vhdl work "W:\vhdl\lib\ps2_port\src\ps2_phy_virtex.vhd" -vhdl work "W:\vhdl\lib\misc\rom_wb.vhd" -vhdl work "W:\vhdl\lib\misc\lcd_port.vhd" -vhdl work "W:\vhdl\lib\misc\gpio_wb.vhd" -vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd" -vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac97_wb.vhd" -vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd" diff --git a/projects/mips_sys/ise101/mips_sys/ucf/systest.ssram.ucf b/projects/mips_sys/ise101/mips_sys/ucf/systest.ssram.ucf deleted file mode 100644 index f8198e9..0000000 --- a/projects/mips_sys/ise101/mips_sys/ucf/systest.ssram.ucf +++ /dev/null @@ -1,503 +0,0 @@ -# -# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE. -# -# (c) Copyright 2005 Xilinx, Inc. -# All rights reserved. -# - -CONFIG STEPPING = "ES"; - -# Bus clock nets -NET "clk" TNM_NET = "clk"; -TIMESPEC "TS_clk" = PERIOD "clk" 9.95 ns HIGH 50 %; - -NET "inst_vga_frontend/inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk"; -#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %; -TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG; - -NET "sys_clk_in" LOC = "AE14"; -NET sys_clk_in IOSTANDARD = LVCMOS33; -NET "sys_rst_n_in" LOC = "D6"; -NET sys_rst_n_in PULLUP; -NET "sys_rst_n_in" TIG; -NET "rst" TIG; - -# Locate DCM/BUFG - Tools can probably figure them out automatically -# but just LOC them down to be safe -#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2; -#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1; - -//////////////////////////////////////////////////////////////////////////// -// Misc Board Signals -//////////////////////////////////////////////////////////////////////////// - -NET sys_error<0> LOC = V6; -NET sys_error<1> LOC = L24; -NET sys_error<*> IOSTANDARD = LVCMOS33; -NET sys_error<*> DRIVE = 2; -NET sys_error<*> TIG; - -//////////////////////////////////////////////////////////////////////////// -// RS-232 -//////////////////////////////////////////////////////////////////////////// -NET sys_rx LOC = W2; -NET sys_rx IOSTANDARD = LVCMOS33; -NET sys_rx TIG; -NET "sys_tx" LOC = "W1"; -NET sys_tx IOSTANDARD = LVCMOS33; -NET "sys_tx" TIG; - -//////////////////////////////////////////////////////////////////////////// -// Buttons, LEDs, and DIP Switches -//////////////////////////////////////////////////////////////////////////// -# GPLED 0-3 -NET "sys_led<0>" LOC = "G5"; #GPLED0 -NET "sys_led<1>" LOC = "G6"; #GPLED1 -NET "sys_led<2>" LOC = "A11"; #GPLED2 -NET "sys_led<3>" LOC = "A12"; #GPLED3 -# North-East-South-West-Center LEDs -NET "sys_led<4>" LOC = "F9"; # W LED -NET "sys_led<5>" LOC = "E2"; # N LED -NET "sys_led<6>" LOC = "E10"; # E LED -NET "sys_led<7>" LOC = "A5"; # S LED -NET "sys_led<8>" LOC = "C6"; # C LED -NET "sys_led<*>" TIG; -NET "sys_led<*>" SLEW = SLOW; -NET "sys_led<*>" DRIVE = 2; -#NET "sys_led<*>" IOSTANDARD = LVCMOS33; -# North-East-South-West-Center Buttons -NET "sys_btn<0>" LOC = "E9"; # W Button -NET "sys_btn<1>" LOC = "E7"; # N Button -NET "sys_btn<2>" LOC = "F10"; # E Button -NET "sys_btn<3>" LOC = "A6"; # S Button -NET "sys_btn<4>" LOC = "B6"; # C Button -NET "sys_btn<*>" TIG; -NET "sys_btn<*>" PULLDOWN; -#NET "sys_btn<*>" IOSTANDARD = LVCMOS33; -# Dip Switches 1-8 -NET "sys_dip<7>" LOC = "U24"; # DIP SW 8 -NET "sys_dip<6>" LOC = "U25"; # DIP SW 7 -NET "sys_dip<5>" LOC = "V23"; # DIP SW 6 -NET "sys_dip<4>" LOC = "U23"; # DIP SW 5 -NET "sys_dip<3>" LOC = "U26"; # DIP SW 4 -NET "sys_dip<2>" LOC = "T26"; # DIP SW 3 -NET "sys_dip<1>" LOC = "R19"; # DIP SW 2 -NET "sys_dip<0>" LOC = "R20"; # DIP SW 1 -NET "sys_dip<*>" PULLDOWN; -NET "sys_dip<*>" IOSTANDARD = LVCMOS33; -NET "sys_dip<*>" TIG; -//////////////////////////////////////////////////////////////////////////// -// LCD -//////////////////////////////////////////////////////////////////////////// -NET sys_lcd_e LOC = AE13; # LCD_E -NET sys_lcd_e IOSTANDARD = LVCMOS33; -NET sys_lcd_e SLEW = SLOW; -NET sys_lcd_e DRIVE = 2; -NET sys_lcd_e TIG; -NET sys_lcd_rs LOC = AC17; # LCD_RS -NET sys_lcd_rs IOSTANDARD = LVCMOS33; -NET sys_lcd_rs SLEW = SLOW; -NET sys_lcd_rs DRIVE = 2; -NET sys_lcd_rs TIG; -NET sys_lcd_rw LOC = AB17; # LCD_RW -NET sys_lcd_rw IOSTANDARD = LVCMOS33; -NET sys_lcd_rw SLEW = SLOW; -NET sys_lcd_rw DRIVE = 2; -NET sys_lcd_rw TIG; -NET sys_lcd_d<3> LOC = AF12; # LCD_DB7 -NET sys_lcd_d<2> LOC = AE12; # LCD_DB6 -NET sys_lcd_d<1> LOC = AC10; # LCD_DB5 -NET sys_lcd_d<0> LOC = AB10; # LCD_DB4 -NET sys_lcd_d<*> IOSTANDARD = LVCMOS33; -NET sys_lcd_d<*> SLEW = SLOW; -NET sys_lcd_d<*> DRIVE = 2; -NET sys_lcd_d<*> PULLDOWN; -NET sys_lcd_d<*> TIG; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for DDR Controllers -#------------------------------------------------------------------------------ - -NET sys_sdr_a_q<0> LOC = C26; # DDR_A0 -NET sys_sdr_a_q<1> LOC = E17; # DDR_A1 -NET sys_sdr_a_q<2> LOC = D18; # DDR_A2 -NET sys_sdr_a_q<3> LOC = C19; # DDR_A3 -NET sys_sdr_a_q<4> LOC = F17; # DDR_A4 -NET sys_sdr_a_q<5> LOC = B18; # DDR_A5 -NET sys_sdr_a_q<6> LOC = B20; # DDR_A6 -NET sys_sdr_a_q<7> LOC = C20; # DDR_A7 -NET sys_sdr_a_q<8> LOC = D20; # DDR_A8 -NET sys_sdr_a_q<9> LOC = C21; # DDR_A9 -NET sys_sdr_a_q<10> LOC = A18; # DDR_A10 -NET sys_sdr_a_q<11> LOC = B21; # DDR_A11 -NET sys_sdr_a_q<12> LOC = A24; # DDR_A12 -NET sys_sdr_ba_q<0> LOC = B12; # DDR_BA0 -NET sys_sdr_ba_q<1> LOC = A16; # DDR_BA1 -NET sys_sdr_cas_qn LOC = F23; # DDR_CAS_N -NET sys_sdr_cke_q LOC = G22; # DDR_CKE -NET sys_sdr_cs_qn LOC = G21; # DDR_CS_N -NET sys_sdr_ras_qn LOC = F24; # DDR_RAS_N -NET sys_sdr_we_qn LOC = A23; # DDR_WE_N - -NET sys_sdr_clk_p LOC = A10; # DDR_CK1_P -NET sys_sdr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK) -NET sys_sdr_clk_n LOC = B10; # DDR_CK1_N - -NET sys_sdr_dm_q<0> LOC = G19; # DDR_DM0 -NET sys_sdr_dm_q<1> LOC = G24; # DDR_DM1 -NET sys_sdr_dm_q<2> LOC = G20; # DDR_DM2 -NET sys_sdr_dm_q<3> LOC = C22; # DDR_DM3 - -NET sys_sdr_dqs_q<0> LOC = D25; # DDR_DQS0 -NET sys_sdr_dqs_q<1> LOC = G18; # DDR_DQS1 -NET sys_sdr_dqs_q<2> LOC = G17; # DDR_DQS2 -NET sys_sdr_dqs_q<3> LOC = D26; # DDR_DQS3 - -NET sys_sdr_data<0> LOC = H20; # DDR_D0 -NET sys_sdr_data<1> LOC = E23; # DDR_D1 -NET sys_sdr_data<2> LOC = H26; # DDR_D2 -NET sys_sdr_data<3> LOC = H22; # DDR_D3 -NET sys_sdr_data<4> LOC = E25; # DDR_D4 -NET sys_sdr_data<5> LOC = E26; # DDR_D5 -NET sys_sdr_data<6> LOC = F26; # DDR_D6 -NET sys_sdr_data<7> LOC = E24; # DDR_D7 -NET sys_sdr_data<8> LOC = E20; # DDR_D8 -NET sys_sdr_data<9> LOC = A22; # DDR_D9 -NET sys_sdr_data<10> LOC = C23; # DDR_D10 -NET sys_sdr_data<11> LOC = C24; # DDR_D11 -NET sys_sdr_data<12> LOC = A20; # DDR_D12 -NET sys_sdr_data<13> LOC = A21; # DDR_D13 -NET sys_sdr_data<14> LOC = D24; # DDR_D14 -NET sys_sdr_data<15> LOC = E18; # DDR_D15 -NET sys_sdr_data<16> LOC = F18; # DDR_D16 -NET sys_sdr_data<17> LOC = A19; # DDR_D17 -NET sys_sdr_data<18> LOC = F19; # DDR_D18 -NET sys_sdr_data<19> LOC = B23; # DDR_D19 -NET sys_sdr_data<20> LOC = E21; # DDR_D20 -NET sys_sdr_data<21> LOC = D22; # DDR_D21 -NET sys_sdr_data<22> LOC = D23; # DDR_D22 -NET sys_sdr_data<23> LOC = B24; # DDR_D23 -NET sys_sdr_data<24> LOC = E22; # DDR_D24 -NET sys_sdr_data<25> LOC = F20; # DDR_D25 -NET sys_sdr_data<26> LOC = H23; # DDR_D26 -NET sys_sdr_data<27> LOC = G25; # DDR_D27 -NET sys_sdr_data<28> LOC = G26; # DDR_D28 -NET sys_sdr_data<29> LOC = H25; # DDR_D29 -NET sys_sdr_data<30> LOC = H24; # DDR_D30 -NET sys_sdr_data<31> LOC = H21; # DDR_D31 - -NET sys_sdr_a_q<*> IOSTANDARD = SSTL2_I; -NET sys_sdr_a_q<*> FAST; - -NET sys_sdr_ba_q<*> IOSTANDARD = SSTL2_I; -NET sys_sdr_ba_q<*> FAST; - -NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_cas_qn FAST; - -NET sys_sdr_cke_q IOSTANDARD = SSTL2_I; -NET sys_sdr_cke_q FAST; - -NET sys_sdr_clk_p IOSTANDARD = SSTL2_I; -NET sys_sdr_clk_p FAST; -NET sys_sdr_clk_fb IOSTANDARD = LVCMOS25; -NET sys_sdr_clk_fb IOBDELAY = NONE; -NET sys_sdr_clk_n IOSTANDARD = SSTL2_I; -NET sys_sdr_clk_n FAST; - -NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_cas_qn FAST; - -NET sys_sdr_cs_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_cs_qn FAST; - -NET sys_sdr_ras_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_ras_qn FAST; - -NET sys_sdr_we_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_we_qn FAST; - -NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II; -NET sys_sdr_dqs_q<*> IOBDELAY = NONE; -NET sys_sdr_dqs_q<*> FAST; - -NET sys_sdr_dm_q<*> IOSTANDARD = SSTL2_II; -NET sys_sdr_dm_q<*> IOBDELAY = NONE; -NET sys_sdr_dm_q<*> FAST; - -NET sys_sdr_data<*> IOSTANDARD = SSTL2_II; -NET sys_sdr_data<*> IOBDELAY = NONE; -NET sys_sdr_data<*> FAST; - -#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n"; - -NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p"; -NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n"; - -# Timing Constraint for DDR Feedback Clock -NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p; - -# USB -NET sys_usb_a<0> LOC = Y10; -NET sys_usb_a<1> LOC = AA10; -NET sys_usb_a<*> IOSTANDARD = LVCMOS33; - -NET sys_usb_d<0> LOC = AB7; -NET sys_usb_d<1> LOC = AC9; -NET sys_usb_d<2> LOC = AB9; -NET sys_usb_d<3> LOC = AE6; -NET sys_usb_d<4> LOC = AD6; -NET sys_usb_d<5> LOC = AF9; -NET sys_usb_d<6> LOC = AE9; -NET sys_usb_d<7> LOC = AD8; -NET sys_usb_d<8> LOC = AC8; -NET sys_usb_d<9> LOC = AF4; -NET sys_usb_d<10> LOC = AE4; -NET sys_usb_d<11> LOC = AD3; -NET sys_usb_d<12> LOC = AC3; -NET sys_usb_d<13> LOC = AF6; -NET sys_usb_d<14> LOC = AF5; -NET sys_usb_d<15> LOC = AA7; -NET sys_usb_d<*> IOSTANDARD = LVCMOS33; -NET sys_usb_d<*> SLEW = FAST; -NET sys_usb_d<*> DRIVE = 8; -NET sys_usb_d<*> PULLDOWN; - -NET sys_usb_rdn LOC = AA8; -NET sys_usb_rdn IOSTANDARD = LVCMOS33; -NET sys_usb_rdn SLEW = FAST; -NET sys_usb_rdn DRIVE = 8; - -NET sys_usb_wrn LOC = Y8; -NET sys_usb_wrn IOSTANDARD = LVCMOS33; -NET sys_usb_wrn SLEW = FAST; -NET sys_usb_wrn DRIVE = 8; - -NET sys_usb_csn LOC = AF10; -NET sys_usb_csn IOSTANDARD = LVCMOS33; -NET sys_usb_csn SLEW = FAST; -NET sys_usb_csn DRIVE = 8; - -NET sys_usb_rstn LOC = A7; -NET sys_usb_rstn IOSTANDARD = LVCMOS25; -NET sys_usb_rstn TIG; - -NET sys_usb_int LOC = V5; -NET sys_usb_int IOSTANDARD = LVCMOS33; -NET sys_usb_int PULLDOWN; -NET sys_usb_int TIG; - -# FLASH -NET sys_flash_ssram_a<24> LOC = T21; -NET sys_flash_ssram_a<23> LOC = U20; -NET sys_flash_ssram_a<22> LOC = T19; -NET sys_flash_ssram_a<21> LOC = AC5; -NET sys_flash_ssram_a<20> LOC = AB5; -NET sys_flash_ssram_a<19> LOC = AC4; -NET sys_flash_ssram_a<18> LOC = AB4; -NET sys_flash_ssram_a<17> LOC = AB3; -NET sys_flash_ssram_a<16> LOC = AA4; -NET sys_flash_ssram_a<15> LOC = AA3; -NET sys_flash_ssram_a<14> LOC = W5; -NET sys_flash_ssram_a<13> LOC = W6; -NET sys_flash_ssram_a<12> LOC = W3; -NET sys_flash_ssram_a<11> LOC = AF3; -NET sys_flash_ssram_a<10> LOC = AE3; -NET sys_flash_ssram_a<9> LOC = AD2; -NET sys_flash_ssram_a<8> LOC = AD1; -NET sys_flash_ssram_a<7> LOC = AC2; -NET sys_flash_ssram_a<6> LOC = AC1; -NET sys_flash_ssram_a<5> LOC = AB2; -NET sys_flash_ssram_a<4> LOC = AB1; -NET sys_flash_ssram_a<3> LOC = AA1; -NET sys_flash_ssram_a<2> LOC = Y2; -NET sys_flash_ssram_a<1> LOC = Y1; -NET sys_flash_ssram_a<0> LOC = T20; -NET sys_flash_ssram_a<*> IOSTANDARD = LVDCI_33; -NET sys_flash_ssram_a<*> SLEW = FAST; -NET sys_flash_ssram_a<*> DRIVE = 8; - - -NET sys_flash_ssram_d<31> LOC = F14; -NET sys_flash_ssram_d<30> LOC = F13; -NET sys_flash_ssram_d<29> LOC = F12; -NET sys_flash_ssram_d<28> LOC = F11; -NET sys_flash_ssram_d<27> LOC = F16; -NET sys_flash_ssram_d<26> LOC = F15; -NET sys_flash_ssram_d<25> LOC = D14; -NET sys_flash_ssram_d<24> LOC = D13; -NET sys_flash_ssram_d<23> LOC = D15; -NET sys_flash_ssram_d<22> LOC = E14; -NET sys_flash_ssram_d<21> LOC = C11; -NET sys_flash_ssram_d<20> LOC = D11; -NET sys_flash_ssram_d<19> LOC = D16; -NET sys_flash_ssram_d<18> LOC = C16; -NET sys_flash_ssram_d<17> LOC = E13; -NET sys_flash_ssram_d<16> LOC = D12; -NET sys_flash_ssram_d<15> LOC = AA14; -NET sys_flash_ssram_d<14> LOC = AB14; -NET sys_flash_ssram_d<13> LOC = AC12; -NET sys_flash_ssram_d<12> LOC = AC11; -NET sys_flash_ssram_d<11> LOC = AA16; -NET sys_flash_ssram_d<10> LOC = AA15; -NET sys_flash_ssram_d<9> LOC = AB13; -NET sys_flash_ssram_d<8> LOC = AA13; -NET sys_flash_ssram_d<7> LOC = AC14; -NET sys_flash_ssram_d<6> LOC = AD14; -NET sys_flash_ssram_d<5> LOC = AA12; -NET sys_flash_ssram_d<4> LOC = AA11; -NET sys_flash_ssram_d<3> LOC = AC16; -NET sys_flash_ssram_d<2> LOC = AC15; -NET sys_flash_ssram_d<1> LOC = AC13; -NET sys_flash_ssram_d<0> LOC = AD13; -NET sys_flash_ssram_d<*> IOSTANDARD = LVCMOS33; -NET sys_flash_ssram_d<*> DRIVE = 12; -NET sys_flash_ssram_d<*> SLEW = FAST; -NET sys_flash_ssram_d<*> PULLDOWN; - -NET sys_flash_ssram_oe_n LOC = AC6; -NET sys_flash_ssram_oe_n IOSTANDARD = LVDCI_33; -NET sys_flash_ssram_oe_n SLEW = FAST; -NET sys_flash_ssram_oe_n DRIVE = 8; - -NET sys_flash_ssram_we_n LOC = AB6; -NET sys_flash_ssram_we_n IOSTANDARD = LVDCI_33; -NET sys_flash_ssram_we_n SLEW = FAST; -NET sys_flash_ssram_we_n DRIVE = 8; - -NET sys_flash_ce LOC = W7; -NET sys_flash_ce IOSTANDARD = LVDCI_33; -NET sys_flash_ce SLEW = FAST; -NET sys_flash_ce DRIVE = 8; - -NET sys_flash_rstn LOC = AD10; -NET sys_flash_rstn IOSTANDARD = LVCMOS33; -NET sys_flash_rstn DRIVE = 8; -NET sys_flash_rstn SLEW = FAST; -NET sys_flash_rstn TIG; - -NET sys_flash_byten LOC = N22; -NET sys_flash_byten IOSTANDARD = LVCMOS33; -NET sys_flash_byten DRIVE = 8; -NET sys_flash_byten SLEW = FAST; -NET sys_flash_byten TIG; - -# SSRAM -NET sys_ssram_clk LOC = AF7; -NET sys_ssram_clk IOSTANDARD = LVCMOS33; -NET sys_ssram_clk DRIVE = 16; -NET sys_ssram_clk SLEW = FAST; - -NET "sys_ssram_clk" TNM_NET = "ssram_clk"; -#TIMESPEC "TS_ssram_clk" = PERIOD "ssram_clk" 9.95 ns HIGH 50 %; - - -NET sys_ssram_clk_fb LOC = AD17; -NET sys_ssram_clk_fb IOSTANDARD = LVCMOS33; - -# Timing Constraint for Feedback Clock -NET sys_ssram_clk_fb FEEDBACK = 1 ns NET sys_ssram_clk; - -NET sys_ssram_ce_n LOC = V7; -NET sys_ssram_ce_n IOSTANDARD = LVDCI_33; -NET sys_ssram_ce_n SLEW = FAST; -NET sys_ssram_ce_n DRIVE = 8; - -NET sys_ssram_bw_n<3> LOC = Y3; #Y4; -NET sys_ssram_bw_n<2> LOC = Y4; #Y3; -NET sys_ssram_bw_n<1> LOC = Y5; #Y6; -NET sys_ssram_bw_n<0> LOC = Y6; #Y5; -NET sys_ssram_bw_n<*> IOSTANDARD = LVDCI_33; -NET sys_ssram_bw_n<*> SLEW = FAST; -NET sys_ssram_bw_n<*> DRIVE = 8; - -NET sys_ssram_adv LOC = W4; -NET sys_ssram_adv IOSTANDARD = LVDCI_33; -NET sys_ssram_adv SLEW = FAST; -NET sys_ssram_adv DRIVE = 8; - -NET sys_ssram_mode LOC = V26; -NET sys_ssram_mode IOSTANDARD = LVDCI_33; -NET sys_ssram_mode SLEW = FAST; -NET sys_ssram_mode DRIVE = 8; - - -# VGA -NET sys_vga_blue<0> LOC = M21; # VGA_B0 -NET sys_vga_blue<1> LOC = M26; # VGA_B1 -NET sys_vga_blue<2> LOC = L26; # VGA_B2 -NET sys_vga_blue<3> LOC = C5; # VGA_B3 -NET sys_vga_blue<4> LOC = C7; # VGA_B4 -NET sys_vga_blue<5> LOC = B7; # VGA_B5 -NET sys_vga_blue<6> LOC = G8; # VGA_B6 -NET sys_vga_blue<7> LOC = F8; # VGA_B7 -NET sys_vga_blue<0> IOSTANDARD = LVCMOS33; -NET sys_vga_blue<1> IOSTANDARD = LVCMOS33; -NET sys_vga_blue<2> IOSTANDARD = LVCMOS33; -NET sys_vga_blue<*> SLEW = FAST; -NET sys_vga_blue<*> DRIVE = 8; - -NET sys_vga_clk LOC = AF8; -NET sys_vga_clk IOSTANDARD = LVDCI_33; -NET sys_vga_clk SLEW = FAST; -NET sys_vga_clk DRIVE = 8; - -NET sys_vga_green<0> LOC = M22; # VGA_G0 -NET sys_vga_green<1> LOC = M23; # VGA_G1 -NET sys_vga_green<2> LOC = M20; # VGA_G2 -NET sys_vga_green<3> LOC = E4; # VGA_G3 -NET sys_vga_green<4> LOC = D3; # VGA_G4 -NET sys_vga_green<5> LOC = H7; # VGA_G5 -NET sys_vga_green<6> LOC = H8; # VGA_G6 -NET sys_vga_green<7> LOC = C1; # VGA_G7 -NET sys_vga_green<0> IOSTANDARD = LVCMOS33; -NET sys_vga_green<1> IOSTANDARD = LVCMOS33; -NET sys_vga_green<2> IOSTANDARD = LVCMOS33; -NET sys_vga_green<*> SLEW = FAST; -NET sys_vga_green<*> DRIVE = 8; - -NET sys_vga_hsync LOC = C10; -NET sys_vga_hsync SLEW = FAST; -NET sys_vga_hsync DRIVE = 8; -#NET sys_vga_hsync IOSTANDARD = LVCMOS33; - -NET sys_vga_red<0> LOC = N23; #VGA_R0 -NET sys_vga_red<1> LOC = N24; #VGA_R1 -NET sys_vga_red<2> LOC = N25; #VGA_R2 -NET sys_vga_red<3> LOC = C2; #VGA_R3 -NET sys_vga_red<4> LOC = G7; #VGA_R4 -NET sys_vga_red<5> LOC = F7; #VGA_R5 -NET sys_vga_red<6> LOC = E5; #VGA_R6 -NET sys_vga_red<7> LOC = E6; #VGA_R7 -NET sys_vga_red<0> IOSTANDARD = LVCMOS33; -NET sys_vga_red<1> IOSTANDARD = LVCMOS33; -NET sys_vga_red<2> IOSTANDARD = LVCMOS33; -NET sys_vga_red<*> SLEW = FAST; -NET sys_vga_red<*> DRIVE = 8; - -NET sys_vga_vsync LOC = A8; -NET sys_vga_vsync SLEW = FAST; -NET sys_vga_vsync DRIVE = 8; -#NET sys_vga_vsync IOSTANDARD = LVCMOS33; - -NET sys_vga_blank_n LOC = M24; -NET sys_vga_blank_n SLEW = FAST; -NET sys_vga_blank_n DRIVE = 8; -NET sys_vga_blank_n IOSTANDARD = LVCMOS33; - -NET sys_vga_sync_n LOC = L23; -NET sys_vga_sync_n SLEW = FAST; -NET sys_vga_sync_n DRIVE = 8; -NET sys_vga_sync_n IOSTANDARD = LVCMOS33; diff --git a/projects/mips_sys/ise101/mips_sys/ucf/systest.ucf b/projects/mips_sys/ise101/mips_sys/ucf/systest.ucf deleted file mode 100644 index 14e7129..0000000 --- a/projects/mips_sys/ise101/mips_sys/ucf/systest.ucf +++ /dev/null @@ -1,629 +0,0 @@ -# -# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE. -# -# (c) Copyright 2005 Xilinx, Inc. -# All rights reserved. -# - -CONFIG STEPPING = "ES"; - -# Bus clock nets -NET "CLK_O" TNM_NET = "sys_clk"; -TIMESPEC "TS_clk" = PERIOD "sys_clk" 9.9 ns HIGH 50 %; - -NET "sdram_clk0" TNM_NET = "sdram_clk"; -TIMESPEC "TS_sdram_clk" = PERIOD "sdram_clk" 7.5 ns HIGH 50 %; -TIMESPEC "TS_unrelate_SDRAM" = FROM sys_clk TO sdram_clk TIG; - -NET "vga_clk" TNM_NET = "vga_clk"; -TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 8.0 ns HIGH 50 %; -TIMESPEC "TS_unrelate_VGA" = FROM sys_clk TO vga_clk TIG; - -NET "cpu_clk" TNM_NET = "cpu_clk"; -TIMESPEC "TS_cpu_clk" = PERIOD "cpu_clk" 9.9 ns HIGH 50 %; -#TIMESPEC "TS_unrelate_CPU" = FROM sys_clk TO cpu_clk TIG; - -NET "sys_clk_in" LOC = "AE14"; -NET sys_clk_in IOSTANDARD = LVCMOS33; -NET "sys_rst_n_in" LOC = "D6"; -NET sys_rst_n_in PULLUP; -NET "sys_rst_n_in" TIG; -NET "RST_O" TIG; - -#NET "sys_clk_in" CLOCK_DEDICATED_ROUTE = FALSE; -#PIN "inst_clockgen/inst_DCM_BASE_0.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; - -#NET "sys_sdr_clk_fb" CLOCK_DEDICATED_ROUTE = FALSE; -#PIN "inst_clockgen/inst_DCM_BASE_0.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE; - -# Locate DCM/BUFG - Tools can probably figure them out automatically -# but just LOC them down to be safe -#INST inst_clockgen/inst_DCM_BASE_0 LOC = DCM_ADV_X0Y4; -#INST inst_clockgen/inst_DCM_BASE_1 LOC = DCM_ADV_X0Y3; - -# --------------------------------------------------------------------------------- -# Floor planning -# --------------------------------------------------------------------------------- -#INST "inst_vga_frontend" AREA_GROUP = "AG_inst_vga_frontend" ; -#AREA_GROUP "AG_inst_vga_frontend" RANGE = SLICE_X8Y191:SLICE_X30Y141 ; -#AREA_GROUP "AG_inst_vga_frontend" RANGE = RAMB16_X0Y18:RAMB16_X0Y23, RAMB16_X1Y18:RAMB16_X1Y23, RAMB16_X2Y18:RAMB16_X2Y23 ; - -#INST "inst_sdram_ctrl_frontend_wb" AREA_GROUP = "AG_inst_sdram_ctrl_frontend_wb" ; -#AREA_GROUP "AG_inst_sdram_ctrl_frontend_wb" RANGE = SLICE_X0Y191:SLICE_X7Y141 ; - -INST "inst_mips_top" AREA_GROUP = "AG_inst_mips_top" ; -# GOOD 1 -#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y85:SLICE_X39Y0 ; -#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y10, RAMB16_X1Y0:RAMB16_X1Y10, RAMB16_X2Y0:RAMB16_X2Y10, RAMB16_X3Y0:RAMB16_X3Y10 ; - -# GOOD 2 (smaller) -#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y69:SLICE_X39Y0 ; -#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y8, RAMB16_X1Y0:RAMB16_X1Y8, RAMB16_X2Y0:RAMB16_X2Y8, RAMB16_X3Y0:RAMB16_X3Y8 ; - -# GOOD 3 (even smaller) -#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y61:SLICE_X39Y0 ; -#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y7, RAMB16_X1Y0:RAMB16_X1Y7, RAMB16_X2Y0:RAMB16_X2Y7, RAMB16_X3Y0:RAMB16_X3Y7 ; - -# GOOD 4 (even more smaller) -AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y53:SLICE_X39Y0 ; -AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y6, RAMB16_X1Y0:RAMB16_X1Y6, RAMB16_X2Y0:RAMB16_X2Y6, RAMB16_X3Y0:RAMB16_X3Y6 ; - -# TEMP 4 -#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y54:SLICE_X39Y0 ; -#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y6, RAMB16_X1Y0:RAMB16_X1Y6, RAMB16_X2Y0:RAMB16_X2Y6, RAMB16_X3Y0:RAMB16_X3Y6 ; - -# TEMP 4.1 -#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y55:SLICE_X39Y0 ; -#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y6, RAMB16_X1Y0:RAMB16_X1Y6, RAMB16_X2Y0:RAMB16_X2Y6, RAMB16_X3Y0:RAMB16_X3Y6 ; -//////////////////////////////////////////////////////////////////////////// -// Misc Board Signals -//////////////////////////////////////////////////////////////////////////// - -NET sys_error<0> LOC = V6; -NET sys_error<1> LOC = L24; -NET sys_error<*> IOSTANDARD = LVCMOS33; -NET sys_error<*> DRIVE = 2; -NET sys_error<*> TIG; - -//////////////////////////////////////////////////////////////////////////// -// RS-232 -//////////////////////////////////////////////////////////////////////////// -NET sys_uart0_rx LOC = W2; -NET sys_uart0_rx IOSTANDARD = LVCMOS33; -NET sys_uart0_rx TIG; -NET sys_uart0_tx LOC = W1; -NET sys_uart0_tx IOSTANDARD = LVCMOS33; -NET sys_uart0_tx TIG; - -NET sys_uart1_rx LOC = AF24; -NET sys_uart1_rx IOSTANDARD = LVCMOS33; -NET sys_uart1_rx TIG; -NET sys_uart1_tx LOC = AE24; -NET sys_uart1_tx IOSTANDARD = LVCMOS33; -NET sys_uart1_tx TIG; - -NET sys_uart2_rx LOC = AD22; -NET sys_uart2_rx IOSTANDARD = LVCMOS33; -NET sys_uart2_rx TIG; -NET sys_uart2_tx LOC = AB21; -NET sys_uart2_tx IOSTANDARD = LVCMOS33; -NET sys_uart2_tx TIG; - -NET sys_uart3_rx LOC = W20; -NET sys_uart3_rx IOSTANDARD = LVCMOS33; -NET sys_uart3_rx TIG; -NET sys_uart3_tx LOC = W21; -NET sys_uart3_tx IOSTANDARD = LVCMOS33; -NET sys_uart3_tx TIG; - -//////////////////////////////////////////////////////////////////////////// -// Buttons, LEDs, and DIP Switches -//////////////////////////////////////////////////////////////////////////// -# GPLED 0-3 -NET "sys_led<0>" LOC = "G5"; #GPLED0 -NET "sys_led<1>" LOC = "G6"; #GPLED1 -NET "sys_led<2>" LOC = "A11"; #GPLED2 -NET "sys_led<3>" LOC = "A12"; #GPLED3 -# North-East-South-West-Center LEDs -NET "sys_led<4>" LOC = "F9"; # W LED -NET "sys_led<5>" LOC = "E2"; # N LED -NET "sys_led<6>" LOC = "E10"; # E LED -NET "sys_led<7>" LOC = "A5"; # S LED -NET "sys_led<8>" LOC = "C6"; # C LED -NET "sys_led<*>" TIG; -NET "sys_led<*>" SLEW = SLOW; -NET "sys_led<*>" DRIVE = 2; -#NET "sys_led<*>" IOSTANDARD = LVCMOS33; -# North-East-South-West-Center Buttons -NET "sys_btn<0>" LOC = "E9"; # W Button -NET "sys_btn<1>" LOC = "E7"; # N Button -NET "sys_btn<2>" LOC = "F10"; # E Button -NET "sys_btn<3>" LOC = "A6"; # S Button -NET "sys_btn<4>" LOC = "B6"; # C Button -NET "sys_btn<*>" TIG; -NET "sys_btn<*>" PULLDOWN; -#NET "sys_btn<*>" IOSTANDARD = LVCMOS33; -# Dip Switches 1-8 -NET "sys_dip<7>" LOC = "U24"; # DIP SW 8 -NET "sys_dip<6>" LOC = "U25"; # DIP SW 7 -NET "sys_dip<5>" LOC = "V23"; # DIP SW 6 -NET "sys_dip<4>" LOC = "U23"; # DIP SW 5 -NET "sys_dip<3>" LOC = "U26"; # DIP SW 4 -NET "sys_dip<2>" LOC = "T26"; # DIP SW 3 -NET "sys_dip<1>" LOC = "R19"; # DIP SW 2 -NET "sys_dip<0>" LOC = "R20"; # DIP SW 1 -NET "sys_dip<*>" PULLDOWN; -NET "sys_dip<*>" IOSTANDARD = LVCMOS33; -NET "sys_dip<*>" TIG; -//////////////////////////////////////////////////////////////////////////// -// LCD -//////////////////////////////////////////////////////////////////////////// -NET sys_lcd_e LOC = AE13; # LCD_E -NET sys_lcd_e IOSTANDARD = LVCMOS33; -NET sys_lcd_e SLEW = SLOW; -NET sys_lcd_e DRIVE = 2; -NET sys_lcd_e TIG; -NET sys_lcd_rs LOC = AC17; # LCD_RS -NET sys_lcd_rs IOSTANDARD = LVCMOS33; -NET sys_lcd_rs SLEW = SLOW; -NET sys_lcd_rs DRIVE = 2; -NET sys_lcd_rs TIG; -NET sys_lcd_rw LOC = AB17; # LCD_RW -NET sys_lcd_rw IOSTANDARD = LVCMOS33; -NET sys_lcd_rw SLEW = SLOW; -NET sys_lcd_rw DRIVE = 2; -NET sys_lcd_rw TIG; -NET sys_lcd_d<3> LOC = AF12; # LCD_DB7 -NET sys_lcd_d<2> LOC = AE12; # LCD_DB6 -NET sys_lcd_d<1> LOC = AC10; # LCD_DB5 -NET sys_lcd_d<0> LOC = AB10; # LCD_DB4 -NET sys_lcd_d<*> IOSTANDARD = LVCMOS33; -NET sys_lcd_d<*> SLEW = SLOW; -NET sys_lcd_d<*> DRIVE = 2; -NET sys_lcd_d<*> PULLDOWN; -NET sys_lcd_d<*> TIG; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for DDR Controllers -#------------------------------------------------------------------------------ - -NET sys_sdr_a_q<0> LOC = C26; # DDR_A0 -NET sys_sdr_a_q<1> LOC = E17; # DDR_A1 -NET sys_sdr_a_q<2> LOC = D18; # DDR_A2 -NET sys_sdr_a_q<3> LOC = C19; # DDR_A3 -NET sys_sdr_a_q<4> LOC = F17; # DDR_A4 -NET sys_sdr_a_q<5> LOC = B18; # DDR_A5 -NET sys_sdr_a_q<6> LOC = B20; # DDR_A6 -NET sys_sdr_a_q<7> LOC = C20; # DDR_A7 -NET sys_sdr_a_q<8> LOC = D20; # DDR_A8 -NET sys_sdr_a_q<9> LOC = C21; # DDR_A9 -NET sys_sdr_a_q<10> LOC = A18; # DDR_A10 -NET sys_sdr_a_q<11> LOC = B21; # DDR_A11 -NET sys_sdr_a_q<12> LOC = A24; # DDR_A12 -NET sys_sdr_ba_q<0> LOC = B12; # DDR_BA0 -NET sys_sdr_ba_q<1> LOC = A16; # DDR_BA1 -NET sys_sdr_cas_qn LOC = F23; # DDR_CAS_N -NET sys_sdr_cke_q LOC = G22; # DDR_CKE -NET sys_sdr_cs_qn LOC = G21; # DDR_CS_N -NET sys_sdr_ras_qn LOC = F24; # DDR_RAS_N -NET sys_sdr_we_qn LOC = A23; # DDR_WE_N - -NET sys_sdr_clk_p LOC = A10; # DDR_CK1_P -NET sys_sdr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK) -NET sys_sdr_clk_n LOC = B10; # DDR_CK1_N - -NET sys_sdr_dm_q<0> LOC = G19; # DDR_DM0 -NET sys_sdr_dm_q<1> LOC = G24; # DDR_DM1 -NET sys_sdr_dm_q<2> LOC = G20; # DDR_DM2 -NET sys_sdr_dm_q<3> LOC = C22; # DDR_DM3 - -NET sys_sdr_dqs_q<0> LOC = D25; # DDR_DQS0 -NET sys_sdr_dqs_q<1> LOC = G18; # DDR_DQS1 -NET sys_sdr_dqs_q<2> LOC = G17; # DDR_DQS2 -NET sys_sdr_dqs_q<3> LOC = D26; # DDR_DQS3 - -NET sys_sdr_data<0> LOC = H20; # DDR_D0 -NET sys_sdr_data<1> LOC = E23; # DDR_D1 -NET sys_sdr_data<2> LOC = H26; # DDR_D2 -NET sys_sdr_data<3> LOC = H22; # DDR_D3 -NET sys_sdr_data<4> LOC = E25; # DDR_D4 -NET sys_sdr_data<5> LOC = E26; # DDR_D5 -NET sys_sdr_data<6> LOC = F26; # DDR_D6 -NET sys_sdr_data<7> LOC = E24; # DDR_D7 -NET sys_sdr_data<8> LOC = E20; # DDR_D8 -NET sys_sdr_data<9> LOC = A22; # DDR_D9 -NET sys_sdr_data<10> LOC = C23; # DDR_D10 -NET sys_sdr_data<11> LOC = C24; # DDR_D11 -NET sys_sdr_data<12> LOC = A20; # DDR_D12 -NET sys_sdr_data<13> LOC = A21; # DDR_D13 -NET sys_sdr_data<14> LOC = D24; # DDR_D14 -NET sys_sdr_data<15> LOC = E18; # DDR_D15 -NET sys_sdr_data<16> LOC = F18; # DDR_D16 -NET sys_sdr_data<17> LOC = A19; # DDR_D17 -NET sys_sdr_data<18> LOC = F19; # DDR_D18 -NET sys_sdr_data<19> LOC = B23; # DDR_D19 -NET sys_sdr_data<20> LOC = E21; # DDR_D20 -NET sys_sdr_data<21> LOC = D22; # DDR_D21 -NET sys_sdr_data<22> LOC = D23; # DDR_D22 -NET sys_sdr_data<23> LOC = B24; # DDR_D23 -NET sys_sdr_data<24> LOC = E22; # DDR_D24 -NET sys_sdr_data<25> LOC = F20; # DDR_D25 -NET sys_sdr_data<26> LOC = H23; # DDR_D26 -NET sys_sdr_data<27> LOC = G25; # DDR_D27 -NET sys_sdr_data<28> LOC = G26; # DDR_D28 -NET sys_sdr_data<29> LOC = H25; # DDR_D29 -NET sys_sdr_data<30> LOC = H24; # DDR_D30 -NET sys_sdr_data<31> LOC = H21; # DDR_D31 - -NET sys_sdr_a_q<*> IOSTANDARD = SSTL2_I; -NET sys_sdr_a_q<*> FAST; - -NET sys_sdr_ba_q<*> IOSTANDARD = SSTL2_I; -NET sys_sdr_ba_q<*> FAST; - -NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_cas_qn FAST; - -NET sys_sdr_cke_q IOSTANDARD = SSTL2_I; -NET sys_sdr_cke_q FAST; - -NET sys_sdr_clk_p IOSTANDARD = SSTL2_I; -NET sys_sdr_clk_p FAST; -NET sys_sdr_clk_fb IOSTANDARD = LVCMOS25; -NET sys_sdr_clk_fb IOBDELAY = NONE; -NET sys_sdr_clk_n IOSTANDARD = SSTL2_I; -NET sys_sdr_clk_n FAST; - -NET sys_sdr_cs_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_cs_qn FAST; - -NET sys_sdr_ras_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_ras_qn FAST; - -NET sys_sdr_we_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_we_qn FAST; - -NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II; -NET sys_sdr_dqs_q<*> IOBDELAY = NONE; -NET sys_sdr_dqs_q<*> FAST; - -NET sys_sdr_dm_q<*> IOSTANDARD = SSTL2_II; -NET sys_sdr_dm_q<*> IOBDELAY = NONE; -NET sys_sdr_dm_q<*> FAST; - -NET sys_sdr_data<*> IOSTANDARD = SSTL2_II; -NET sys_sdr_data<*> IOBDELAY = NONE; -NET sys_sdr_data<*> FAST; - -#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n"; - -NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p"; -NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n"; - -# Timing Constraint for DDR Feedback Clock -NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p; - -# USB -NET sys_usb_a<0> LOC = Y10; -NET sys_usb_a<1> LOC = AA10; -NET sys_usb_a<*> IOSTANDARD = LVCMOS33; - -NET sys_usb_d<0> LOC = AB7; -NET sys_usb_d<1> LOC = AC9; -NET sys_usb_d<2> LOC = AB9; -NET sys_usb_d<3> LOC = AE6; -NET sys_usb_d<4> LOC = AD6; -NET sys_usb_d<5> LOC = AF9; -NET sys_usb_d<6> LOC = AE9; -NET sys_usb_d<7> LOC = AD8; -NET sys_usb_d<8> LOC = AC8; -NET sys_usb_d<9> LOC = AF4; -NET sys_usb_d<10> LOC = AE4; -NET sys_usb_d<11> LOC = AD3; -NET sys_usb_d<12> LOC = AC3; -NET sys_usb_d<13> LOC = AF6; -NET sys_usb_d<14> LOC = AF5; -NET sys_usb_d<15> LOC = AA7; -NET sys_usb_d<*> IOSTANDARD = LVCMOS33; -NET sys_usb_d<*> SLEW = FAST; -NET sys_usb_d<*> DRIVE = 8; -NET sys_usb_d<*> PULLDOWN; -NET sys_usb_d<*> IOBDELAY = NONE; - -NET sys_usb_rdn LOC = AA8; -NET sys_usb_rdn IOSTANDARD = LVCMOS33; -NET sys_usb_rdn SLEW = FAST; -NET sys_usb_rdn DRIVE = 8; - -NET sys_usb_wrn LOC = Y8; -NET sys_usb_wrn IOSTANDARD = LVCMOS33; -NET sys_usb_wrn SLEW = FAST; -NET sys_usb_wrn DRIVE = 8; - -NET sys_usb_csn LOC = AF10; -NET sys_usb_csn IOSTANDARD = LVCMOS33; -NET sys_usb_csn SLEW = FAST; -NET sys_usb_csn DRIVE = 8; - -NET sys_usb_rstn LOC = A7; -NET sys_usb_rstn IOSTANDARD = LVCMOS25; -NET sys_usb_rstn TIG; - -NET sys_usb_int LOC = V5; -NET sys_usb_int IOSTANDARD = LVCMOS33; -NET sys_usb_int PULLDOWN; -NET sys_usb_int TIG; - -# FLASH -NET sys_flash_a<24> LOC = T21; -NET sys_flash_a<23> LOC = U20; -NET sys_flash_a<22> LOC = T19; -NET sys_flash_a<21> LOC = AC5; -NET sys_flash_a<20> LOC = AB5; -NET sys_flash_a<19> LOC = AC4; -NET sys_flash_a<18> LOC = AB4; -NET sys_flash_a<17> LOC = AB3; -NET sys_flash_a<16> LOC = AA4; -NET sys_flash_a<15> LOC = AA3; -NET sys_flash_a<14> LOC = W5; -NET sys_flash_a<13> LOC = W6; -NET sys_flash_a<12> LOC = W3; -NET sys_flash_a<11> LOC = AF3; -NET sys_flash_a<10> LOC = AE3; -NET sys_flash_a<9> LOC = AD2; -NET sys_flash_a<8> LOC = AD1; -NET sys_flash_a<7> LOC = AC2; -NET sys_flash_a<6> LOC = AC1; -NET sys_flash_a<5> LOC = AB2; -NET sys_flash_a<4> LOC = AB1; -NET sys_flash_a<3> LOC = AA1; -NET sys_flash_a<2> LOC = Y2; -NET sys_flash_a<1> LOC = Y1; -NET sys_flash_a<0> LOC = T20; - -NET sys_flash_d<31> LOC = F14; -NET sys_flash_d<30> LOC = F13; -NET sys_flash_d<29> LOC = F12; -NET sys_flash_d<28> LOC = F11; -NET sys_flash_d<27> LOC = F16; -NET sys_flash_d<26> LOC = F15; -NET sys_flash_d<25> LOC = D14; -NET sys_flash_d<24> LOC = D13; -NET sys_flash_d<23> LOC = D15; -NET sys_flash_d<22> LOC = E14; -NET sys_flash_d<21> LOC = C11; -NET sys_flash_d<20> LOC = D11; -NET sys_flash_d<19> LOC = D16; -NET sys_flash_d<18> LOC = C16; -NET sys_flash_d<17> LOC = E13; -NET sys_flash_d<16> LOC = D12; -NET sys_flash_d<15> LOC = AA14; -NET sys_flash_d<14> LOC = AB14; -NET sys_flash_d<13> LOC = AC12; -NET sys_flash_d<12> LOC = AC11; -NET sys_flash_d<11> LOC = AA16; -NET sys_flash_d<10> LOC = AA15; -NET sys_flash_d<9> LOC = AB13; -NET sys_flash_d<8> LOC = AA13; -NET sys_flash_d<7> LOC = AC14; -NET sys_flash_d<6> LOC = AD14; -NET sys_flash_d<5> LOC = AA12; -NET sys_flash_d<4> LOC = AA11; -NET sys_flash_d<3> LOC = AC16; -NET sys_flash_d<2> LOC = AC15; -NET sys_flash_d<1> LOC = AC13; -NET sys_flash_d<0> LOC = AD13; -NET sys_flash_rdn LOC = AC6; -NET sys_flash_wrn LOC = AB6; -NET sys_flash_ce LOC = W7; -NET sys_flash_ac97_rstn LOC = AD10; -NET sys_flash_byten LOC = N22; - -NET sys_flash_a<*> IOSTANDARD = LVDCI_33; -NET sys_flash_a<*> SLEW = FAST; -NET sys_flash_a<*> DRIVE = 8; - -NET sys_flash_d<*> IOSTANDARD = LVCMOS33; -NET sys_flash_d<*> DRIVE = 12; -NET sys_flash_d<*> SLEW = FAST; -NET sys_flash_d<*> IOBDELAY = NONE; -NET sys_flash_d<*> PULLDOWN; - -NET sys_flash_rdn IOSTANDARD = LVDCI_33; -NET sys_flash_rdn SLEW = FAST; -NET sys_flash_rdn DRIVE = 8; - -NET sys_flash_wrn IOSTANDARD = LVDCI_33; -NET sys_flash_wrn SLEW = FAST; -NET sys_flash_wrn DRIVE = 8; - -NET sys_flash_ce IOSTANDARD = LVDCI_33; -NET sys_flash_ce SLEW = FAST; -NET sys_flash_ce DRIVE = 8; - -NET sys_flash_ac97_rstn IOSTANDARD = LVCMOS33; -NET sys_flash_ac97_rstn DRIVE = 8; -NET sys_flash_ac97_rstn SLEW = FAST; -NET sys_flash_ac97_rstn TIG; - -NET sys_flash_byten IOSTANDARD = LVCMOS33; -NET sys_flash_byten DRIVE = 8; -NET sys_flash_byten SLEW = FAST; -NET sys_flash_byten TIG; - -# VGA -NET sys_vga_blue<0> LOC = M21; # VGA_B0 -NET sys_vga_blue<1> LOC = M26; # VGA_B1 -NET sys_vga_blue<2> LOC = L26; # VGA_B2 -NET sys_vga_blue<3> LOC = C5; # VGA_B3 -NET sys_vga_blue<4> LOC = C7; # VGA_B4 -NET sys_vga_blue<5> LOC = B7; # VGA_B5 -NET sys_vga_blue<6> LOC = G8; # VGA_B6 -NET sys_vga_blue<7> LOC = F8; # VGA_B7 -NET sys_vga_blue<0> IOSTANDARD = LVCMOS33; -NET sys_vga_blue<1> IOSTANDARD = LVCMOS33; -NET sys_vga_blue<2> IOSTANDARD = LVCMOS33; -NET sys_vga_blue<*> SLEW = FAST; -NET sys_vga_blue<*> DRIVE = 8; - -NET sys_vga_clk LOC = AF8; -NET sys_vga_clk IOSTANDARD = LVDCI_33; -NET sys_vga_clk SLEW = FAST; -NET sys_vga_clk DRIVE = 8; - -NET sys_vga_green<0> LOC = M22; # VGA_G0 -NET sys_vga_green<1> LOC = M23; # VGA_G1 -NET sys_vga_green<2> LOC = M20; # VGA_G2 -NET sys_vga_green<3> LOC = E4; # VGA_G3 -NET sys_vga_green<4> LOC = D3; # VGA_G4 -NET sys_vga_green<5> LOC = H7; # VGA_G5 -NET sys_vga_green<6> LOC = H8; # VGA_G6 -NET sys_vga_green<7> LOC = C1; # VGA_G7 -NET sys_vga_green<0> IOSTANDARD = LVCMOS33; -NET sys_vga_green<1> IOSTANDARD = LVCMOS33; -NET sys_vga_green<2> IOSTANDARD = LVCMOS33; -NET sys_vga_green<*> SLEW = FAST; -NET sys_vga_green<*> DRIVE = 8; - -NET sys_vga_hsync LOC = C10; -NET sys_vga_hsync SLEW = FAST; -NET sys_vga_hsync DRIVE = 8; -#NET sys_vga_hsync IOSTANDARD = LVCMOS33; - -NET sys_vga_red<0> LOC = N23; #VGA_R0 -NET sys_vga_red<1> LOC = N24; #VGA_R1 -NET sys_vga_red<2> LOC = N25; #VGA_R2 -NET sys_vga_red<3> LOC = C2; #VGA_R3 -NET sys_vga_red<4> LOC = G7; #VGA_R4 -NET sys_vga_red<5> LOC = F7; #VGA_R5 -NET sys_vga_red<6> LOC = E5; #VGA_R6 -NET sys_vga_red<7> LOC = E6; #VGA_R7 -NET sys_vga_red<0> IOSTANDARD = LVCMOS33; -NET sys_vga_red<1> IOSTANDARD = LVCMOS33; -NET sys_vga_red<2> IOSTANDARD = LVCMOS33; -NET sys_vga_red<*> SLEW = FAST; -NET sys_vga_red<*> DRIVE = 8; - -NET sys_vga_vsync LOC = A8; -NET sys_vga_vsync SLEW = FAST; -NET sys_vga_vsync DRIVE = 8; -#NET sys_vga_vsync IOSTANDARD = LVCMOS33; - -NET sys_vga_blank_n LOC = M24; -NET sys_vga_blank_n SLEW = FAST; -NET sys_vga_blank_n DRIVE = 8; -NET sys_vga_blank_n IOSTANDARD = LVCMOS33; - -NET sys_vga_sync_n LOC = L23; -NET sys_vga_sync_n SLEW = FAST; -NET sys_vga_sync_n DRIVE = 8; -NET sys_vga_sync_n IOSTANDARD = LVCMOS33; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for AC97 Sound Controller -#------------------------------------------------------------------------------ -NET "sys_ac97_bit_clk" TNM_NET = "ac97_clk"; -TIMESPEC "TSACBITCLK" = PERIOD "ac97_clk" 80 ns HIGH 50 %; - -NET sys_ac97_bit_clk LOC = AE10; -NET sys_ac97_bit_clk IOSTANDARD = LVCMOS33; -NET sys_ac97_bit_clk PERIOD = 80; -NET sys_ac97_sdata_in LOC = AD16; -NET sys_ac97_sdata_in IOSTANDARD = LVCMOS33; -NET sys_ac97_sdata_out LOC = C8; -NET sys_ac97_sdata_out SLEW = FAST; -NET sys_ac97_ssync LOC = D9; -NET sys_ac97_ssync SLEW = FAST; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for PS/2 Ports -#------------------------------------------------------------------------------ - -#Keyboard -NET sys_ps2_0_clk LOC = D2; -NET sys_ps2_0_clk SLEW = SLOW; -NET sys_ps2_0_clk DRIVE = 2; -NET sys_ps2_0_clk TIG; -NET sys_ps2_0_data LOC = G9; -NET sys_ps2_0_data SLEW = SLOW; -NET sys_ps2_0_data DRIVE = 2; -NET sys_ps2_0_data TIG; - -#Mouse -NET sys_ps2_1_clk LOC = B14; -NET sys_ps2_1_clk SLEW = SLOW; -NET sys_ps2_1_clk DRIVE = 2; -NET sys_ps2_1_clk TIG; -NET sys_ps2_1_data LOC = C14; -NET sys_ps2_1_data SLEW = SLOW; -NET sys_ps2_1_data DRIVE = 2; -NET sys_ps2_1_data TIG; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for Ethernet PHY -#------------------------------------------------------------------------------ -# MDC -Net sys_phy_mdc LOC = D1; -Net sys_phy_mdc IOSTANDARD = LVCMOS25; - -# MDIO -Net sys_phy_mdio LOC = G4; -Net sys_phy_mdio IOSTANDARD = LVCMOS25; - -# /RST -Net sys_phy_rstn LOC = D10; -Net sys_phy_rstn TIG; - -# INT -Net sys_phy_int LOC = H4; -Net sys_phy_int TIG; - -#### Module Ethernet_MAC constraints - -NET "sys_phy_tx_clk" TNM_NET = "phy_tx_clk"; -TIMESPEC "TS_phy_tx_clk" = PERIOD "phy_tx_clk" 8.0 ns HIGH 50 %; - -NET "sys_phy_rx_clk" TNM_NET = "phy_rx_clk"; -TIMESPEC "TS_phy_rx_clk" = PERIOD "phy_rx_clk" 8.0 ns HIGH 50 %; - -Net sys_phy_crs LOC = D5; -Net sys_phy_col LOC = E3; - -Net sys_phy_tx_clk LOC=C15; -Net sys_phy_tx_en LOC = F4; -Net sys_phy_tx_er LOC=F3; -Net sys_phy_gtx_clk LOC=G10; - -Net sys_phy_rx_clk LOC=B15; -Net sys_phy_rx_dv LOC=A9; -Net sys_phy_rx_er LOC=B9; - -Net sys_phy_tx<0> LOC=H1; -Net sys_phy_tx<1> LOC=H2; -Net sys_phy_tx<2> LOC=H3; -Net sys_phy_tx<3> LOC=G1; -Net sys_phy_tx<4> LOC=G2; -Net sys_phy_tx<5> LOC=H5; -Net sys_phy_tx<6> LOC=H6; -Net sys_phy_tx<7> LOC=G3; - -Net sys_phy_rx<0> LOC=F1; -Net sys_phy_rx<1> LOC=E1; -Net sys_phy_rx<2> LOC=D4; -Net sys_phy_rx<3> LOC=C4; -Net sys_phy_rx<4> LOC=B4; -Net sys_phy_rx<5> LOC=A4; -Net sys_phy_rx<6> LOC=B3; -Net sys_phy_rx<7> LOC=A3; diff --git a/projects/mips_sys/ise92/mips_sys/mips_sys.prj b/projects/mips_sys/ise92/mips_sys/mips_sys.prj deleted file mode 100644 index 0916a32..0000000 --- a/projects/mips_sys/ise92/mips_sys/mips_sys.prj +++ /dev/null @@ -1,43 +0,0 @@ -vhdl work "../../../../lib/VGA_ctrl/src/vga_types.vhd" -vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd" -vhdl work "../../src/sdram_config.vhd" -vhdl work "../../../../lib/misc/utils_pkg.vhd" -vhdl work "../../../../lib/misc/dpram_1w1r.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/vga_sync.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd" -vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd" -vhdl work "../../../../lib/FIFO/src/gray_counter.vhd" -vhdl work "../../../../lib/uart/kcuart_tx.vhd" -vhdl work "../../../../lib/uart/kcuart_rx.vhd" -vhdl work "../../../../lib/uart/bbfifo_16x8.vhd" -vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/dpram.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd" -vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd" -vhdl work "../../../../lib/FIFO/src/async_fifo_ctrl.vhd" -vhdl work "../../src/sys_types.vhd" -vhdl work "../../src/ram_ld.vhd" -vhdl work "../../src/bootloader.ROM_ld.vhd" -vhdl work "../../../../lib/uart/uart_tx.vhd" -vhdl work "../../../../lib/uart/uart_rx.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" -vhdl work "../../../../lib/FIFO/src/fifo_async.vhd" -vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd" -vhdl work "../../../../lib/uart/uart_wb.vhd" -vhdl work "../../../../lib/misc/rom_wb.vhd" -vhdl work "../../../../lib/misc/ram_wb.vhd" -vhdl work "../../../../lib/misc/lcd_port.vhd" -vhdl work "../../../../lib/misc/gpio_wb.vhd" -vhdl work "../../../../lib/misc/clockgen_virtex4.vhd" -vhdl work "../../../../lib/misc/async_port_wb.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" -vhdl work "../../src/mips_sys.vhd" diff --git a/projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj b/projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj deleted file mode 100644 index 49db644..0000000 --- a/projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj +++ /dev/null @@ -1,43 +0,0 @@ -vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_types.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd" -vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd" -vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd" -vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_sync.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd" -vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd" -vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd" -vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd" -vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_timing.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\fonts\char_rom_fixedsys_8x16.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\dpram.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\clkgen_virtex4.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\async_fifo_ctrl.vhd" -vhdl work "W:\vhdl\projects\mips_sys\src\sys_types.vhd" -vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd" -vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd" -vhdl work "W:\vhdl\lib\uart\uart_tx.vhd" -vhdl work "W:\vhdl\lib\uart\uart_rx.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd" -vhdl work "W:\vhdl\lib\uart\uart_wb.vhd" -vhdl work "W:\vhdl\lib\misc\rom_wb.vhd" -vhdl work "W:\vhdl\lib\misc\ram_wb.vhd" -vhdl work "W:\vhdl\lib\misc\lcd_port.vhd" -vhdl work "W:\vhdl\lib\misc\gpio_wb.vhd" -vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd" -vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend64.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd" -vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd" diff --git a/projects/mips_sys/ise92/mips_sys/ucf/systest.ucf b/projects/mips_sys/ise92/mips_sys/ucf/systest.ucf deleted file mode 100644 index 07b8d92..0000000 --- a/projects/mips_sys/ise92/mips_sys/ucf/systest.ucf +++ /dev/null @@ -1,469 +0,0 @@ -# -# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE. -# -# (c) Copyright 2005 Xilinx, Inc. -# All rights reserved. -# - -CONFIG STEPPING = "ES"; - -# Bus clock nets -NET "clk" TNM_NET = "clk"; -TIMESPEC "TS_clk" = PERIOD "clk" 9.95 ns HIGH 50 %; - -NET "inst_vga_frontend/inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk"; -#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %; -TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG; - -NET "sys_clk_in" LOC = "AE14"; -NET sys_clk_in IOSTANDARD = LVCMOS33; -NET "sys_rst_n_in" LOC = "D6"; -NET sys_rst_n_in PULLUP; -NET "sys_rst_n_in" TIG; -NET "rst" TIG; - -# Locate DCM/BUFG - Tools can probably figure them out automatically -# but just LOC them down to be safe -#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2; -#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1; - -# GOOD -INST "inst_mips_top" AREA_GROUP = "AG_inst_mips_top" ; -AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y85:SLICE_X39Y0 ; -AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y10, RAMB16_X1Y0:RAMB16_X1Y10, RAMB16_X2Y0:RAMB16_X2Y10, RAMB16_X3Y0:RAMB16_X3Y10 ; - -//////////////////////////////////////////////////////////////////////////// -// Misc Board Signals -//////////////////////////////////////////////////////////////////////////// - -NET sys_error<0> LOC = V6; -NET sys_error<1> LOC = L24; -NET sys_error<*> IOSTANDARD = LVCMOS33; -NET sys_error<*> DRIVE = 2; -NET sys_error<*> TIG; - -//////////////////////////////////////////////////////////////////////////// -// RS-232 -//////////////////////////////////////////////////////////////////////////// -NET sys_rx LOC = W2; -NET sys_rx IOSTANDARD = LVCMOS33; -NET sys_rx TIG; -NET "sys_tx" LOC = "W1"; -NET sys_tx IOSTANDARD = LVCMOS33; -NET "sys_tx" TIG; - -//////////////////////////////////////////////////////////////////////////// -// Buttons, LEDs, and DIP Switches -//////////////////////////////////////////////////////////////////////////// -# GPLED 0-3 -NET "sys_led<0>" LOC = "G5"; #GPLED0 -NET "sys_led<1>" LOC = "G6"; #GPLED1 -NET "sys_led<2>" LOC = "A11"; #GPLED2 -NET "sys_led<3>" LOC = "A12"; #GPLED3 -# North-East-South-West-Center LEDs -NET "sys_led<4>" LOC = "F9"; # W LED -NET "sys_led<5>" LOC = "E2"; # N LED -NET "sys_led<6>" LOC = "E10"; # E LED -NET "sys_led<7>" LOC = "A5"; # S LED -NET "sys_led<8>" LOC = "C6"; # C LED -NET "sys_led<*>" TIG; -NET "sys_led<*>" SLEW = SLOW; -NET "sys_led<*>" DRIVE = 2; -#NET "sys_led<*>" IOSTANDARD = LVCMOS33; -# North-East-South-West-Center Buttons -NET "sys_btn<0>" LOC = "E9"; # W Button -NET "sys_btn<1>" LOC = "E7"; # N Button -NET "sys_btn<2>" LOC = "F10"; # E Button -NET "sys_btn<3>" LOC = "A6"; # S Button -NET "sys_btn<4>" LOC = "B6"; # C Button -NET "sys_btn<*>" TIG; -NET "sys_btn<*>" PULLDOWN; -#NET "sys_btn<*>" IOSTANDARD = LVCMOS33; -# Dip Switches 1-8 -NET "sys_dip<7>" LOC = "U24"; # DIP SW 8 -NET "sys_dip<6>" LOC = "U25"; # DIP SW 7 -NET "sys_dip<5>" LOC = "V23"; # DIP SW 6 -NET "sys_dip<4>" LOC = "U23"; # DIP SW 5 -NET "sys_dip<3>" LOC = "U26"; # DIP SW 4 -NET "sys_dip<2>" LOC = "T26"; # DIP SW 3 -NET "sys_dip<1>" LOC = "R19"; # DIP SW 2 -NET "sys_dip<0>" LOC = "R20"; # DIP SW 1 -NET "sys_dip<*>" PULLDOWN; -NET "sys_dip<*>" IOSTANDARD = LVCMOS33; -NET "sys_dip<*>" TIG; -//////////////////////////////////////////////////////////////////////////// -// LCD -//////////////////////////////////////////////////////////////////////////// -NET sys_lcd_e LOC = AE13; # LCD_E -NET sys_lcd_e IOSTANDARD = LVCMOS33; -NET sys_lcd_e SLEW = SLOW; -NET sys_lcd_e DRIVE = 2; -NET sys_lcd_e TIG; -NET sys_lcd_rs LOC = AC17; # LCD_RS -NET sys_lcd_rs IOSTANDARD = LVCMOS33; -NET sys_lcd_rs SLEW = SLOW; -NET sys_lcd_rs DRIVE = 2; -NET sys_lcd_rs TIG; -NET sys_lcd_rw LOC = AB17; # LCD_RW -NET sys_lcd_rw IOSTANDARD = LVCMOS33; -NET sys_lcd_rw SLEW = SLOW; -NET sys_lcd_rw DRIVE = 2; -NET sys_lcd_rw TIG; -NET sys_lcd_d<3> LOC = AF12; # LCD_DB7 -NET sys_lcd_d<2> LOC = AE12; # LCD_DB6 -NET sys_lcd_d<1> LOC = AC10; # LCD_DB5 -NET sys_lcd_d<0> LOC = AB10; # LCD_DB4 -NET sys_lcd_d<*> IOSTANDARD = LVCMOS33; -NET sys_lcd_d<*> SLEW = SLOW; -NET sys_lcd_d<*> DRIVE = 2; -NET sys_lcd_d<*> PULLDOWN; -NET sys_lcd_d<*> TIG; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for DDR Controllers -#------------------------------------------------------------------------------ - -NET sys_sdr_a_q<0> LOC = C26; # DDR_A0 -NET sys_sdr_a_q<1> LOC = E17; # DDR_A1 -NET sys_sdr_a_q<2> LOC = D18; # DDR_A2 -NET sys_sdr_a_q<3> LOC = C19; # DDR_A3 -NET sys_sdr_a_q<4> LOC = F17; # DDR_A4 -NET sys_sdr_a_q<5> LOC = B18; # DDR_A5 -NET sys_sdr_a_q<6> LOC = B20; # DDR_A6 -NET sys_sdr_a_q<7> LOC = C20; # DDR_A7 -NET sys_sdr_a_q<8> LOC = D20; # DDR_A8 -NET sys_sdr_a_q<9> LOC = C21; # DDR_A9 -NET sys_sdr_a_q<10> LOC = A18; # DDR_A10 -NET sys_sdr_a_q<11> LOC = B21; # DDR_A11 -NET sys_sdr_a_q<12> LOC = A24; # DDR_A12 -NET sys_sdr_ba_q<0> LOC = B12; # DDR_BA0 -NET sys_sdr_ba_q<1> LOC = A16; # DDR_BA1 -NET sys_sdr_cas_qn LOC = F23; # DDR_CAS_N -NET sys_sdr_cke_q LOC = G22; # DDR_CKE -NET sys_sdr_cs_qn LOC = G21; # DDR_CS_N -NET sys_sdr_ras_qn LOC = F24; # DDR_RAS_N -NET sys_sdr_we_qn LOC = A23; # DDR_WE_N - -NET sys_sdr_clk_p LOC = A10; # DDR_CK1_P -NET sys_sdr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK) -NET sys_sdr_clk_n LOC = B10; # DDR_CK1_N - -NET sys_sdr_dm_q<0> LOC = G19; # DDR_DM0 -NET sys_sdr_dm_q<1> LOC = G24; # DDR_DM1 -NET sys_sdr_dm_q<2> LOC = G20; # DDR_DM2 -NET sys_sdr_dm_q<3> LOC = C22; # DDR_DM3 - -NET sys_sdr_dqs_q<0> LOC = D25; # DDR_DQS0 -NET sys_sdr_dqs_q<1> LOC = G18; # DDR_DQS1 -NET sys_sdr_dqs_q<2> LOC = G17; # DDR_DQS2 -NET sys_sdr_dqs_q<3> LOC = D26; # DDR_DQS3 - -NET sys_sdr_data<0> LOC = H20; # DDR_D0 -NET sys_sdr_data<1> LOC = E23; # DDR_D1 -NET sys_sdr_data<2> LOC = H26; # DDR_D2 -NET sys_sdr_data<3> LOC = H22; # DDR_D3 -NET sys_sdr_data<4> LOC = E25; # DDR_D4 -NET sys_sdr_data<5> LOC = E26; # DDR_D5 -NET sys_sdr_data<6> LOC = F26; # DDR_D6 -NET sys_sdr_data<7> LOC = E24; # DDR_D7 -NET sys_sdr_data<8> LOC = E20; # DDR_D8 -NET sys_sdr_data<9> LOC = A22; # DDR_D9 -NET sys_sdr_data<10> LOC = C23; # DDR_D10 -NET sys_sdr_data<11> LOC = C24; # DDR_D11 -NET sys_sdr_data<12> LOC = A20; # DDR_D12 -NET sys_sdr_data<13> LOC = A21; # DDR_D13 -NET sys_sdr_data<14> LOC = D24; # DDR_D14 -NET sys_sdr_data<15> LOC = E18; # DDR_D15 -NET sys_sdr_data<16> LOC = F18; # DDR_D16 -NET sys_sdr_data<17> LOC = A19; # DDR_D17 -NET sys_sdr_data<18> LOC = F19; # DDR_D18 -NET sys_sdr_data<19> LOC = B23; # DDR_D19 -NET sys_sdr_data<20> LOC = E21; # DDR_D20 -NET sys_sdr_data<21> LOC = D22; # DDR_D21 -NET sys_sdr_data<22> LOC = D23; # DDR_D22 -NET sys_sdr_data<23> LOC = B24; # DDR_D23 -NET sys_sdr_data<24> LOC = E22; # DDR_D24 -NET sys_sdr_data<25> LOC = F20; # DDR_D25 -NET sys_sdr_data<26> LOC = H23; # DDR_D26 -NET sys_sdr_data<27> LOC = G25; # DDR_D27 -NET sys_sdr_data<28> LOC = G26; # DDR_D28 -NET sys_sdr_data<29> LOC = H25; # DDR_D29 -NET sys_sdr_data<30> LOC = H24; # DDR_D30 -NET sys_sdr_data<31> LOC = H21; # DDR_D31 - -NET sys_sdr_a_q<*> IOSTANDARD = SSTL2_I; -NET sys_sdr_a_q<*> FAST; - -NET sys_sdr_ba_q<*> IOSTANDARD = SSTL2_I; -NET sys_sdr_ba_q<*> FAST; - -NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_cas_qn FAST; - -NET sys_sdr_cke_q IOSTANDARD = SSTL2_I; -NET sys_sdr_cke_q FAST; - -NET sys_sdr_clk_p IOSTANDARD = SSTL2_I; -NET sys_sdr_clk_p FAST; -NET sys_sdr_clk_fb IOSTANDARD = LVCMOS25; -NET sys_sdr_clk_fb IOBDELAY = NONE; -NET sys_sdr_clk_n IOSTANDARD = SSTL2_I; -NET sys_sdr_clk_n FAST; - -NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_cas_qn FAST; - -NET sys_sdr_cs_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_cs_qn FAST; - -NET sys_sdr_ras_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_ras_qn FAST; - -NET sys_sdr_we_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_we_qn FAST; - -NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II; -NET sys_sdr_dqs_q<*> IOBDELAY = NONE; -NET sys_sdr_dqs_q<*> FAST; - -NET sys_sdr_dm_q<*> IOSTANDARD = SSTL2_II; -NET sys_sdr_dm_q<*> IOBDELAY = NONE; -NET sys_sdr_dm_q<*> FAST; - -NET sys_sdr_data<*> IOSTANDARD = SSTL2_II; -NET sys_sdr_data<*> IOBDELAY = NONE; -NET sys_sdr_data<*> FAST; - -#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n"; - -NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p"; -NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n"; - -# Timing Constraint for DDR Feedback Clock -NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p; - -# USB -NET sys_usb_a<0> LOC = Y10; -NET sys_usb_a<1> LOC = AA10; -NET sys_usb_a<*> IOSTANDARD = LVCMOS33; - -NET sys_usb_d<0> LOC = AB7; -NET sys_usb_d<1> LOC = AC9; -NET sys_usb_d<2> LOC = AB9; -NET sys_usb_d<3> LOC = AE6; -NET sys_usb_d<4> LOC = AD6; -NET sys_usb_d<5> LOC = AF9; -NET sys_usb_d<6> LOC = AE9; -NET sys_usb_d<7> LOC = AD8; -NET sys_usb_d<8> LOC = AC8; -NET sys_usb_d<9> LOC = AF4; -NET sys_usb_d<10> LOC = AE4; -NET sys_usb_d<11> LOC = AD3; -NET sys_usb_d<12> LOC = AC3; -NET sys_usb_d<13> LOC = AF6; -NET sys_usb_d<14> LOC = AF5; -NET sys_usb_d<15> LOC = AA7; -NET sys_usb_d<*> IOSTANDARD = LVCMOS33; -NET sys_usb_d<*> SLEW = FAST; -NET sys_usb_d<*> DRIVE = 8; -NET sys_usb_d<*> PULLDOWN; - -NET sys_usb_rdn LOC = AA8; -NET sys_usb_rdn IOSTANDARD = LVCMOS33; -NET sys_usb_rdn SLEW = FAST; -NET sys_usb_rdn DRIVE = 8; - -NET sys_usb_wrn LOC = Y8; -NET sys_usb_wrn IOSTANDARD = LVCMOS33; -NET sys_usb_wrn SLEW = FAST; -NET sys_usb_wrn DRIVE = 8; - -NET sys_usb_csn LOC = AF10; -NET sys_usb_csn IOSTANDARD = LVCMOS33; -NET sys_usb_csn SLEW = FAST; -NET sys_usb_csn DRIVE = 8; - -NET sys_usb_rstn LOC = A7; -NET sys_usb_rstn IOSTANDARD = LVCMOS25; -NET sys_usb_rstn TIG; - -NET sys_usb_int LOC = V5; -NET sys_usb_int IOSTANDARD = LVCMOS33; -NET sys_usb_int PULLDOWN; -NET sys_usb_int TIG; - -# FLASH -NET sys_flash_a<24> LOC = T21; -NET sys_flash_a<23> LOC = U20; -NET sys_flash_a<22> LOC = T19; -NET sys_flash_a<21> LOC = AC5; -NET sys_flash_a<20> LOC = AB5; -NET sys_flash_a<19> LOC = AC4; -NET sys_flash_a<18> LOC = AB4; -NET sys_flash_a<17> LOC = AB3; -NET sys_flash_a<16> LOC = AA4; -NET sys_flash_a<15> LOC = AA3; -NET sys_flash_a<14> LOC = W5; -NET sys_flash_a<13> LOC = W6; -NET sys_flash_a<12> LOC = W3; -NET sys_flash_a<11> LOC = AF3; -NET sys_flash_a<10> LOC = AE3; -NET sys_flash_a<9> LOC = AD2; -NET sys_flash_a<8> LOC = AD1; -NET sys_flash_a<7> LOC = AC2; -NET sys_flash_a<6> LOC = AC1; -NET sys_flash_a<5> LOC = AB2; -NET sys_flash_a<4> LOC = AB1; -NET sys_flash_a<3> LOC = AA1; -NET sys_flash_a<2> LOC = Y2; -NET sys_flash_a<1> LOC = Y1; -NET sys_flash_a<0> LOC = T20; - -NET sys_flash_d<31> LOC = F14; -NET sys_flash_d<30> LOC = F13; -NET sys_flash_d<29> LOC = F12; -NET sys_flash_d<28> LOC = F11; -NET sys_flash_d<27> LOC = F16; -NET sys_flash_d<26> LOC = F15; -NET sys_flash_d<25> LOC = D14; -NET sys_flash_d<24> LOC = D13; -NET sys_flash_d<23> LOC = D15; -NET sys_flash_d<22> LOC = E14; -NET sys_flash_d<21> LOC = C11; -NET sys_flash_d<20> LOC = D11; -NET sys_flash_d<19> LOC = D16; -NET sys_flash_d<18> LOC = C16; -NET sys_flash_d<17> LOC = E13; -NET sys_flash_d<16> LOC = D12; -NET sys_flash_d<15> LOC = AA14; -NET sys_flash_d<14> LOC = AB14; -NET sys_flash_d<13> LOC = AC12; -NET sys_flash_d<12> LOC = AC11; -NET sys_flash_d<11> LOC = AA16; -NET sys_flash_d<10> LOC = AA15; -NET sys_flash_d<9> LOC = AB13; -NET sys_flash_d<8> LOC = AA13; -NET sys_flash_d<7> LOC = AC14; -NET sys_flash_d<6> LOC = AD14; -NET sys_flash_d<5> LOC = AA12; -NET sys_flash_d<4> LOC = AA11; -NET sys_flash_d<3> LOC = AC16; -NET sys_flash_d<2> LOC = AC15; -NET sys_flash_d<1> LOC = AC13; -NET sys_flash_d<0> LOC = AD13; -NET sys_flash_rdn LOC = AC6; -NET sys_flash_wrn LOC = AB6; -NET sys_flash_ce LOC = W7; -NET sys_flash_rstn LOC = AD10; -NET sys_flash_byten LOC = N22; - -NET sys_flash_a<*> IOSTANDARD = LVDCI_33; -NET sys_flash_a<*> SLEW = FAST; -NET sys_flash_a<*> DRIVE = 8; - -NET sys_flash_d<*> IOSTANDARD = LVCMOS33; -NET sys_flash_d<*> DRIVE = 12; -NET sys_flash_d<*> SLEW = FAST; -NET sys_flash_d<*> PULLDOWN; - -NET sys_flash_rdn IOSTANDARD = LVDCI_33; -NET sys_flash_rdn SLEW = FAST; -NET sys_flash_rdn DRIVE = 8; - -NET sys_flash_wrn IOSTANDARD = LVDCI_33; -NET sys_flash_wrn SLEW = FAST; -NET sys_flash_wrn DRIVE = 8; - -NET sys_flash_ce IOSTANDARD = LVDCI_33; -NET sys_flash_ce SLEW = FAST; -NET sys_flash_ce DRIVE = 8; - -NET sys_flash_rstn IOSTANDARD = LVCMOS33; -NET sys_flash_rstn DRIVE = 8; -NET sys_flash_rstn SLEW = FAST; -NET sys_flash_rstn TIG; - -NET sys_flash_byten IOSTANDARD = LVCMOS33; -NET sys_flash_byten DRIVE = 8; -NET sys_flash_byten SLEW = FAST; -NET sys_flash_byten TIG; - -# VGA -NET sys_vga_blue<0> LOC = M21; # VGA_B0 -NET sys_vga_blue<1> LOC = M26; # VGA_B1 -NET sys_vga_blue<2> LOC = L26; # VGA_B2 -NET sys_vga_blue<3> LOC = C5; # VGA_B3 -NET sys_vga_blue<4> LOC = C7; # VGA_B4 -NET sys_vga_blue<5> LOC = B7; # VGA_B5 -NET sys_vga_blue<6> LOC = G8; # VGA_B6 -NET sys_vga_blue<7> LOC = F8; # VGA_B7 -NET sys_vga_blue<0> IOSTANDARD = LVCMOS33; -NET sys_vga_blue<1> IOSTANDARD = LVCMOS33; -NET sys_vga_blue<2> IOSTANDARD = LVCMOS33; -NET sys_vga_blue<*> SLEW = FAST; -NET sys_vga_blue<*> DRIVE = 8; - -NET sys_vga_clk LOC = AF8; -NET sys_vga_clk IOSTANDARD = LVDCI_33; -NET sys_vga_clk SLEW = FAST; -NET sys_vga_clk DRIVE = 8; - -NET sys_vga_green<0> LOC = M22; # VGA_G0 -NET sys_vga_green<1> LOC = M23; # VGA_G1 -NET sys_vga_green<2> LOC = M20; # VGA_G2 -NET sys_vga_green<3> LOC = E4; # VGA_G3 -NET sys_vga_green<4> LOC = D3; # VGA_G4 -NET sys_vga_green<5> LOC = H7; # VGA_G5 -NET sys_vga_green<6> LOC = H8; # VGA_G6 -NET sys_vga_green<7> LOC = C1; # VGA_G7 -NET sys_vga_green<0> IOSTANDARD = LVCMOS33; -NET sys_vga_green<1> IOSTANDARD = LVCMOS33; -NET sys_vga_green<2> IOSTANDARD = LVCMOS33; -NET sys_vga_green<*> SLEW = FAST; -NET sys_vga_green<*> DRIVE = 8; - -NET sys_vga_hsync LOC = C10; -NET sys_vga_hsync SLEW = FAST; -NET sys_vga_hsync DRIVE = 8; -#NET sys_vga_hsync IOSTANDARD = LVCMOS33; - -NET sys_vga_red<0> LOC = N23; #VGA_R0 -NET sys_vga_red<1> LOC = N24; #VGA_R1 -NET sys_vga_red<2> LOC = N25; #VGA_R2 -NET sys_vga_red<3> LOC = C2; #VGA_R3 -NET sys_vga_red<4> LOC = G7; #VGA_R4 -NET sys_vga_red<5> LOC = F7; #VGA_R5 -NET sys_vga_red<6> LOC = E5; #VGA_R6 -NET sys_vga_red<7> LOC = E6; #VGA_R7 -NET sys_vga_red<0> IOSTANDARD = LVCMOS33; -NET sys_vga_red<1> IOSTANDARD = LVCMOS33; -NET sys_vga_red<2> IOSTANDARD = LVCMOS33; -NET sys_vga_red<*> SLEW = FAST; -NET sys_vga_red<*> DRIVE = 8; - -NET sys_vga_vsync LOC = A8; -NET sys_vga_vsync SLEW = FAST; -NET sys_vga_vsync DRIVE = 8; -#NET sys_vga_vsync IOSTANDARD = LVCMOS33; - -NET sys_vga_blank_n LOC = M24; -NET sys_vga_blank_n SLEW = FAST; -NET sys_vga_blank_n DRIVE = 8; -NET sys_vga_blank_n IOSTANDARD = LVCMOS33; - -NET sys_vga_sync_n LOC = L23; -NET sys_vga_sync_n SLEW = FAST; -NET sys_vga_sync_n DRIVE = 8; -NET sys_vga_sync_n IOSTANDARD = LVCMOS33; diff --git a/projects/mips_sys/sim/tb_mips_sys.fdo b/projects/mips_sys/sim/tb_mips_sys.fdo deleted file mode 100644 index 6535215..0000000 --- a/projects/mips_sys/sim/tb_mips_sys.fdo +++ /dev/null @@ -1,118 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -# Configs -vcom -explicit -93 "../src/sdram_config_sim.vhd" - -# Packages -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_types.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_instr.vhd" -vcom -explicit -93 "../../../lib/FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd" -vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd" - -# RAMs -vcom -explicit -93 "../../../lib/rams/dpram_1w1r2c_ro_sim.vhd" -vcom -explicit -93 "../../../lib/rams/dpram_2w2r2c_ra_sim.vhd" -vcom -explicit -93 "../../../lib/rams/dpram_1w1r2c_ra_sim.vhd" -#vcom -explicit -93 "../../../lib/misc/dpram_1w1r.vhd" - -# FIFOS -vcom -explicit -93 "../../../lib/FIFO/src/gray_counter.vhd" -vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync_ctrl.vhd" -vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync.vhd" -vcom -explicit -93 "../../../lib/FIFO/src/fifo_async_ctrl.vhd" -vcom -explicit -93 "../../../lib/FIFO/src/fifo_async.vhd" - -# CPU -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_reg.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_alu.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_cop.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_dcache.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_icache.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_biu.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_top.vhd" -vcom -explicit -93 "../src/bootloader.ROM.vhd" -vcom -explicit -93 "../../../lib/misc/rom_wb.vhd" - -# VGA -vcom -explicit -93 "../../../lib/VGA_ctrl/src/fonts/char_rom_c64.vhd" -vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_types.vhd" -vcom -explicit -93 "../../../lib/VGA_ctrl/src/char_gen.vhd" -vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_sync.vhd" -vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_timing.vhd" -vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_backend.vhd" -vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_frontend64.vhd" - -# UART -vcom -explicit -93 "../../../lib/uart/bbfifo_16x8.vhd" -vcom -explicit -93 "../../../lib/uart/kcuart_rx.vhd" -vcom -explicit -93 "../../../lib/uart/kcuart_tx.vhd" -vcom -explicit -93 "../../../lib/uart/uart_rx.vhd" -vcom -explicit -93 "../../../lib/uart/uart_tx.vhd" -vcom -explicit -93 "../../../lib/uart/uart_wb.vhd" - -# PS2 -vcom -explicit -93 "../../../lib/ps2_port/src/debounce.vhd" -vcom -explicit -93 "../../../lib/ps2_port/src/ps2_core.vhd" -vcom -explicit -93 "../../../lib/ps2_port/src/ps2_phy_virtex.vhd" -vcom -explicit -93 "../../../lib/ps2_port/src/ps2_wb.vhd" - -# GPIO -vcom -explicit -93 "../../../lib/misc/gpio_wb.vhd" - -# LCD -vcom -explicit -93 "../../../lib/misc/lcd_port.vhd" - -# Flash and USB -vcom -explicit -93 "../../../lib/misc/async_types.vhd" -vcom -explicit -93 "../../../lib/misc/async_port_wb.vhd" -vcom -explicit -93 "../../../lib/misc/flash_port_wb.vhd" -vcom -explicit -93 "../src/async_defs_sim.vhd" - -# Sync SRAM -vcom -explicit -93 "../../../lib/SSRAM/src/package_utility.vhd" -vcom -explicit -93 "../../../lib/SSRAM/src/CY7C1354B.vhd" -vcom -explicit -93 "../../../lib/SSRAM/src/ssram_port_wb.vhd" - -# SDRAM -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" - -# AC-97 -vcom -explicit -93 "../../../lib/misc/singleshot.vhd" -vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_out.vhd" -vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_in.vhd" -vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_io.vhd" -vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac97_wb.vhd" - -# Ethernet MAC -vcom -explicit -93 "../../../lib/emac/src/emac_types.vhd" -vcom -explicit -93 "../../../lib/emac/src/piso.vhd" -vcom -explicit -93 "../../../lib/emac/src/sipo.vhd" -vcom -explicit -93 "../../../lib/emac/src/crc32.vhd" -vcom -explicit -93 "../../../lib/emac/src/emac_rx.vhd" -vcom -explicit -93 "../../../lib/emac/src/emac_tx.vhd" -vcom -explicit -93 "../../../lib/emac/src/emac_top_jb.vhd" - -# Clock Generator -vcom -explicit -93 "../src/clockgen_virtex4.vhd" - -# Top and TB -vcom -explicit -93 "../src/mips_sys_sim.vhd" -vcom -explicit -93 "../src/tb_mips_sys.vhd" - -vsim -t 1ps -lib work tb_mips_sys -do {tb_mips_sys.wdo} -view wave -view structure -view signals -run 10 ms diff --git a/projects/mips_sys/sim/tb_mips_sys.wdo b/projects/mips_sys/sim/tb_mips_sys.wdo deleted file mode 100644 index e79c1ce..0000000 --- a/projects/mips_sys/sim/tb_mips_sys.wdo +++ /dev/null @@ -1,457 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider UUT -add wave -noupdate -format Logic /tb_mips_sys/uut/rst_o -add wave -noupdate -format Logic /tb_mips_sys/uut/nmi -add wave -noupdate -format Logic /tb_mips_sys/uut/rst_in -add wave -noupdate -format Logic /tb_mips_sys/sys_rst_n_in -add wave -noupdate -format Logic /tb_mips_sys/sys_clk_in -add wave -noupdate -format Literal /tb_mips_sys/dip -add wave -noupdate -format Literal /tb_mips_sys/btn -add wave -noupdate -format Literal /tb_mips_sys/led -add wave -noupdate -format Logic /tb_mips_sys/sys_phy_rstn -add wave -noupdate -format Logic /tb_mips_sys/sys_phy_mdc -add wave -noupdate -format Logic /tb_mips_sys/sys_phy_mdio -add wave -noupdate -format Logic /tb_mips_sys/sys_phy_int -add wave -noupdate -format Logic /tb_mips_sys/sys_ps2_clk -add wave -noupdate -format Logic /tb_mips_sys/sys_ps2_data -add wave -noupdate -format Logic /tb_mips_sys/sys_rx -add wave -noupdate -format Logic /tb_mips_sys/sys_tx -add wave -noupdate -format Literal /tb_mips_sys/sys_lcd_d -add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_e -add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rs -add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rw -add wave -noupdate -format Logic /tb_mips_sys/refresh -add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_fb -add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_p -add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_n -add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cke_q -add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cs_qn -add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_ras_qn -add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cas_qn -add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_we_qn -add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dqs_q -add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_ba_q -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_a_q -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_data -add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dm_q -add wave -noupdate -format Literal /tb_mips_sys/sys_error -add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o -add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o -add wave -noupdate -format Logic /tb_mips_sys/uut/we_o -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o -add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o -add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i -add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i -add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o -add wave -noupdate -format Literal /tb_mips_sys/uut/mem_area -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_flash -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_usb -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_sdram -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_rom -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_gpio -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart0 -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart1 -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart2 -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_vga -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ssram -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ac97 -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ps2 -add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o -add wave -noupdate -divider {Clock Gen} -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/rst_in -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/clk_in -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_clk_out -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/vga_clk_out -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk_fb_in -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk0_out -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk270_out -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_clk0_out -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_clk270_out -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_rst_out -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_cnt -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_pipe0 -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_pipe1 -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/vga_fx_lock -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_fx_lock -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_lock -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_lock -add wave -noupdate -divider Arbiter -add wave -noupdate -format Literal /tb_mips_sys/uut/arb_idx -add wave -noupdate -format Literal /tb_mips_sys/uut/arb_req -add wave -noupdate -format Literal /tb_mips_sys/uut/arb_gnt -add wave -noupdate -divider {Ethernet MAC} -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/eth_tx_reg -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/clk_i -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/rst_i -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/int_o -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/cyc_i -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/stb_i -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_emac_jb/sel_i -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/we_i -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/ack_o -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/srdy_o -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/mrdy_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/addr_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/dat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/dat_o -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/rx_int_en -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/tx_int_en -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/irq_rx -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/irq_tx -add wave -noupdate -divider AC97 -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_sdata_in -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_bit_clk -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_sdata_out -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_ssync -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/cmd_reg_we -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/cmd_pending -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/stat_valid -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/stat_pending -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_frame_valid -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_frame -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_tx -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_status -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_ac97_wb/request -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_data_start -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/ac97_stat -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_frame_sync -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_rx -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_tx -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_re -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_we -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_full -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_empty -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_almost_full -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_almost_empty -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/ac_frame_reg -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_ssync -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_bit_clk -add wave -noupdate -format Logic /tb_mips_sys/ac_synced -add wave -noupdate -divider {CPU Master} -add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o_cpu -add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o_cpu -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o_cpu -add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o_cpu -add wave -noupdate -format Logic /tb_mips_sys/uut/we_o_cpu -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_cpu -add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_cpu -add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_cpu -add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_cpu -add wave -noupdate -divider {VGA Master} -add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o_vga -add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o_vga -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o_vga -add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o_vga -add wave -noupdate -format Logic /tb_mips_sys/uut/we_o_vga -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_vga -add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_vga -add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_vga -add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_vga -add wave -noupdate -divider BUI -add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o -add wave -noupdate -format Literal -label .op -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.op -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/read_cycle -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/ack -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/dat -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_dout -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_re -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_we -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_full -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_empty -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_rdy -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_dout -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_re -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_we -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_full -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_empty -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bus_idle -add wave -noupdate -divider VGA-Slave -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/rst_i -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/clk_i -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/int_o -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/cyc_i -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/srdy_o -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/mrdy_i -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/sel_i -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/we_i -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/stb_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/addr_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/sdat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/sdat_o -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/ack_o -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_reset -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/blit_finish_strobe -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_re -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_we -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_empty -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_bsy -add wave -noupdate -divider -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_addr_src_0 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_addr_src_1 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_addr_dst -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_dimx_src_0 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_dimx_src_1 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_dimx_dst -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_ny -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_const_color -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_func -add wave -noupdate -divider -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_reset -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_request -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_const_color_en -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_request_set -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/blit_finish_strobe -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_complete_int -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_complete_int_ack -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_complete_int_en -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_empty_int -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_empty_int_ack -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_empty_int_en -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_din -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_dout -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_re -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_we -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_empty -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_full -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_bsy -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_avail -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_addr_src_0 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_addr_src_1 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_addr_dst -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_dimx_src_0 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_dimx_src_1 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_dimx_dst -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_nx -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_ny -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_cc -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_func -add wave -noupdate -divider USB -add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o -add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rstn -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_d -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_a -add wave -noupdate -format Logic /tb_mips_sys/sys_usb_csn -add wave -noupdate -format Logic /tb_mips_sys/sys_usb_wrn -add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rdn -add wave -noupdate -format Logic /tb_mips_sys/sys_usb_int -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_usb_port/s -add wave -noupdate -divider Flash -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ac97_rstn -add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/as -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/s -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_we_n -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_oe_n -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a -add wave -noupdate -format Logic /tb_mips_sys/sys_flash_ce -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_a -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_do -add wave -noupdate -format Logic /tb_mips_sys/uut/flash_oe_n -add wave -noupdate -format Logic /tb_mips_sys/uut/flash_we_n -add wave -noupdate -format Logic /tb_mips_sys/uut/flash_d_drv -add wave -noupdate -format Logic /tb_mips_sys/uut/flash_bsy -add wave -noupdate -divider {Sync SRAM} -add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_clk -add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_cke_n -add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_ce_n -add wave -noupdate -format Literal /tb_mips_sys/sys_ssram_dp -add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_adv -add wave -noupdate -format Literal /tb_mips_sys/sys_ssram_bw_n -add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_mode -add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_zz -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_we_n -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_oe_n -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/ssram_a -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/ssram_do -add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_oe_n -add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_we_n -add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_d_drv -add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_bsy -add wave -noupdate -divider {MIPS TOP} -add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/hdu -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_run -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_reg_dual/reg_mem -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/id_stage -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/mem_stage -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/wb_stage -add wave -noupdate -divider {CPU DMEM} -add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o -add wave -noupdate -divider {CPU IMEM} -add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o -add wave -noupdate -divider {User ROM} -add wave -noupdate -divider UUT -add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc -add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sys_sdr_a_q -add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_ba_q -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cas_qn -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cke_q -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_fb -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_n -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_p -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cs_qn -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sys_sdr_data -add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dm_q -add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dqs_q -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_ras_qn -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_we_qn -add wave -noupdate -divider I-Cache -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/rst_i -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/clk_i -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/ack_i -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/srdy_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/addr_o -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/dat_i -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/stb_o -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cyc_o -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/ctrl -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_en -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_dout -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_busy -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/s -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/sn -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_match -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_match_inv -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/request_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cache_index_inv -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_inv -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_reg_inv -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cache_entry_in -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cache_entry_out -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cache_entry_out_inv -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/data_ram_we -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_ram_we -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_count -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_count_en -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_count_rdy -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/flush_count -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/flush_count_rst -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/flush_count_en -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/flush_count_rdy -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/request_count -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/request_count_en -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/request_count_rdy -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/invalidate_all -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/invalidate_ack -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/invalidate_en -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/invalidate_req -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/req_tag -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/req_cache_index -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/req_word_index -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_tag -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_cache_index -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_word_index -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_tag -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_cache_index -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_word_index -add wave -noupdate -divider D-Cache -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/rst_i -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/clk_i -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/ack_i -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/srdy_i -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/mrdy_o -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/addr_o -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/dat_i -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/stb_o -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cyc_o -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/ctrl -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_en -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_we -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_be -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_dout -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_busy -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/s -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/sn -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_hit -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_match -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_hit_inv -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_match_inv -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/request_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_index_inv -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_inv -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_reg_inv -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_entry_in -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_entry_out -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_entry_out_inv -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_data_reg -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_be_reg -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_we_reg -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_we2 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_ram_din -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_ram_we -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_count -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_count_en -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_count_rdy -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/flush_count -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/flush_count_rst -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/flush_count_en -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/flush_count_rdy -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/request_count -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/request_count_en -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/request_count_rdy -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/invalidate_all -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/invalidate_ack -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/invalidate_en -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/invalidate_req -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/hit_cache_index -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_hit_we -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/instant_raw -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/req_tag -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/req_cache_index -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/req_word_index -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_tag -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_cache_index -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_word_index -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_tag -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_cache_index -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_word_index -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {9216870000 ps} 0} {{Cursor 100} {98503600 ps} 0} {{Cursor 3} {15592084279 ps} 0} -configure wave -namecolwidth 187 -configure wave -valuecolwidth 64 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {15591849308 ps} {15592330693 ps} diff --git a/projects/mips_sys/sim/tb_mips_sys_emac.fdo b/projects/mips_sys/sim/tb_mips_sys_emac.fdo deleted file mode 100644 index a55a471..0000000 --- a/projects/mips_sys/sim/tb_mips_sys_emac.fdo +++ /dev/null @@ -1,116 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -# Configs -vcom -explicit -93 "../src/sdram_config_sim.vhd" - -# Packages -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_types.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_instr.vhd" -vcom -explicit -93 "../../../lib/FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd" -vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd" - -# RAMs -vcom -explicit -93 "../../../lib/misc/dpram_2w2r.vhd" -vcom -explicit -93 "../../../lib/misc/dpram_1w1r.vhd" - -# FIFOS -vcom -explicit -93 "../../../lib/FIFO/src/gray_counter.vhd" -vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync_ctrl.vhd" -vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync.vhd" -vcom -explicit -93 "../../../lib/FIFO/src/fifo_async_ctrl.vhd" -vcom -explicit -93 "../../../lib/FIFO/src/fifo_async.vhd" - -# CPU -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_reg.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_alu.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_cop.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_dcache.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_icache.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_biu.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_top.vhd" -vcom -explicit -93 "../src/bootloader.ROM.vhd" -vcom -explicit -93 "../../../lib/misc/rom_wb.vhd" - -# VGA -vcom -explicit -93 "../../../lib/VGA_ctrl/src/fonts/char_rom_c64.vhd" -vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_types.vhd" -vcom -explicit -93 "../../../lib/VGA_ctrl/src/char_gen.vhd" -vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_sync.vhd" -vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_timing.vhd" -vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_backend.vhd" -vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_frontend64.vhd" - -# UART -vcom -explicit -93 "../../../lib/uart/bbfifo_16x8.vhd" -vcom -explicit -93 "../../../lib/uart/kcuart_rx.vhd" -vcom -explicit -93 "../../../lib/uart/kcuart_tx.vhd" -vcom -explicit -93 "../../../lib/uart/uart_rx.vhd" -vcom -explicit -93 "../../../lib/uart/uart_tx.vhd" -vcom -explicit -93 "../../../lib/uart/uart_wb.vhd" - -# PS2 -vcom -explicit -93 "../../../lib/ps2_port/src/debounce.vhd" -vcom -explicit -93 "../../../lib/ps2_port/src/ps2_core.vhd" -vcom -explicit -93 "../../../lib/ps2_port/src/ps2_phy_virtex.vhd" -vcom -explicit -93 "../../../lib/ps2_port/src/ps2_wb.vhd" - -# GPIO -vcom -explicit -93 "../../../lib/misc/gpio_wb.vhd" - -# LCD -vcom -explicit -93 "../../../lib/misc/lcd_port.vhd" - -# Flash and USB -vcom -explicit -93 "../../../lib/misc/async_types.vhd" -vcom -explicit -93 "../../../lib/misc/async_port_wb.vhd" -vcom -explicit -93 "../../../lib/misc/flash_port_wb.vhd" -vcom -explicit -93 "../src/async_defs_sim.vhd" - -# Sync SRAM -vcom -explicit -93 "../../../lib/SSRAM/src/package_utility.vhd" -vcom -explicit -93 "../../../lib/SSRAM/src/CY7C1354B.vhd" -vcom -explicit -93 "../../../lib/SSRAM/src/ssram_port_wb.vhd" - -# SDRAM -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" - -# AC-97 -vcom -explicit -93 "../../../lib/misc/singleshot.vhd" -vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_out.vhd" -vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_in.vhd" -vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_io.vhd" -vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac97_wb.vhd" - -# Ethernet MAC -vcom -explicit -93 "../../../lib/emac/src/emac_types.vhd" -vcom -explicit -93 "../../../lib/emac/src/piso.vhd" -vcom -explicit -93 "../../../lib/emac/src/sipo.vhd" -vcom -explicit -93 "../../../lib/emac/src/crc32.vhd" -vcom -explicit -93 "../../../lib/emac/src/emac_rx.vhd" -vcom -explicit -93 "../../../lib/emac/src/emac_tx.vhd" -vcom -explicit -93 "../../../lib/emac/src/emac_top_jb.vhd" - -# Clock Generator -vcom -explicit -93 "../src/clockgen_virtex4.vhd" - -# Top and TB -vcom -explicit -93 "../src/mips_sys_sim.vhd" -vcom -explicit -93 "../src/tb_mips_sys.vhd" - -vsim -t 1ps -lib work tb_mips_sys -do {tb_mips_sys_emac.wdo} -view wave -view structure -view signals -run 40 ms diff --git a/projects/mips_sys/sim/tb_mips_sys_emac.wdo b/projects/mips_sys/sim/tb_mips_sys_emac.wdo deleted file mode 100644 index 3a549c2..0000000 --- a/projects/mips_sys/sim/tb_mips_sys_emac.wdo +++ /dev/null @@ -1,185 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider UUT -add wave -noupdate -format Logic /tb_mips_sys/uut/rst_o -add wave -noupdate -format Logic /tb_mips_sys/uut/nmi -add wave -noupdate -format Logic /tb_mips_sys/uut/rst_in -add wave -noupdate -format Logic /tb_mips_sys/sys_rst_n_in -add wave -noupdate -format Logic /tb_mips_sys/sys_clk_in -add wave -noupdate -format Literal /tb_mips_sys/dip -add wave -noupdate -format Literal /tb_mips_sys/btn -add wave -noupdate -format Literal /tb_mips_sys/led -add wave -noupdate -format Logic /tb_mips_sys/sys_phy_rstn -add wave -noupdate -format Logic /tb_mips_sys/sys_phy_mdc -add wave -noupdate -format Logic /tb_mips_sys/sys_phy_mdio -add wave -noupdate -format Logic /tb_mips_sys/sys_phy_int -add wave -noupdate -format Logic /tb_mips_sys/sys_phy_rx_clk -add wave -noupdate -format Logic /tb_mips_sys/sys_phy_rx_dv -add wave -noupdate -format Logic /tb_mips_sys/sys_phy_rx_er -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_phy_rx -add wave -noupdate -format Logic /tb_mips_sys/sys_phy_tx_clk -add wave -noupdate -format Logic /tb_mips_sys/sys_phy_tx_en -add wave -noupdate -format Logic /tb_mips_sys/sys_phy_tx_er -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_phy_tx -add wave -noupdate -format Logic /tb_mips_sys/sys_phy_gtx_clk -add wave -noupdate -format Logic /tb_mips_sys/sys_phy_crs -add wave -noupdate -format Logic /tb_mips_sys/sys_phy_col -add wave -noupdate -format Logic /tb_mips_sys/sys_ps2_clk -add wave -noupdate -format Logic /tb_mips_sys/sys_ps2_data -add wave -noupdate -format Logic /tb_mips_sys/sys_rx -add wave -noupdate -format Logic /tb_mips_sys/sys_tx -add wave -noupdate -format Literal /tb_mips_sys/sys_lcd_d -add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_e -add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rs -add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rw -add wave -noupdate -format Logic /tb_mips_sys/refresh -add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_fb -add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_p -add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_n -add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cke_q -add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cs_qn -add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_ras_qn -add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cas_qn -add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_we_qn -add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dqs_q -add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_ba_q -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_a_q -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_data -add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dm_q -add wave -noupdate -format Literal /tb_mips_sys/sys_error -add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o -add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o -add wave -noupdate -format Logic /tb_mips_sys/uut/we_o -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o -add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o -add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i -add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i -add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o -add wave -noupdate -format Literal /tb_mips_sys/uut/mem_area -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_flash -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_usb -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_sdram -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_rom -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_gpio -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart0 -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart1 -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart2 -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_vga -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ssram -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ac97 -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ps2 -add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o -add wave -noupdate -divider {Clock Gen} -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/rst_in -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/clk_in -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_clk_out -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/vga_clk_out -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk_fb_in -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk0_out -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk270_out -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_clk0_out -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_clk270_out -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_rst_out -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_cnt -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_pipe0 -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_pipe1 -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/vga_fx_lock -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_fx_lock -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_lock -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_lock -add wave -noupdate -divider Arbiter -add wave -noupdate -format Literal /tb_mips_sys/uut/arb_idx -add wave -noupdate -format Literal /tb_mips_sys/uut/arb_req -add wave -noupdate -format Literal /tb_mips_sys/uut/arb_gnt -add wave -noupdate -divider {Ethernet MAC} -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/eth_tx_reg -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/clk_i -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/rst_i -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/int_o -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/cyc_i -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/stb_i -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_emac_jb/sel_i -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/we_i -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/ack_o -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/srdy_o -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/mrdy_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/addr_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/dat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/dat_o -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/rx_int_en -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/tx_int_en -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/irq_rx -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/irq_tx -add wave -noupdate -divider {EMAC TX} -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/inst_emac_tx/din_vld -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_tx/din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_tx/ctrl_in -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_tx/ctrl_out -add wave -noupdate -divider {EMAC RX} -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/inst_emac_rx/dout_vld -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_rx/dout -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_rx/ctrl_in -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_rx/ctrl_out -add wave -noupdate -divider {CPU Master} -add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o_cpu -add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o_cpu -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o_cpu -add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o_cpu -add wave -noupdate -format Logic /tb_mips_sys/uut/we_o_cpu -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_cpu -add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_cpu -add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_cpu -add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_cpu -add wave -noupdate -divider Flash -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ac97_rstn -add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/as -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/s -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_we_n -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_oe_n -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a -add wave -noupdate -format Logic /tb_mips_sys/sys_flash_ce -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_a -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_do -add wave -noupdate -format Logic /tb_mips_sys/uut/flash_oe_n -add wave -noupdate -format Logic /tb_mips_sys/uut/flash_we_n -add wave -noupdate -format Logic /tb_mips_sys/uut/flash_d_drv -add wave -noupdate -format Logic /tb_mips_sys/uut/flash_bsy -add wave -noupdate -divider {MIPS TOP} -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/dmem_addr -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/dmem_din -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/dmem_dout -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc -add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o -add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/hdu -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_run -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_reg_dual/reg_mem -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/id_stage -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/mem_stage -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/wb_stage -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {2312967085 ps} 0} {{Cursor 100} {4871595869 ps} 0} {{Cursor 3} {4495154370 ps} 0} {{Cursor 7} {6077658830 ps} 0} -configure wave -namecolwidth 187 -configure wave -valuecolwidth 64 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {41227735500 ps} diff --git a/projects/mips_sys/src/.directory_history b/projects/mips_sys/src/.directory_history deleted file mode 100644 index 2f56f3d..0000000 --- a/projects/mips_sys/src/.directory_history +++ /dev/null @@ -1,4 +0,0 @@ -VHDL/projects/mips_sys/src/async_defs.vhd - -VHDL/projects/mips_sys/src/sys_types.vhd -VHDL/projects/mips_sys/src/async_defs.vhd diff --git a/projects/mips_sys/src/async_defs_sim.vhd b/projects/mips_sys/src/async_defs_sim.vhd deleted file mode 100644 index 8f58939..0000000 --- a/projects/mips_sys/src/async_defs_sim.vhd +++ /dev/null @@ -1,70 +0,0 @@ -------------------------------------------------------------------------- --- Project: MIPS System controller --- This file: --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -use work.async_types.all; - -package async_defs is - - constant ts_flash : async_timespec_t := - ( - T_leadin => 10.0, - T_pulse_rd => 120.0, - T_pulse_wr => 70.0, - T_leadout => 10.0, - T_release => 40.0, - T_pulse_rst => 80.0, - T_pulse_page_rd => 30.0, - can_page_rd => true, - nbits_page_rd => 4, - pol_cs => '1', - pol_oe => '0', - pol_we => '0', - pol_be => '0', - pol_rst => '0' - ); - - constant ts_usb : async_timespec_t := - ( - T_leadin => 10.0, - T_pulse_rd => 60.0, - T_pulse_wr => 60.0, - T_leadout => 10.0, - T_release => 80.0, - T_pulse_rst => 80.0, - T_pulse_page_rd => 00.0, - can_page_rd => false, - nbits_page_rd => 0, - pol_cs => '0', - pol_oe => '0', - pol_we => '0', - pol_be => '0', - pol_rst => '0' - ); - - ---------------------------------------------------------------------------------------------- - -end async_defs; diff --git a/projects/mips_sys/src/bootloader.ROM.vhd b/projects/mips_sys/src/bootloader.ROM.vhd deleted file mode 100644 index 1e0f12d..0000000 --- a/projects/mips_sys/src/bootloader.ROM.vhd +++ /dev/null @@ -1,2082 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -ENTITY rom IS - Port - ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); -END rom; - -ARCHITECTURE data OF rom IS - - subtype word_t is unsigned(31 downto 0); - type word_array_t is array (0 to 2047) of word_t; - constant word_array : word_array_t := - ( - - X"3C1D8000", -- 00000000 - X"27BDEFF0", -- 00000004 - X"3C1A1040", -- 00000008 - X"375A000C", -- 0000000C - X"409A6000", -- 00000010 - X"241A0000", -- 00000014 - X"409A6800", -- 00000018 - X"401A7800", -- 0000001C - X"00000000", -- 00000020 - X"409AF800", -- 00000024 - X"42000020", -- 00000028 - X"42000022", -- 0000002C - X"3C1ABFC0", -- 00000030 - X"275A005C", -- 00000034 - X"0340F809", -- 00000038 - X"00000000", -- 0000003C - X"3C1ABFC0", -- 00000040 - X"275A114C", -- 00000044 - X"0340F809", -- 00000048 - X"00000000", -- 0000004C - X"00000000", -- 00000050 - X"0BF00014", -- 00000054 - X"00000000", -- 00000058 - X"3C1AA001", -- 0000005C - X"275A0008", -- 00000060 - X"241B000D", -- 00000064 - X"AF5B0000", -- 00000068 - X"03E00008", -- 0000006C - X"00000000", -- 00000070 - X"00000000", -- 00000074 - X"00000000", -- 00000078 - X"00000000", -- 0000007C - X"00000000", -- 00000080 - X"00000000", -- 00000084 - X"00000000", -- 00000088 - X"00000000", -- 0000008C - X"00000000", -- 00000090 - X"00000000", -- 00000094 - X"00000000", -- 00000098 - X"00000000", -- 0000009C - X"00000000", -- 000000A0 - X"00000000", -- 000000A4 - X"00000000", -- 000000A8 - X"00000000", -- 000000AC - X"00000000", -- 000000B0 - X"00000000", -- 000000B4 - X"00000000", -- 000000B8 - X"00000000", -- 000000BC - X"00000000", -- 000000C0 - X"00000000", -- 000000C4 - X"00000000", -- 000000C8 - X"00000000", -- 000000CC - X"00000000", -- 000000D0 - X"00000000", -- 000000D4 - X"00000000", -- 000000D8 - X"00000000", -- 000000DC - X"00000000", -- 000000E0 - X"00000000", -- 000000E4 - X"00000000", -- 000000E8 - X"00000000", -- 000000EC - X"00000000", -- 000000F0 - X"00000000", -- 000000F4 - X"00000000", -- 000000F8 - X"00000000", -- 000000FC - X"00000000", -- 00000100 - X"00000000", -- 00000104 - X"00000000", -- 00000108 - X"00000000", -- 0000010C - X"00000000", -- 00000110 - X"00000000", -- 00000114 - X"00000000", -- 00000118 - X"00000000", -- 0000011C - X"00000000", -- 00000120 - X"00000000", -- 00000124 - X"00000000", -- 00000128 - X"00000000", -- 0000012C - X"00000000", -- 00000130 - X"00000000", -- 00000134 - X"00000000", -- 00000138 - X"00000000", -- 0000013C - X"00000000", -- 00000140 - X"00000000", -- 00000144 - X"00000000", -- 00000148 - X"00000000", -- 0000014C - X"00000000", -- 00000150 - X"00000000", -- 00000154 - X"00000000", -- 00000158 - X"00000000", -- 0000015C - X"00000000", -- 00000160 - X"00000000", -- 00000164 - X"00000000", -- 00000168 - X"00000000", -- 0000016C - X"00000000", -- 00000170 - X"00000000", -- 00000174 - X"00000000", -- 00000178 - X"00000000", -- 0000017C - X"401A6800", -- 00000180 - X"3C1BC000", -- 00000184 - X"001AD082", -- 00000188 - X"335A000F", -- 0000018C - X"035BD025", -- 00000190 - X"3C1BA000", -- 00000194 - X"277B0000", -- 00000198 - X"AF7A0000", -- 0000019C - X"401A6800", -- 000001A0 - X"00000000", -- 000001A4 - X"001AD202", -- 000001A8 - X"335A00FF", -- 000001AC - X"1740FFFB", -- 000001B0 - X"00000000", -- 000001B4 - X"401A7000", -- 000001B8 - X"00000000", -- 000001BC - X"03400008", -- 000001C0 - X"42000010", -- 000001C4 - X"40026000", -- 000001C8 - X"03E00008", -- 000001CC - X"00000000", -- 000001D0 - X"40846000", -- 000001D4 - X"03E00008", -- 000001D8 - X"00000000", -- 000001DC - X"40026800", -- 000001E0 - X"03E00008", -- 000001E4 - X"00000000", -- 000001E8 - X"40846800", -- 000001EC - X"03E00008", -- 000001F0 - X"00000000", -- 000001F4 - X"40027800", -- 000001F8 - X"03E00008", -- 000001FC - X"00000000", -- 00000200 - X"3C02A001", -- 00000204 - X"34430004", -- 00000208 - X"8C620000", -- 0000020C - X"00000000", -- 00000210 - X"30420010", -- 00000214 - X"1040FFFC", -- 00000218 - X"3C02A001", -- 0000021C - X"8C420000", -- 00000220 - X"00000000", -- 00000224 - X"00021600", -- 00000228 - X"03E00008", -- 0000022C - X"00021603", -- 00000230 - X"00042600", -- 00000234 - X"3C02A001", -- 00000238 - X"00042603", -- 0000023C - X"34430004", -- 00000240 - X"8C620000", -- 00000244 - X"00000000", -- 00000248 - X"30420002", -- 0000024C - X"1440FFFC", -- 00000250 - X"3C02A001", -- 00000254 - X"AC440000", -- 00000258 - X"03E00008", -- 0000025C - X"00000000", -- 00000260 - X"00042600", -- 00000264 - X"00042603", -- 00000268 - X"2402000A", -- 0000026C - X"1482000A", -- 00000270 - X"3C02A001", -- 00000274 - X"34430004", -- 00000278 - X"8C620000", -- 0000027C - X"00000000", -- 00000280 - X"30420002", -- 00000284 - X"1440FFFC", -- 00000288 - X"3C02A001", -- 0000028C - X"2403000D", -- 00000290 - X"AC430000", -- 00000294 - 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X"00000000", -- 00001CB8 - X"00000000", -- 00001CBC - X"00000000", -- 00001CC0 - X"00000000", -- 00001CC4 - X"00000000", -- 00001CC8 - X"00000000", -- 00001CCC - X"00000000", -- 00001CD0 - X"00000000", -- 00001CD4 - X"00000000", -- 00001CD8 - X"00000000", -- 00001CDC - X"00000000", -- 00001CE0 - X"00000000", -- 00001CE4 - X"00000000", -- 00001CE8 - X"00000000", -- 00001CEC - X"00000000", -- 00001CF0 - X"00000000", -- 00001CF4 - X"00000000", -- 00001CF8 - X"00000000", -- 00001CFC - X"00000000", -- 00001D00 - X"00000000", -- 00001D04 - X"00000000", -- 00001D08 - X"00000000", -- 00001D0C - X"00000000", -- 00001D10 - X"00000000", -- 00001D14 - X"00000000", -- 00001D18 - X"00000000", -- 00001D1C - X"00000000", -- 00001D20 - X"00000000", -- 00001D24 - X"00000000", -- 00001D28 - X"00000000", -- 00001D2C - X"00000000", -- 00001D30 - X"00000000", -- 00001D34 - X"00000000", -- 00001D38 - X"00000000", -- 00001D3C - X"00000000", -- 00001D40 - X"00000000", -- 00001D44 - X"00000000", -- 00001D48 - X"00000000", -- 00001D4C - X"00000000", -- 00001D50 - X"00000000", -- 00001D54 - X"00000000", -- 00001D58 - X"00000000", -- 00001D5C - X"00000000", -- 00001D60 - X"00000000", -- 00001D64 - X"00000000", -- 00001D68 - X"00000000", -- 00001D6C - X"00000000", -- 00001D70 - X"00000000", -- 00001D74 - X"00000000", -- 00001D78 - X"00000000", -- 00001D7C - X"00000000", -- 00001D80 - X"00000000", -- 00001D84 - X"00000000", -- 00001D88 - X"00000000", -- 00001D8C - X"00000000", -- 00001D90 - X"00000000", -- 00001D94 - X"00000000", -- 00001D98 - X"00000000", -- 00001D9C - X"00000000", -- 00001DA0 - X"00000000", -- 00001DA4 - X"00000000", -- 00001DA8 - X"00000000", -- 00001DAC - X"00000000", -- 00001DB0 - X"00000000", -- 00001DB4 - X"00000000", -- 00001DB8 - X"00000000", -- 00001DBC - X"00000000", -- 00001DC0 - X"00000000", -- 00001DC4 - X"00000000", -- 00001DC8 - X"00000000", -- 00001DCC - X"00000000", -- 00001DD0 - X"00000000", -- 00001DD4 - X"00000000", -- 00001DD8 - X"00000000", -- 00001DDC - X"00000000", -- 00001DE0 - X"00000000", -- 00001DE4 - X"00000000", -- 00001DE8 - X"00000000", -- 00001DEC - X"00000000", -- 00001DF0 - X"00000000", -- 00001DF4 - X"00000000", -- 00001DF8 - X"00000000", -- 00001DFC - X"00000000", -- 00001E00 - X"00000000", -- 00001E04 - X"00000000", -- 00001E08 - X"00000000", -- 00001E0C - X"00000000", -- 00001E10 - X"00000000", -- 00001E14 - X"00000000", -- 00001E18 - X"00000000", -- 00001E1C - X"00000000", -- 00001E20 - X"00000000", -- 00001E24 - X"00000000", -- 00001E28 - X"00000000", -- 00001E2C - X"00000000", -- 00001E30 - X"00000000", -- 00001E34 - X"00000000", -- 00001E38 - X"00000000", -- 00001E3C - X"00000000", -- 00001E40 - X"00000000", -- 00001E44 - X"00000000", -- 00001E48 - X"00000000", -- 00001E4C - X"00000000", -- 00001E50 - X"00000000", -- 00001E54 - X"00000000", -- 00001E58 - X"00000000", -- 00001E5C - X"00000000", -- 00001E60 - X"00000000", -- 00001E64 - X"00000000", -- 00001E68 - X"00000000", -- 00001E6C - X"00000000", -- 00001E70 - X"00000000", -- 00001E74 - X"00000000", -- 00001E78 - X"00000000", -- 00001E7C - X"00000000", -- 00001E80 - X"00000000", -- 00001E84 - X"00000000", -- 00001E88 - X"00000000", -- 00001E8C - X"00000000", -- 00001E90 - X"00000000", -- 00001E94 - X"00000000", -- 00001E98 - X"00000000", -- 00001E9C - X"00000000", -- 00001EA0 - X"00000000", -- 00001EA4 - X"00000000", -- 00001EA8 - X"00000000", -- 00001EAC - X"00000000", -- 00001EB0 - X"00000000", -- 00001EB4 - X"00000000", -- 00001EB8 - X"00000000", -- 00001EBC - X"00000000", -- 00001EC0 - X"00000000", -- 00001EC4 - X"00000000", -- 00001EC8 - X"00000000", -- 00001ECC - X"00000000", -- 00001ED0 - X"00000000", -- 00001ED4 - X"00000000", -- 00001ED8 - X"00000000", -- 00001EDC - X"00000000", -- 00001EE0 - X"00000000", -- 00001EE4 - X"00000000", -- 00001EE8 - X"00000000", -- 00001EEC - X"00000000", -- 00001EF0 - X"00000000", -- 00001EF4 - X"00000000", -- 00001EF8 - X"00000000", -- 00001EFC - X"00000000", -- 00001F00 - X"00000000", -- 00001F04 - X"00000000", -- 00001F08 - X"00000000", -- 00001F0C - X"00000000", -- 00001F10 - X"00000000", -- 00001F14 - X"00000000", -- 00001F18 - X"00000000", -- 00001F1C - X"00000000", -- 00001F20 - X"00000000", -- 00001F24 - X"00000000", -- 00001F28 - X"00000000", -- 00001F2C - X"00000000", -- 00001F30 - X"00000000", -- 00001F34 - X"00000000", -- 00001F38 - X"00000000", -- 00001F3C - X"00000000", -- 00001F40 - X"00000000", -- 00001F44 - X"00000000", -- 00001F48 - X"00000000", -- 00001F4C - X"00000000", -- 00001F50 - X"00000000", -- 00001F54 - X"00000000", -- 00001F58 - X"00000000", -- 00001F5C - X"00000000", -- 00001F60 - X"00000000", -- 00001F64 - X"00000000", -- 00001F68 - X"00000000", -- 00001F6C - X"00000000", -- 00001F70 - X"00000000", -- 00001F74 - X"00000000", -- 00001F78 - X"00000000", -- 00001F7C - X"00000000", -- 00001F80 - X"00000000", -- 00001F84 - X"00000000", -- 00001F88 - X"00000000", -- 00001F8C - X"00000000", -- 00001F90 - X"00000000", -- 00001F94 - X"00000000", -- 00001F98 - X"00000000", -- 00001F9C - X"00000000", -- 00001FA0 - X"00000000", -- 00001FA4 - X"00000000", -- 00001FA8 - X"00000000", -- 00001FAC - X"00000000", -- 00001FB0 - X"00000000", -- 00001FB4 - X"00000000", -- 00001FB8 - X"00000000", -- 00001FBC - X"00000000", -- 00001FC0 - X"00000000", -- 00001FC4 - X"00000000", -- 00001FC8 - X"00000000", -- 00001FCC - X"00000000", -- 00001FD0 - X"00000000", -- 00001FD4 - X"00000000", -- 00001FD8 - X"00000000", -- 00001FDC - X"00000000", -- 00001FE0 - X"00000000", -- 00001FE4 - X"00000000", -- 00001FE8 - X"00000000", -- 00001FEC - X"00000000", -- 00001FF0 - X"00000000", -- 00001FF4 - X"00000000", -- 00001FF8 - X"00000000" -- 00001FFC - ); - -begin - -PROM_READ: - process(clk) - begin - if rising_edge(clk) and ce = '1' then - dout <= word_array(to_integer(addr(12 downto 2))); - end if; - end process; - -end data; diff --git a/projects/mips_sys/src/bootloader.ROM_ld.vhd b/projects/mips_sys/src/bootloader.ROM_ld.vhd deleted file mode 100644 index 2785865..0000000 --- a/projects/mips_sys/src/bootloader.ROM_ld.vhd +++ /dev/null @@ -1,2174 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -ENTITY rom IS - Port - ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); -END rom; - -ARCHITECTURE data OF rom IS - - subtype word_t is unsigned(31 downto 0); - type word_array_t is array (0 to 2047) of word_t; - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : unsigned (15 downto 0); - signal jtag_ld_dout : unsigned (31 downto 0); - signal jtag_ld_din : unsigned (31 downto 0); - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (47 downto 0); - - signal word_array : word_array_t := - ( - - X"3C1D8000", -- 00000000 - X"27BDEFF0", -- 00000004 - X"3C1A1040", -- 00000008 - X"375A000C", -- 0000000C - X"409A6000", -- 00000010 - X"241A0000", -- 00000014 - X"409A6800", -- 00000018 - X"401A7800", -- 0000001C - X"00000000", -- 00000020 - X"409AF800", -- 00000024 - X"42000020", -- 00000028 - X"42000022", -- 0000002C - X"3C1ABFC0", -- 00000030 - X"275A005C", -- 00000034 - X"0340F809", -- 00000038 - X"00000000", -- 0000003C - X"3C1ABFC0", -- 00000040 - X"275A114C", -- 00000044 - X"0340F809", -- 00000048 - X"00000000", -- 0000004C - X"00000000", -- 00000050 - X"0BF00014", -- 00000054 - X"00000000", -- 00000058 - X"3C1AA001", -- 0000005C - X"275A0008", -- 00000060 - X"241B000D", -- 00000064 - X"AF5B0000", -- 00000068 - X"03E00008", -- 0000006C - X"00000000", -- 00000070 - X"00000000", -- 00000074 - X"00000000", -- 00000078 - X"00000000", -- 0000007C - X"00000000", -- 00000080 - X"00000000", -- 00000084 - X"00000000", -- 00000088 - X"00000000", -- 0000008C - X"00000000", -- 00000090 - X"00000000", -- 00000094 - X"00000000", -- 00000098 - X"00000000", -- 0000009C - X"00000000", -- 000000A0 - X"00000000", -- 000000A4 - X"00000000", -- 000000A8 - X"00000000", -- 000000AC - X"00000000", -- 000000B0 - X"00000000", -- 000000B4 - X"00000000", -- 000000B8 - X"00000000", -- 000000BC - X"00000000", -- 000000C0 - X"00000000", -- 000000C4 - X"00000000", -- 000000C8 - X"00000000", -- 000000CC - X"00000000", -- 000000D0 - X"00000000", -- 000000D4 - X"00000000", -- 000000D8 - X"00000000", -- 000000DC - X"00000000", -- 000000E0 - X"00000000", -- 000000E4 - X"00000000", -- 000000E8 - X"00000000", -- 000000EC - X"00000000", -- 000000F0 - X"00000000", -- 000000F4 - X"00000000", -- 000000F8 - X"00000000", -- 000000FC - X"00000000", -- 00000100 - X"00000000", -- 00000104 - X"00000000", -- 00000108 - X"00000000", -- 0000010C - X"00000000", -- 00000110 - X"00000000", -- 00000114 - X"00000000", -- 00000118 - X"00000000", -- 0000011C - X"00000000", -- 00000120 - X"00000000", -- 00000124 - X"00000000", -- 00000128 - X"00000000", -- 0000012C - X"00000000", -- 00000130 - X"00000000", -- 00000134 - X"00000000", -- 00000138 - X"00000000", -- 0000013C - X"00000000", -- 00000140 - X"00000000", -- 00000144 - X"00000000", -- 00000148 - X"00000000", -- 0000014C - X"00000000", -- 00000150 - X"00000000", -- 00000154 - X"00000000", -- 00000158 - X"00000000", -- 0000015C - X"00000000", -- 00000160 - X"00000000", -- 00000164 - X"00000000", -- 00000168 - X"00000000", -- 0000016C - X"00000000", -- 00000170 - X"00000000", -- 00000174 - X"00000000", -- 00000178 - X"00000000", -- 0000017C - X"401A6800", -- 00000180 - X"3C1BC000", -- 00000184 - X"001AD082", -- 00000188 - X"335A000F", -- 0000018C - X"035BD025", -- 00000190 - X"3C1BA000", -- 00000194 - X"277B0000", -- 00000198 - X"AF7A0000", -- 0000019C - X"401A6800", -- 000001A0 - X"00000000", -- 000001A4 - X"001AD202", -- 000001A8 - X"335A00FF", -- 000001AC - X"1740FFFB", -- 000001B0 - X"00000000", -- 000001B4 - X"401A7000", -- 000001B8 - X"00000000", -- 000001BC - X"03400008", -- 000001C0 - X"42000010", -- 000001C4 - X"40026000", -- 000001C8 - X"03E00008", -- 000001CC - X"00000000", -- 000001D0 - X"40846000", -- 000001D4 - X"03E00008", -- 000001D8 - X"00000000", -- 000001DC - X"40026800", -- 000001E0 - X"03E00008", -- 000001E4 - X"00000000", -- 000001E8 - X"40846800", -- 000001EC - X"03E00008", -- 000001F0 - X"00000000", -- 000001F4 - X"40027800", -- 000001F8 - X"03E00008", -- 000001FC - X"00000000", -- 00000200 - X"3C02A001", -- 00000204 - X"34430004", -- 00000208 - X"8C620000", -- 0000020C - X"00000000", -- 00000210 - X"30420010", -- 00000214 - X"1040FFFC", -- 00000218 - X"3C02A001", -- 0000021C - X"8C420000", -- 00000220 - X"00000000", -- 00000224 - X"00021600", -- 00000228 - X"03E00008", -- 0000022C - X"00021603", -- 00000230 - X"00042600", -- 00000234 - X"3C02A001", -- 00000238 - X"00042603", -- 0000023C - X"34430004", -- 00000240 - X"8C620000", -- 00000244 - X"00000000", -- 00000248 - X"30420002", -- 0000024C - X"1440FFFC", -- 00000250 - X"3C02A001", -- 00000254 - X"AC440000", -- 00000258 - X"03E00008", -- 0000025C - X"00000000", -- 00000260 - X"00042600", -- 00000264 - X"00042603", -- 00000268 - X"2402000A", -- 0000026C - X"1482000A", -- 00000270 - X"3C02A001", -- 00000274 - X"34430004", -- 00000278 - X"8C620000", -- 0000027C - X"00000000", -- 00000280 - X"30420002", -- 00000284 - X"1440FFFC", -- 00000288 - X"3C02A001", -- 0000028C - X"2403000D", -- 00000290 - X"AC430000", -- 00000294 - X"3C02A001", -- 00000298 - X"34430004", -- 0000029C - X"8C620000", -- 000002A0 - X"00000000", -- 000002A4 - X"30420002", -- 000002A8 - X"1440FFFC", -- 000002AC - X"3C02A001", -- 000002B0 - X"AC440000", -- 000002B4 - X"03E00008", -- 000002B8 - X"00000000", -- 000002BC - X"3C02A001", -- 000002C0 - X"34470004", -- 000002C4 - X"00802821", -- 000002C8 - X"2409000A", -- 000002CC - X"3C06A001", -- 000002D0 - X"0BF000C6", -- 000002D4 - X"2408000D", -- 000002D8 - X"14690007", -- 000002DC - X"00000000", -- 000002E0 - X"8CE20000", -- 000002E4 - X"00000000", -- 000002E8 - X"30420002", -- 000002EC - X"1440FFFC", -- 000002F0 - X"00000000", -- 000002F4 - X"ACC80000", -- 000002F8 - X"8CE20000", -- 000002FC - X"00000000", -- 00000300 - X"30420002", -- 00000304 - X"1440FFFC", -- 00000308 - X"00000000", -- 0000030C - X"ACC30000", -- 00000310 - X"24A50001", -- 00000314 - X"80A30000", -- 00000318 - X"00000000", -- 0000031C - X"1460FFEE", -- 00000320 - X"00A41023", -- 00000324 - X"03E00008", -- 00000328 - X"00000000", -- 0000032C - X"00042600", -- 00000330 - X"3C02A001", -- 00000334 - X"00042603", -- 00000338 - X"344A0004", -- 0000033C - X"00003821", -- 00000340 - X"3C09A001", -- 00000344 - X"24080002", -- 00000348 - X"308200FF", -- 0000034C - X"00022902", -- 00000350 - X"00041100", -- 00000354 - X"00022600", -- 00000358 - X"2CA3000A", -- 0000035C - X"00042603", -- 00000360 - X"14600002", -- 00000364 - X"24A60030", -- 00000368 - X"24A60037", -- 0000036C - X"8D420000", -- 00000370 - X"00000000", -- 00000374 - X"30420002", -- 00000378 - X"1440FFFC", -- 0000037C - X"00061600", -- 00000380 - X"00021603", -- 00000384 - X"24E70001", -- 00000388 - X"AD220000", -- 0000038C - X"14E8FFEF", -- 00000390 - X"308200FF", -- 00000394 - X"03E00008", -- 00000398 - X"00000000", -- 0000039C - X"27BDFFE0", -- 000003A0 - X"AFB20018", -- 000003A4 - X"AFB10014", -- 000003A8 - X"AFB00010", -- 000003AC - X"AFBF001C", -- 000003B0 - X"00808821", -- 000003B4 - X"00008021", -- 000003B8 - X"24120004", -- 000003BC - X"00112603", -- 000003C0 - X"0FF000CC", -- 000003C4 - X"26100001", -- 000003C8 - X"1612FFFC", -- 000003CC - X"00118A00", -- 000003D0 - X"8FBF001C", -- 000003D4 - X"8FB20018", -- 000003D8 - X"8FB10014", -- 000003DC - X"8FB00010", -- 000003E0 - X"03E00008", -- 000003E4 - X"27BD0020", -- 000003E8 - X"27BDFFC8", -- 000003EC - X"AFB60028", -- 000003F0 - X"AFBF0034", -- 000003F4 - X"AFBE0030", -- 000003F8 - X"AFB7002C", -- 000003FC - X"AFB50024", -- 00000400 - X"AFB40020", -- 00000404 - X"AFB3001C", -- 00000408 - X"AFB20018", -- 0000040C - X"AFB10014", -- 00000410 - X"AFB00010", -- 00000414 - X"00801021", -- 00000418 - X"10A00002", -- 0000041C - X"00C0B021", -- 00000420 - X"00002021", -- 00000424 - X"00409821", -- 00000428 - X"3C02A001", -- 0000042C - X"00E09021", -- 00000430 - X"0080A821", -- 00000434 - X"345E0004", -- 00000438 - X"00E0A021", -- 0000043C - X"3C17A001", -- 00000440 - X"0FF000E8", -- 00000444 - X"02A02021", -- 00000448 - X"3C04BFC0", -- 0000044C - X"0FF000B0", -- 00000450 - X"24841698", -- 00000454 - X"02608821", -- 00000458 - X"0BF00128", -- 0000045C - X"00008021", -- 00000460 - X"12400009", -- 00000464 - X"00000000", -- 00000468 - X"82240000", -- 0000046C - X"0FF000CC", -- 00000470 - X"2652FFFF", -- 00000474 - X"3C04BFC0", -- 00000478 - X"0FF000B0", -- 0000047C - X"24841770", -- 00000480 - X"0BF00128", -- 00000484 - X"26310001", -- 00000488 - X"3C04BFC0", -- 0000048C - X"0FF000B0", -- 00000490 - X"2484169C", -- 00000494 - X"0BF0012C", -- 00000498 - X"3C04BFC0", -- 0000049C - X"0216102A", -- 000004A0 - X"1440FFEF", -- 000004A4 - X"26100001", -- 000004A8 - X"3C04BFC0", -- 000004AC - X"0FF000B0", -- 000004B0 - X"2484169C", -- 000004B4 - X"02602821", -- 000004B8 - X"0BF00155", -- 000004BC - X"00002021", -- 000004C0 - X"1280001E", -- 000004C4 - X"00000000", -- 000004C8 - X"90A30000", -- 000004CC - X"00000000", -- 000004D0 - X"2462FFE0", -- 000004D4 - X"304200FF", -- 000004D8 - X"2C420060", -- 000004DC - X"14400003", -- 000004E0 - X"00031E00", -- 000004E4 - X"2403002E", -- 000004E8 - X"00031E00", -- 000004EC - X"00031E03", -- 000004F0 - X"2402000A", -- 000004F4 - X"14620007", -- 000004F8 - X"00000000", -- 000004FC - X"8FC20000", -- 00000500 - X"00000000", -- 00000504 - X"30420002", -- 00000508 - X"1440FFFC", -- 0000050C - X"2402000D", -- 00000510 - X"AEE20000", -- 00000514 - X"8FC20000", -- 00000518 - X"00000000", -- 0000051C - X"30420002", -- 00000520 - X"1440FFFC", -- 00000524 - X"00000000", -- 00000528 - X"AEE30000", -- 0000052C - X"2694FFFF", -- 00000530 - X"24840001", -- 00000534 - X"0BF00155", -- 00000538 - X"24A50001", -- 0000053C - X"3C04BFC0", -- 00000540 - X"0FF000B0", -- 00000544 - X"24841770", -- 00000548 - X"0BF00159", -- 0000054C - X"3C04BFC0", -- 00000550 - X"0096102A", -- 00000554 - X"1440FFDA", -- 00000558 - X"00000000", -- 0000055C - X"3C04BFC0", -- 00000560 - X"0FF000B0", -- 00000564 - X"248416C4", -- 00000568 - X"02B6A821", -- 0000056C - X"1640FFB4", -- 00000570 - X"02769821", -- 00000574 - X"8FBF0034", -- 00000578 - X"8FBE0030", -- 0000057C - X"8FB7002C", -- 00000580 - X"8FB60028", -- 00000584 - X"8FB50024", -- 00000588 - X"8FB40020", -- 0000058C - X"8FB3001C", -- 00000590 - X"8FB20018", -- 00000594 - X"8FB10014", -- 00000598 - X"8FB00010", -- 0000059C - X"03E00008", -- 000005A0 - X"27BD0038", -- 000005A4 - X"00C03821", -- 000005A8 - X"00A03021", -- 000005AC - X"0BF000FB", -- 000005B0 - X"24050001", -- 000005B4 - X"8C840000", -- 000005B8 - X"3C020070", -- 000005BC - X"34420070", -- 000005C0 - X"3C0300FF", -- 000005C4 - X"AC820000", -- 000005C8 - X"346300FF", -- 000005CC - X"8C820000", -- 000005D0 - X"AC830000", -- 000005D4 - X"03E00008", -- 000005D8 - X"00000000", -- 000005DC - X"27BDFFF8", -- 000005E0 - X"AC850000", -- 000005E4 - X"24820008", -- 000005E8 - X"0BF0017F", -- 000005EC - X"24830020", -- 000005F0 - X"A0400000", -- 000005F4 - X"24420001", -- 000005F8 - X"1443FFFD", -- 000005FC - X"00000000", -- 00000600 - X"24020001", -- 00000604 - X"AC820004", -- 00000608 - X"03E00008", -- 0000060C - X"27BD0008", -- 00000610 - X"8C870000", -- 00000614 - X"3C020098", -- 00000618 - X"34420098", -- 0000061C - X"ACE20000", -- 00000620 - X"3C0200FF", -- 00000624 - X"344200FF", -- 00000628 - X"ACE20000", -- 0000062C - X"3C020090", -- 00000630 - X"34420090", -- 00000634 - X"ACE20000", -- 00000638 - X"00804021", -- 0000063C - X"94E4009C", -- 00000640 - X"24030002", -- 00000644 - X"24020020", -- 00000648 - X"AD030008", -- 0000064C - X"AD03001C", -- 00000650 - X"AD020018", -- 00000654 - X"3084FFFF", -- 00000658 - X"0BF0019D", -- 0000065C - X"00001821", -- 00000660 - X"8D020008", -- 00000664 - X"00000000", -- 00000668 - X"00021040", -- 0000066C - X"AD020008", -- 00000670 - X"0064102B", -- 00000674 - X"1440FFFA", -- 00000678 - X"24630001", -- 0000067C - X"94E200AC", -- 00000680 - X"94E300A8", -- 00000684 - X"3042FFFF", -- 00000688 - X"8D04001C", -- 0000068C - X"3063FFFF", -- 00000690 - X"00021200", -- 00000694 - X"00432825", -- 00000698 - X"AD040014", -- 0000069C - X"0BF001AE", -- 000006A0 - X"00001821", -- 000006A4 - X"8D020014", -- 000006A8 - X"00000000", -- 000006AC - X"00021040", -- 000006B0 - X"AD020014", -- 000006B4 - X"0065102B", -- 000006B8 - X"1440FFFA", -- 000006BC - X"24630001", -- 000006C0 - X"94E300B8", -- 000006C4 - X"94E600B4", -- 000006C8 - X"94E200C0", -- 000006CC - X"94E400BC", -- 000006D0 - X"8D05001C", -- 000006D4 - X"3042FFFF", -- 000006D8 - X"3084FFFF", -- 000006DC - X"00021200", -- 000006E0 - X"00441025", -- 000006E4 - X"00052A00", -- 000006E8 - X"00A20018", -- 000006EC - X"3063FFFF", -- 000006F0 - X"30C6FFFF", -- 000006F4 - X"00031A00", -- 000006F8 - X"00661825", -- 000006FC - X"24630001", -- 00000700 - X"AD030010", -- 00000704 - X"3C0300FF", -- 00000708 - X"346300FF", -- 0000070C - X"00001021", -- 00000710 - X"00002812", -- 00000714 - X"AD05000C", -- 00000718 - X"ACE30000", -- 0000071C - X"03E00008", -- 00000720 - X"00000000", -- 00000724 - X"8C820008", -- 00000728 - X"8C860000", -- 0000072C - X"00021082", -- 00000730 - X"00A2102B", -- 00000734 - X"14400004", -- 00000738 - X"3C030090", -- 0000073C - X"3C028010", -- 00000740 - X"03E00008", -- 00000744 - X"34420002", -- 00000748 - X"8C820010", -- 0000074C - X"00000000", -- 00000750 - X"2442FFFF", -- 00000754 - X"00021400", -- 00000758 - X"00A21024", -- 0000075C - X"24420002", -- 00000760 - X"34630090", -- 00000764 - X"00021080", -- 00000768 - X"ACC30000", -- 0000076C - X"00C21021", -- 00000770 - X"8C430000", -- 00000774 - X"3C020001", -- 00000778 - X"34420001", -- 0000077C - X"00621824", -- 00000780 - X"3C0200FF", -- 00000784 - X"344200FF", -- 00000788 - X"ACC20000", -- 0000078C - X"03E00008", -- 00000790 - X"0003102B", -- 00000794 - X"8C820008", -- 00000798 - X"00A01821", -- 0000079C - X"00021082", -- 000007A0 - X"00A2102B", -- 000007A4 - X"8C850000", -- 000007A8 - X"14400003", -- 000007AC - X"3C028010", -- 000007B0 - X"0BF0020C", -- 000007B4 - X"34430002", -- 000007B8 - X"8C820010", -- 000007BC - X"00000000", -- 000007C0 - X"2442FFFF", -- 000007C4 - X"00021400", -- 000007C8 - X"00621024", -- 000007CC - X"00021080", -- 000007D0 - X"00A22021", -- 000007D4 - X"3C020020", -- 000007D8 - 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X"00000000", -- 00001C0C - X"00000000", -- 00001C10 - X"00000000", -- 00001C14 - X"00000000", -- 00001C18 - X"00000000", -- 00001C1C - X"00000000", -- 00001C20 - X"00000000", -- 00001C24 - X"00000000", -- 00001C28 - X"00000000", -- 00001C2C - X"00000000", -- 00001C30 - X"00000000", -- 00001C34 - X"00000000", -- 00001C38 - X"00000000", -- 00001C3C - X"00000000", -- 00001C40 - X"00000000", -- 00001C44 - X"00000000", -- 00001C48 - X"00000000", -- 00001C4C - X"00000000", -- 00001C50 - X"00000000", -- 00001C54 - X"00000000", -- 00001C58 - X"00000000", -- 00001C5C - X"00000000", -- 00001C60 - X"00000000", -- 00001C64 - X"00000000", -- 00001C68 - X"00000000", -- 00001C6C - X"00000000", -- 00001C70 - X"00000000", -- 00001C74 - X"00000000", -- 00001C78 - X"00000000", -- 00001C7C - X"00000000", -- 00001C80 - X"00000000", -- 00001C84 - X"00000000", -- 00001C88 - X"00000000", -- 00001C8C - X"00000000", -- 00001C90 - X"00000000", -- 00001C94 - X"00000000", -- 00001C98 - X"00000000", -- 00001C9C - X"00000000", -- 00001CA0 - X"00000000", -- 00001CA4 - X"00000000", -- 00001CA8 - X"00000000", -- 00001CAC - X"00000000", -- 00001CB0 - X"00000000", -- 00001CB4 - X"00000000", -- 00001CB8 - X"00000000", -- 00001CBC - X"00000000", -- 00001CC0 - X"00000000", -- 00001CC4 - X"00000000", -- 00001CC8 - X"00000000", -- 00001CCC - X"00000000", -- 00001CD0 - X"00000000", -- 00001CD4 - X"00000000", -- 00001CD8 - X"00000000", -- 00001CDC - X"00000000", -- 00001CE0 - X"00000000", -- 00001CE4 - X"00000000", -- 00001CE8 - X"00000000", -- 00001CEC - X"00000000", -- 00001CF0 - X"00000000", -- 00001CF4 - X"00000000", -- 00001CF8 - X"00000000", -- 00001CFC - X"00000000", -- 00001D00 - X"00000000", -- 00001D04 - X"00000000", -- 00001D08 - X"00000000", -- 00001D0C - X"00000000", -- 00001D10 - X"00000000", -- 00001D14 - X"00000000", -- 00001D18 - X"00000000", -- 00001D1C - X"00000000", -- 00001D20 - X"00000000", -- 00001D24 - X"00000000", -- 00001D28 - X"00000000", -- 00001D2C - X"00000000", -- 00001D30 - X"00000000", -- 00001D34 - X"00000000", -- 00001D38 - X"00000000", -- 00001D3C - X"00000000", -- 00001D40 - X"00000000", -- 00001D44 - X"00000000", -- 00001D48 - X"00000000", -- 00001D4C - X"00000000", -- 00001D50 - X"00000000", -- 00001D54 - X"00000000", -- 00001D58 - X"00000000", -- 00001D5C - X"00000000", -- 00001D60 - X"00000000", -- 00001D64 - X"00000000", -- 00001D68 - X"00000000", -- 00001D6C - X"00000000", -- 00001D70 - X"00000000", -- 00001D74 - X"00000000", -- 00001D78 - X"00000000", -- 00001D7C - X"00000000", -- 00001D80 - X"00000000", -- 00001D84 - X"00000000", -- 00001D88 - X"00000000", -- 00001D8C - X"00000000", -- 00001D90 - X"00000000", -- 00001D94 - X"00000000", -- 00001D98 - X"00000000", -- 00001D9C - X"00000000", -- 00001DA0 - X"00000000", -- 00001DA4 - X"00000000", -- 00001DA8 - X"00000000", -- 00001DAC - X"00000000", -- 00001DB0 - X"00000000", -- 00001DB4 - X"00000000", -- 00001DB8 - X"00000000", -- 00001DBC - X"00000000", -- 00001DC0 - X"00000000", -- 00001DC4 - X"00000000", -- 00001DC8 - X"00000000", -- 00001DCC - X"00000000", -- 00001DD0 - X"00000000", -- 00001DD4 - X"00000000", -- 00001DD8 - X"00000000", -- 00001DDC - X"00000000", -- 00001DE0 - X"00000000", -- 00001DE4 - X"00000000", -- 00001DE8 - X"00000000", -- 00001DEC - X"00000000", -- 00001DF0 - X"00000000", -- 00001DF4 - X"00000000", -- 00001DF8 - X"00000000", -- 00001DFC - X"00000000", -- 00001E00 - X"00000000", -- 00001E04 - X"00000000", -- 00001E08 - X"00000000", -- 00001E0C - X"00000000", -- 00001E10 - X"00000000", -- 00001E14 - X"00000000", -- 00001E18 - X"00000000", -- 00001E1C - X"00000000", -- 00001E20 - X"00000000", -- 00001E24 - X"00000000", -- 00001E28 - X"00000000", -- 00001E2C - X"00000000", -- 00001E30 - X"00000000", -- 00001E34 - X"00000000", -- 00001E38 - X"00000000", -- 00001E3C - X"00000000", -- 00001E40 - X"00000000", -- 00001E44 - X"00000000", -- 00001E48 - X"00000000", -- 00001E4C - X"00000000", -- 00001E50 - X"00000000", -- 00001E54 - X"00000000", -- 00001E58 - X"00000000", -- 00001E5C - X"00000000", -- 00001E60 - X"00000000", -- 00001E64 - X"00000000", -- 00001E68 - X"00000000", -- 00001E6C - X"00000000", -- 00001E70 - X"00000000", -- 00001E74 - X"00000000", -- 00001E78 - X"00000000", -- 00001E7C - X"00000000", -- 00001E80 - X"00000000", -- 00001E84 - X"00000000", -- 00001E88 - X"00000000", -- 00001E8C - X"00000000", -- 00001E90 - X"00000000", -- 00001E94 - X"00000000", -- 00001E98 - X"00000000", -- 00001E9C - X"00000000", -- 00001EA0 - X"00000000", -- 00001EA4 - X"00000000", -- 00001EA8 - X"00000000", -- 00001EAC - X"00000000", -- 00001EB0 - X"00000000", -- 00001EB4 - X"00000000", -- 00001EB8 - X"00000000", -- 00001EBC - X"00000000", -- 00001EC0 - X"00000000", -- 00001EC4 - X"00000000", -- 00001EC8 - X"00000000", -- 00001ECC - X"00000000", -- 00001ED0 - X"00000000", -- 00001ED4 - X"00000000", -- 00001ED8 - X"00000000", -- 00001EDC - X"00000000", -- 00001EE0 - X"00000000", -- 00001EE4 - X"00000000", -- 00001EE8 - X"00000000", -- 00001EEC - X"00000000", -- 00001EF0 - X"00000000", -- 00001EF4 - X"00000000", -- 00001EF8 - X"00000000", -- 00001EFC - X"00000000", -- 00001F00 - X"00000000", -- 00001F04 - X"00000000", -- 00001F08 - X"00000000", -- 00001F0C - X"00000000", -- 00001F10 - X"00000000", -- 00001F14 - X"00000000", -- 00001F18 - X"00000000", -- 00001F1C - X"00000000", -- 00001F20 - X"00000000", -- 00001F24 - X"00000000", -- 00001F28 - X"00000000", -- 00001F2C - X"00000000", -- 00001F30 - X"00000000", -- 00001F34 - X"00000000", -- 00001F38 - X"00000000", -- 00001F3C - X"00000000", -- 00001F40 - X"00000000", -- 00001F44 - X"00000000", -- 00001F48 - X"00000000", -- 00001F4C - X"00000000", -- 00001F50 - X"00000000", -- 00001F54 - X"00000000", -- 00001F58 - X"00000000", -- 00001F5C - X"00000000", -- 00001F60 - X"00000000", -- 00001F64 - X"00000000", -- 00001F68 - X"00000000", -- 00001F6C - X"00000000", -- 00001F70 - X"00000000", -- 00001F74 - X"00000000", -- 00001F78 - X"00000000", -- 00001F7C - X"00000000", -- 00001F80 - X"00000000", -- 00001F84 - X"00000000", -- 00001F88 - X"00000000", -- 00001F8C - X"00000000", -- 00001F90 - X"00000000", -- 00001F94 - X"00000000", -- 00001F98 - X"00000000", -- 00001F9C - X"00000000", -- 00001FA0 - X"00000000", -- 00001FA4 - X"00000000", -- 00001FA8 - X"00000000", -- 00001FAC - X"00000000", -- 00001FB0 - X"00000000", -- 00001FB4 - X"00000000", -- 00001FB8 - X"00000000", -- 00001FBC - X"00000000", -- 00001FC0 - X"00000000", -- 00001FC4 - X"00000000", -- 00001FC8 - X"00000000", -- 00001FCC - X"00000000", -- 00001FD0 - X"00000000", -- 00001FD4 - X"00000000", -- 00001FD8 - X"00000000", -- 00001FDC - X"00000000", -- 00001FE0 - X"00000000", -- 00001FE4 - X"00000000", -- 00001FE8 - X"00000000", -- 00001FEC - X"00000000", -- 00001FF0 - X"00000000", -- 00001FF4 - X"00000000", -- 00001FF8 - X"00000000" -- 00001FFC - ); - -begin - -PROM_READ: - process(clk) - begin - if rising_edge(clk) and ce = '1' then - dout <= word_array(to_integer(addr(12 downto 2))); - end if; - end process; - - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length); - jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout; - - end if; - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - word_array(to_integer(jtag_ld_addr(10 downto 0))) <= jtag_ld_din; - else - jtag_ld_dout <= word_array(to_integer(jtag_ld_addr(10 downto 0))); - end if; - end if; - end process; - -end data; diff --git a/projects/mips_sys/src/clockgen_virtex4.vhd b/projects/mips_sys/src/clockgen_virtex4.vhd deleted file mode 100644 index d8bebfd..0000000 --- a/projects/mips_sys/src/clockgen_virtex4.vhd +++ /dev/null @@ -1,363 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: Clock generator (Virtex-4 specific) --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library ieee, work; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -USE WORK.utils_pkg.ALL; - -Library UNISIM; -use UNISIM.vcomponents.all; - -entity clockgen is - generic - ( - clk_in_freq : real := 100.0; - cpu_clk_out_freq : real := 100.0; - vga_clk_out_freq : real := 100.0; - sdr0_clk_out_phaseshift : integer := 0; - sdr1_clk_out_phaseshift : integer := 0 - ); - port - ( - -- Clocks and Reset - rst_in : in std_logic; -- external async reset, low active - clk_in : in std_logic; -- system clock (e.g. 100MHz), from board - sys_clk_out : out std_logic; - cpu_clk_out : out std_logic; - vga_clk_out : out std_logic; - sdr0_clk_fb_in : in std_logic; -- feedback clock - sdr0_clk0_out : out std_logic; -- System clock #0, dcm#0 output 0° - sdr0_clk270_out : out std_logic; -- System clock #0, dcm#0 output 270° - sdr1_clk0_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0° - sdr1_clk270_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270° - sys_rst_out : out std_logic -- DCM locked status - ); -end; - -architecture tech of clockgen is - - signal dcm_rst : unsigned(2 downto 0); - signal vga_clk0 : std_logic; - signal vga_clkfx : std_logic; - signal vga_clk0_bufg : std_logic; - signal sys_clk0 : std_logic; - signal sys_clk0_bufg : std_logic; - signal cpu_clkfx : std_logic; - signal cpu_clkfx_bufg : std_logic; - signal sdr0_clk0 : std_logic; - signal sdr0_clk270 : std_logic; - signal sdr1_clk0 : std_logic; - signal sdr1_clk270 : std_logic; - signal sdr1_clk0_bufg : std_logic; - signal reset_cnt : unsigned(4 downto 0); - signal reset_pipe0 : unsigned(19 downto 0); - signal reset_pipe1 : unsigned(19 downto 0); - signal reset_pipe2 : unsigned(19 downto 0); - signal vga_fx_lock : std_logic; - signal sys_fx_lock : std_logic; - signal sdr0_lock : std_logic; - signal sdr1_lock : std_logic; - - -begin - - ------------------------------------------------------------------------------------------------------- - -- Clock generation - ------------------------------------------------------------------------------------------------------- - - -- Compnent instantiation - inst_DCM_VGA_FX : DCM_BASE - generic map - ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, vga_clk_out_freq), -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, vga_clk_out_freq), -- Can be any integer from 2 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00 - CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X - DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE - DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" - PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023 - STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - ) - port map - ( - CLK0 => vga_clk0, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => open, -- 270 degree DCM CLK output - CLK2X => open, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => vga_clkfx, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => vga_fx_lock, -- DCM LOCK status output - CLKFB => vga_clk0_bufg, -- DCM clock feedback - CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM) - RST => dcm_rst(0) -- DCM asynchronous reset input - ); - -BUFG_vga_clk0 : BUFG - port map - ( - O => vga_clk0_bufg, -- Clock buffer output - I => vga_clk0 -- Clock buffer input - ); - -BUFG_vga_clkfx : BUFG - port map - ( - O => vga_clk_out, -- Clock buffer output - I => vga_clkfx -- Clock buffer input - ); - - -- Compnent instantiation - inst_DCM_CPU_FX : DCM_BASE - generic map - ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, cpu_clk_out_freq), -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, cpu_clk_out_freq), -- Can be any integer from 2 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00 - CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X - DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE - DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" - PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023 - STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - ) - port map - ( - CLK0 => sys_clk0, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => open, -- 270 degree DCM CLK output - CLK2X => open, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => cpu_clkfx, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => sys_fx_lock, -- DCM LOCK status output - CLKFB => sys_clk0_bufg, -- DCM clock feedback - CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM) - RST => dcm_rst(0) -- DCM asynchronous reset input - ); - -BUFG_sys_clk0 : BUFG - port map - ( - O => sys_clk0_bufg, -- Clock buffer output - I => sys_clk0 -- Clock buffer input - ); - -BUFG_sys_clkfx : BUFG - port map - ( - O => cpu_clkfx_bufg, -- Clock buffer output - I => cpu_clkfx -- Clock buffer input - ); - - sys_clk_out <= sys_clk0_bufg; - cpu_clk_out <= cpu_clkfx_bufg; - -inst_DCM_SDRCLK_0 : DCM_BASE - generic map - ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00 - CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X - DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE - DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE - DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" - PHASE_SHIFT => sdr0_clk_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023 - STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - ) - port map - ( - CLK0 => sdr0_clk0, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => sdr0_clk270, -- 270 degree DCM CLK output - CLK2X => open, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => open, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => sdr0_lock, -- DCM LOCK status output - CLKFB => sdr0_clk_fb_in, -- DCM clock feedback - CLKIN => sys_clk0_bufg, -- Clock input (from IBUFG, BUFG or DCM) - RST => dcm_rst(1) -- DCM asynchronous reset input - ); - -bufg_sdr0_clk0: bufg - port map - ( - o => sdr0_clk0_out, - i => sdr0_clk0 - ); - -bufg_sdr0_clk270: bufg - port map ( - o => sdr0_clk270_out, - i => sdr0_clk270 - ); - - inst_DCM_SDRCLK_1 : DCM_BASE - generic map - ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00 - CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X - DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE - DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE - DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" - PHASE_SHIFT => sdr1_clk_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023 - STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - ) - port map - ( - CLK0 => sdr1_clk0, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => sdr1_clk270, -- 270 degree DCM CLK output - CLK2X => open, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => open, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => sdr1_lock, -- DCM LOCK status output - CLKFB => sdr1_clk0_bufg, -- DCM clock feedback - CLKIN => sdr0_clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM) - RST => dcm_rst(2) -- DCM asynchronous reset input - ); - - sdr1_clk0_out <= sdr1_clk0_bufg; - -bufg_sdr1_clk0: bufg - port map - ( - o => sdr1_clk0_bufg, - i => sdr1_clk0 - ); - - -bufg_sdr1_clk270: bufg - port map ( - o => sdr1_clk270_out, - i => sdr1_clk270 - ); - - dcm_rst(0) <= reset_pipe0(reset_pipe0'left); - -dcm_reset0: - process(rst_in, clk_in) - begin - if rst_in = '1' then - reset_pipe0 <= (others => '1'); - elsif rising_edge(clk_in) then - reset_pipe0 <= reset_pipe0(reset_pipe0'left-1 downto 0) & '0'; - end if; - - end process; - - dcm_rst(1) <= reset_pipe1(reset_pipe1'left); - -dcm_reset1: - process(vga_fx_lock, clk_in) - begin - if vga_fx_lock = '0' then - reset_pipe1 <= (others => '1'); - elsif rising_edge(clk_in) then - reset_pipe1 <= reset_pipe1(reset_pipe1'left-1 downto 0) & '0'; - end if; - - end process; - - dcm_rst(2) <= reset_pipe2(reset_pipe2'left); - -dcm_reset2: - process(sdr0_lock, clk_in) - begin - if sdr0_lock = '0' then - reset_pipe2 <= (others => '1'); - elsif rising_edge(clk_in) then - reset_pipe2 <= reset_pipe2(reset_pipe2'left-1 downto 0) & '0'; - end if; - - end process; - -reset_out_logic: - process(rst_in, clk_in, sdr0_lock, sdr1_lock, sys_fx_lock, vga_fx_lock) - begin - if rst_in = '1' or sdr0_lock = '0' or sdr1_lock = '0' or sys_fx_lock = '0' or vga_fx_lock = '0' then - sys_rst_out <= '1'; - reset_cnt <= (reset_cnt'left downto reset_cnt'right => '1'); - elsif rising_edge(clk_in) then - if reset_cnt /= (reset_cnt'left downto reset_cnt'right => '0') then - reset_cnt <= reset_cnt - 1; - else - sys_rst_out <= '0'; - end if; - end if; - - end process; - -end architecture tech; - - diff --git a/projects/mips_sys/src/mips_sys.vhd b/projects/mips_sys/src/mips_sys.vhd deleted file mode 100644 index b59b783..0000000 --- a/projects/mips_sys/src/mips_sys.vhd +++ /dev/null @@ -1,1170 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: system test using Xilinx ML-402 - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -Library UNISIM; -use UNISIM.vcomponents.all; - -library work; -use work.mips_types.all; -use work.sdram_config.all; -use work.sdram_types.all; -use work.vga_types.all; -use work.async_types.all; -use work.async_defs.all; - - -ENTITY mips_sys IS -GENERIC -( - sys_freq_in : real := 100.0; - cpu_freq : real := 100.0; - sdram_phaseshift : integer := 0; - tsvga : vga_timespec_t := ts_vga_800_600_60 - -); -PORT -( - sys_rst_n_in : in std_logic; - sys_clk_in : in std_logic; - - -- Buttons and LEDs - sys_btn : in unsigned(4 downto 0); - sys_dip : in unsigned(7 downto 0); - sys_led : out unsigned(8 downto 0); - - -- UART - sys_uart0_rx : in std_logic; - sys_uart0_tx : out std_logic; - sys_uart1_rx : in std_logic; - sys_uart1_tx : out std_logic; - sys_uart2_rx : in std_logic; - sys_uart2_tx : out std_logic; - sys_uart3_rx : in std_logic; - sys_uart3_tx : out std_logic; - - -- LCD - sys_lcd_d : inout unsigned(3 downto 0); - sys_lcd_e : out std_logic; - sys_lcd_rs : out std_logic; - sys_lcd_rw : out std_logic; - - -- DDR SDRAM - sys_sdr_clk_p : out std_logic; -- ddr_sdram_clock - sys_sdr_clk_n : out std_logic; -- /ddr_sdram_clock - sys_sdr_cke_q : out std_logic; -- clock enable - sys_sdr_cs_qn : out std_logic; -- /chip select - sys_sdr_ras_qn : out std_logic; -- /ras - sys_sdr_cas_qn : out std_logic; -- /cas - sys_sdr_we_qn : out std_logic; -- /write enable - sys_sdr_dm_q : out unsigned(DDR_DM_WIDTH-1 downto 0); -- data mask bits, set to "00" - sys_sdr_dqs_q : inout unsigned(DDR_DQS_WIDTH-1 downto 0); -- data strobe, only for write - sys_sdr_ba_q : out unsigned(DDR_BANK_WIDTH-1 downto 0); -- bank select - sys_sdr_a_q : out unsigned(DDR_ADDR_WIDTH-1 downto 0); -- address bus - sys_sdr_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus - sys_sdr_clk_fb : in std_logic; - - -- VGA - sys_vga_clk : out std_logic; - sys_vga_red : out unsigned(7 downto 0); - sys_vga_green : out unsigned(7 downto 0); - sys_vga_blue : out unsigned(7 downto 0); - sys_vga_blank_n : out std_logic; - sys_vga_sync_n : out std_logic; - sys_vga_hsync : out std_logic; - sys_vga_vsync : out std_logic; - - sys_usb_d : inout unsigned(15 downto 0); - sys_usb_a : out unsigned(1 downto 0); - sys_usb_csn : out std_logic; - sys_usb_wrn : out std_logic; - sys_usb_rdn : out std_logic; - sys_usb_rstn : out std_logic; - sys_usb_int : in std_logic; - - sys_flash_d : inout unsigned(31 downto 0); - sys_flash_a : out unsigned(24 downto 0); - sys_flash_ce : out std_logic; - sys_flash_wrn : out std_logic; - sys_flash_rdn : out std_logic; - sys_flash_ac97_rstn : out std_logic; - sys_flash_byten : out std_logic; - - sys_ac97_sdata_in : in std_logic; - sys_ac97_bit_clk : in std_logic; - sys_ac97_sdata_out : out std_logic; - sys_ac97_ssync : out std_logic; - - sys_ps2_0_clk : inout std_logic; - sys_ps2_0_data : inout std_logic; - - sys_ps2_1_clk : inout std_logic; - sys_ps2_1_data : inout std_logic; - - sys_phy_rstn : out std_logic; - sys_phy_mdc : out std_logic; - sys_phy_mdio : inout std_logic; - sys_phy_int : in std_logic; - - sys_phy_rx_clk : in STD_LOGIC; - sys_phy_rx_dv : in STD_LOGIC; - sys_phy_rx_er : in STD_LOGIC; - sys_phy_rx : in unsigned(7 downto 0); - sys_phy_tx_clk : in STD_LOGIC; - sys_phy_tx_en : out STD_LOGIC; - sys_phy_tx_er : out STD_LOGIC; - sys_phy_tx : out unsigned(7 downto 0); - sys_phy_gtx_clk : out STD_LOGIC; - sys_phy_crs : in STD_LOGIC; - sys_phy_col : in STD_LOGIC; - - sys_error : out unsigned(1 downto 0) -- indicates Errors - -); --- attribute BUFFER_TYPE : string; --- attribute BUFFER_TYPE of sys_clk_in : signal is "BUFG"; --- attribute BUFFER_TYPE of sys_sdr_dcm_clk_fb : signal is "BUFG"; - -END mips_sys; - -ARCHITECTURE behavior OF mips_sys IS - - COMPONENT mips_top - Port - ( - debug : out chip_debug_t; - eb : in STD_LOGIC; - nmi : in STD_LOGIC; - cpu_clk : in STD_LOGIC; - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - ACK_I : in STD_LOGIC; - SRDY_I : in STD_LOGIC; - ADDR_O : out word_t; - DAT_I : in word_t; - DAT_O : out word_t; - WE_O : out STD_LOGIC; - SEL_O : out unsigned(3 downto 0); - CYC_O : out STD_LOGIC; - STB_O : out STD_LOGIC; - MRDY_O : out STD_LOGIC; - INT : in unsigned (5 downto 0) - - ); - END COMPONENT; - - COMPONENT rom_wb - PORT - ( - CLK_I : in STD_LOGIC; - RST_I : in STD_LOGIC; - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - WE_I : in STD_LOGIC; - ACK_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - SRDY_O : out STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0) - ); - END COMPONENT; - - COMPONENT lcd_port - PORT - ( - rst : in std_logic; - clk : in std_logic; - we : in std_logic; - din : in unsigned(7 downto 0); - dout : out unsigned(7 downto 0); - lcd_d : inout unsigned(3 downto 0); - lcd_e : out std_logic; - lcd_rs : out std_logic; - lcd_rw : out std_logic - ); - END COMPONENT; - - COMPONENT async_port_wb - GENERIC - ( - f_sysclk : real := sys_freq_in; - addr_width : natural := 32; - data_width : natural := 32; - byte_sel_width : natural := 4; - async_timespec : async_timespec_t - ); - PORT - ( - CLK_I : in STD_LOGIC; - RST_I : in STD_LOGIC; - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - WE_I : in STD_LOGIC; - ACK_O : out STD_LOGIC; - SRDY_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - SEL_I : in unsigned(3 downto 0); - ADDR_I : in unsigned(31 downto 0); - DAT_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0); - page_mode_en : in STD_LOGIC; - async_a : out unsigned(addr_width-1 downto 0); - async_d : inout unsigned(data_width-1 downto 0); - async_cs : out std_logic; - async_wr : out std_logic; - async_rd : out std_logic; - async_be : out unsigned(byte_sel_width-1 downto 0); - async_rst : out std_logic - ); - END COMPONENT; - - COMPONENT uart_wb - PORT - ( - CLK_I : in STD_LOGIC; - RST_I : in STD_LOGIC; - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - SEL_I : in unsigned(3 downto 0); - WE_I : in STD_LOGIC; - ACK_O : out STD_LOGIC; - SRDY_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - DAT_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0); - INT_O : out STD_LOGIC; - ser_rx : in std_logic; - ser_tx : out std_logic - ); - END COMPONENT; - - COMPONENT gpio_wb - Generic - ( - f_sysclk : real := sys_freq_in - ); - PORT - ( - CLK_I : in STD_LOGIC; - RST_I : in STD_LOGIC; - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - SEL_I : in unsigned(3 downto 0); - WE_I : in STD_LOGIC; - ACK_O : out STD_LOGIC; - SRDY_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - DAT_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0); - INT_TIM_O : out STD_LOGIC; - - sys_gpi_0 : in unsigned(31 downto 0); - sys_gpo_0 : out unsigned(31 downto 0) - ); - END COMPONENT; - - COMPONENT vga_frontend64 - GENERIC - ( - fifo_depth : integer; - fifo_almost_full_thresh : natural; - fifo_almost_empty_thresh : natural; - tsvga : vga_timespec_t - ); - PORT - ( - -- System signals - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - - -- JBUS Master signals - CYC_O : out STD_LOGIC; - STB_O : out STD_LOGIC; - WE_O : out STD_LOGIC; - SEL_O : out unsigned(7 downto 0); - ACK_I : in STD_LOGIC; - SRDY_I : in STD_LOGIC; - MRDY_O : out STD_LOGIC; - ADDR_O : out unsigned(31 downto 0); - MDAT_I : in unsigned(63 downto 0); - MDAT_O : out unsigned(63 downto 0); - - -- JBUS Slave signals - INT_O : out STD_LOGIC; - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - WE_I : in STD_LOGIC; - SEL_I : in unsigned(3 downto 0); - ACK_O : out STD_LOGIC; - SRDY_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - SDAT_I : in unsigned(31 downto 0); - SDAT_O : out unsigned(31 downto 0); - - -- VGA signals - vga_clk_in : in std_logic; - vga_clk_ce : in std_logic; - vga_red : out unsigned(7 downto 0); - vga_green : out unsigned(7 downto 0); - vga_blue : out unsigned(7 downto 0); - vga_blank_n : out std_logic; - vga_sync_n : out std_logic; - vga_hsync : out std_logic; - vga_vsync : out std_logic - ); - END COMPONENT; - - signal cpu_clk : std_logic; - signal nmi : std_logic; - signal eb : std_logic; - signal sdram_clk0 : std_logic; - signal sdram_clk270 : std_logic; - signal sdram_clk270var : std_logic; - signal vga_clk : std_logic; - signal vga_ce : std_logic; - signal rst_in : std_logic; - signal int_timer : std_logic; - signal int_uart0 : std_logic; - signal int_uart1 : std_logic; - signal uart1_tx : std_logic; - signal uart1_rx : std_logic; - signal usb_addr : unsigned(3 downto 0); - signal ac97_rstn : std_logic; - signal mem_mapped_io : std_logic; - signal flash_rstn : std_logic; - signal flash_page_mode_en : std_logic; - signal flash_addr : unsigned(24 downto 0); - signal ps2_0_clk_rx : std_logic; - signal ps2_0_data_rx : std_logic; - signal ps2_0_clk_tx : std_logic; - signal ps2_0_data_tx : std_logic; - signal ps2_1_clk_rx : std_logic; - signal ps2_1_data_rx : std_logic; - signal ps2_1_clk_tx : std_logic; - signal ps2_1_data_tx : std_logic; - - -- Arbiter - constant ARB_MAX_MASTER : natural := 2; - signal arb_idx : natural range 0 to ARB_MAX_MASTER-1; - signal arb_req : unsigned (ARB_MAX_MASTER-1 downto 0); - signal arb_gnt : unsigned (ARB_MAX_MASTER-1 downto 0); - - -- J-Bus signals - signal CLK_O : std_logic; - signal RST_O : std_logic; - signal INT : unsigned(5 downto 0); - signal MDAT_I : word_t; - signal MDAT_O : unsigned(63 downto 0); - signal ADDR_O : word_t; - signal SEL_O : unsigned(7 downto 0); - signal WE_O : std_logic; - signal CYC_O : std_logic; - signal STB_O : std_logic; - signal ACK_I : std_logic; - signal SRDY_I : std_logic; - signal MRDY_O : std_logic; - - -- CPU Master - signal MRDY_O_cpu : std_logic; - signal MDAT_O_cpu : word_t; - signal ADDR_O_cpu : word_t; - signal SEL_O_cpu : unsigned(3 downto 0); - signal WE_O_cpu : std_logic; - signal CYC_O_cpu : std_logic; - signal STB_O_cpu : std_logic; - signal SRDY_I_cpu : std_logic; - signal ACK_I_cpu : std_logic; - - -- VGA Master - signal MRDY_O_vga : std_logic; - signal ADDR_O_vga : word_t; - signal SEL_O_vga : unsigned(7 downto 0); - signal WE_O_vga : std_logic; - signal CYC_O_vga : std_logic; - signal STB_O_vga : std_logic; - signal SRDY_I_vga : std_logic; - signal ACK_I_vga : std_logic; - signal MDAT_I_vga : unsigned(63 downto 0); - signal MDAT_O_vga : unsigned(63 downto 0); - - -- Slaves - signal CYC_I_flash : std_logic; - signal ACK_O_flash : std_logic; - signal SRDY_O_flash : std_logic; - signal SDAT_O_flash : unsigned(31 downto 0); - - signal CYC_I_usb : std_logic; - signal ACK_O_usb : std_logic; - signal SRDY_O_usb : std_logic; - signal SDAT_O_usb : unsigned(31 downto 0); - - signal CYC_I_sdram : std_logic; - signal ACK_O_sdram : std_logic; - signal SRDY_O_sdram : std_logic; - signal SDAT_O_sdram : unsigned(63 downto 0); - - signal CYC_I_rom : std_logic; - signal ACK_O_rom : std_logic; - signal SRDY_O_rom : std_logic; - signal SDAT_O_rom : unsigned(31 downto 0); - - signal CYC_I_gpio : std_logic; - signal ACK_O_gpio : std_logic; - signal SRDY_O_gpio : std_logic; - signal SDAT_O_gpio : unsigned(31 downto 0); - - signal CYC_I_uart0 : std_logic; - signal ACK_O_uart0 : std_logic; - signal SRDY_O_uart0 : std_logic; - signal SDAT_O_uart0 : unsigned(31 downto 0); - signal CYC_I_uart1 : std_logic; - signal ACK_O_uart1 : std_logic; - signal SRDY_O_uart1 : std_logic; - signal SDAT_O_uart1 : unsigned(31 downto 0); - - signal INT_O_vga : std_logic; - signal CYC_I_vga : std_logic; - signal ACK_O_vga : std_logic; - signal SRDY_O_vga : std_logic; - signal SDAT_O_vga : unsigned(31 downto 0); - - signal INT_O_ac97 : std_logic; - signal CYC_I_ac97 : std_logic; - signal ACK_O_ac97 : std_logic; - signal SRDY_O_ac97 : std_logic; - signal SDAT_O_ac97 : unsigned(31 downto 0); - - signal INT_O_ps2_0 : std_logic; - signal CYC_I_ps2_0 : std_logic; - signal ACK_O_ps2_0 : std_logic; - signal SRDY_O_ps2_0 : std_logic; - signal SDAT_O_ps2_0 : unsigned(31 downto 0); - - signal INT_O_ps2_1 : std_logic; - signal CYC_I_ps2_1 : std_logic; - signal ACK_O_ps2_1 : std_logic; - signal SRDY_O_ps2_1 : std_logic; - signal SDAT_O_ps2_1 : unsigned(31 downto 0); - - signal INT_O_emac : std_logic; - signal CYC_I_emac : std_logic; - signal ACK_O_emac : std_logic; - signal SRDY_O_emac : std_logic; - signal SDAT_O_emac : unsigned(31 downto 0); - - signal gpi_0 : unsigned(31 downto 0); - signal gpo_0 : unsigned(31 downto 0); - - signal ac97_inten : std_logic; - signal usb_inten : std_logic; - signal phy_inten : std_logic; - - signal debug : chip_debug_t; - - -- DDR SDRAM - constant BURST_LEN : natural := 2; - constant vga_freq : real := real(tsvga.f_pxl_clk)/1.0E6; - - --- attribute rom_style: string; --- attribute rom_style of cmd_fifo_dout: signal is "DISTRIBUTED"; --- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED"; --- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED"; - - type mem_area_t is (mem_dead, mem_flash, mem_usb, mem_rom, mem_gpio, mem_uart0, mem_uart1, mem_ps2_0, mem_ps2_1, mem_sdram, mem_vga, mem_ac97, mem_emac); - signal mem_area : mem_area_t; - - attribute KEEP : string; - attribute KEEP of vga_clk : signal is "TRUE"; - attribute KEEP of sdram_clk0 : signal is "TRUE"; - attribute KEEP of cpu_clk : signal is "TRUE"; - attribute KEEP of CLK_O : signal is "TRUE"; - attribute KEEP of RST_O : signal is "TRUE"; - -BEGIN - - ------------------------------------ - -- GPIO_0 bits used for - -- 8.. 0 = O: LED 8..0 - -- 11.. 9 = free - -- 12 = O: USB RST - -- 13 = O: USB INTEN - -- 14 = free - -- 15 = O: AC97 INTEN - -- 32..16 = I: DIP 7..0 - -- 28..24 = I: BTN 4..0 - -- 29 = O: PHY RESET - -- 30 = O: PHY MDC - -- 31 = IO: PHY MDIO - ------------------------------------ - gpi_0(28 downto 24) <= sys_btn; - gpi_0(23 downto 16) <= sys_dip; - gpi_0(31) <= sys_phy_mdio; - - sys_led <= gpo_0(8 downto 0); - sys_usb_rstn <= not gpo_0(12); - usb_inten <= gpo_0(13); - phy_inten <= gpo_0(14); - ac97_inten <= gpo_0(15); - sys_phy_rstn <= not gpo_0(29); - sys_phy_mdc <= gpo_0(30); - sys_phy_mdio <= gpo_0(31); - - eb <= sys_dip(7); - sys_error(0) <= debug.imem_err; - sys_error(1) <= debug.dmem_err; - nmi <= not sys_rst_n_in; - rst_in <= not sys_rst_n_in and sys_btn(0); - sys_flash_byten <= '1'; - sys_usb_a <= usb_Addr(3 downto 2); - sys_flash_a <= '0' & flash_addr(24 downto 2) & '0'; - flash_page_mode_en <= not mem_mapped_io; - - sys_flash_ac97_rstn <= ac97_rstn and flash_rstn; - sys_uart1_tx <= uart1_tx; - sys_uart2_tx <= uart1_tx; - uart1_rx <= sys_uart1_rx and sys_uart2_rx; - sys_uart3_tx <= sys_uart3_rx; - - sys_vga_clk <= vga_clk; - vga_ce <= not RST_O; - - --------------------------------------------------------------- - -- Arbiter - MRDY_O <= MRDY_O_cpu when arb_gnt(0) = '1' else MRDY_O_vga when arb_gnt(1) = '1' else '0'; - MDAT_O <= (MDAT_O_cpu & MDAT_O_cpu) when arb_gnt(0) = '1' else MDAT_O_vga when arb_gnt(1) = '1' else (others => '0'); - ADDR_O <= ADDR_O_cpu when arb_gnt(0) = '1' else ADDR_O_vga when arb_gnt(1) = '1' else (others => '0'); - SEL_O <= ("0000" & SEL_O_cpu) when arb_gnt(0) = '1' else SEL_O_vga when arb_gnt(1) = '1' else (others => '0'); - WE_O <= WE_O_cpu when arb_gnt(0) = '1' else WE_O_vga when arb_gnt(1) = '1' else '0'; - CYC_O <= CYC_O_cpu when arb_gnt(0) = '1' else CYC_O_vga when arb_gnt(1) = '1' else '0'; - STB_O <= STB_O_cpu when arb_gnt(0) = '1' else STB_O_vga when arb_gnt(1) = '1' else '0'; - SRDY_I_cpu <= SRDY_I and arb_gnt(0); - SRDY_I_vga <= SRDY_I and arb_gnt(1); - ACK_I_cpu <= ACK_I and arb_gnt(0); - ACK_I_vga <= ACK_I and arb_gnt(1); - - arb_req(0) <= CYC_O_cpu; - arb_req(1) <= CYC_O_vga; - - MDAT_I_vga <= SDAT_O_sdram; - -arbiter_proc: - process(CLK_O) - begin - if rising_edge(CLK_O) then - if RST_O = '1' then - arb_gnt <= (others => '0'); - arb_idx <= 0; - elsif arb_req(arb_idx) = '0' then - if arb_idx /= ARB_MAX_MASTER-1 then - arb_idx <= arb_idx + 1; - else - arb_idx <= 0; - end if; - else - arb_gnt <= (others => '0'); - arb_gnt(arb_idx) <= '1'; - end if; - end if; - end process; - -int_sample: - process(CLK_O) - begin - if rising_edge(CLK_O) then - INT <= int_timer & (INT_O_ps2_0 or INT_O_ps2_1 or INT_O_emac) & (INT_O_vga or (ac97_inten and INT_O_ac97)) & (usb_inten and sys_usb_int) & (int_uart0 or int_uart1) & sys_btn(4); - end if; - end process; - -mem_mux: - process(ADDR_O) - begin - mem_area <= mem_dead; - mem_mapped_io <= '0'; - if ADDR_O(31 downto 28) = X"0" then - mem_area <= mem_flash; - elsif ADDR_O(31 downto 28) = X"1" then - mem_area <= mem_emac; - elsif ADDR_O(31 downto 28) = X"A" then - mem_mapped_io <= '1'; - if ADDR_O(27 downto 26) = "00" then - if ADDR_O(18 downto 16) = "000" then - mem_area <= mem_gpio; - elsif ADDR_O(18 downto 16) = "001" then - if ADDR_O(9 downto 8) = "00" then - mem_area <= mem_uart0; - elsif ADDR_O(9 downto 8) = "01" then - mem_area <= mem_uart1; - elsif ADDR_O(9 downto 8) = "10" then - mem_area <= mem_ps2_0; - elsif ADDR_O(9 downto 8) = "11" then - mem_area <= mem_ps2_1; - end if; - elsif ADDR_O(18 downto 16) = "010" then - mem_area <= mem_usb; - elsif ADDR_O(18 downto 16) = "011" then - mem_area <= mem_vga; - elsif ADDR_O(18 downto 16) = "100" then - mem_area <= mem_ac97; - elsif ADDR_O(18 downto 16) = "101" then - mem_area <= mem_emac; - end if; - elsif ADDR_O(27 downto 26) = "01" then - mem_area <= mem_flash; - end if; - elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then - mem_area <= mem_rom; - elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then - mem_area <= mem_sdram; - end if; - end process; - -signal_mux: - process(mem_area, CYC_O) - begin - - CYC_I_uart0 <= '0'; - CYC_I_uart1 <= '0'; - CYC_I_ps2_0 <= '0'; - CYC_I_ps2_1 <= '0'; - CYC_I_gpio <= '0'; - CYC_I_flash <= '0'; - CYC_I_usb <= '0'; - CYC_I_rom <= '0'; - CYC_I_sdram <= '0'; - CYC_I_vga <= '0'; - CYC_I_ac97 <= '0'; - CYC_I_emac <= '0'; - - case mem_area is - - when mem_gpio => - CYC_I_gpio <= CYC_O; - - when mem_uart0 => - CYC_I_uart0 <= CYC_O; - - when mem_uart1 => - CYC_I_uart1 <= CYC_O; - - when mem_ps2_0 => - CYC_I_ps2_0 <= CYC_O; - - when mem_ps2_1 => - CYC_I_ps2_1 <= CYC_O; - - when mem_flash => - CYC_I_flash <= CYC_O; - - when mem_usb => - CYC_I_usb <= CYC_O; - - when mem_rom => - CYC_I_rom <= CYC_O; - - when mem_sdram => - CYC_I_sdram <= CYC_O; - - when mem_vga => - CYC_I_vga <= CYC_O; - - when mem_ac97 => - CYC_I_ac97 <= CYC_O; - - when mem_emac => - CYC_I_emac <= CYC_O; - - when others => null; - - end case; - - end process; - ------------------------------------------------------------------- - SRDY_I <= SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart0 or SRDY_O_uart1 or SRDY_O_ps2_0 or SRDY_O_ps2_1 or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97 or SRDY_O_emac; - ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_rom or ACK_O_uart0 or ACK_O_uart1 or ACK_O_ps2_0 or ACK_O_ps2_1 or ACK_O_gpio or ACK_O_vga or ACK_O_ac97 or ACK_O_emac; - MDAT_I <= SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else - SDAT_O_rom when CYC_I_rom = '1' else - SDAT_O_flash when CYC_I_flash = '1' else - SDAT_O_usb when CYC_I_usb = '1' else - SDAT_O_uart0 when CYC_I_uart0 = '1' else - SDAT_O_uart1 when CYC_I_uart1 = '1' else - SDAT_O_ps2_0 when CYC_I_ps2_0 = '1' else - SDAT_O_ps2_1 when CYC_I_ps2_1 = '1' else - SDAT_O_vga when CYC_I_vga = '1' else - SDAT_O_ac97 when CYC_I_ac97 = '1' else - SDAT_O_emac when CYC_I_emac = '1' else - SDAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF"; - ------------------------------------------------------------------- -inst_mips_top: mips_top - PORT MAP - ( - debug => debug, - eb => eb, - nmi => nmi, - cpu_clk => cpu_clk, - RST_I => RST_O, - CLK_I => CLK_O, - ACK_I => ACK_I_cpu, - SRDY_I => SRDY_I_cpu, - MRDY_O => MRDY_O_cpu, - CYC_O => CYC_O_cpu, - STB_O => STB_O_cpu, - WE_O => WE_O_cpu, - SEL_O => SEL_O_cpu, - DAT_I => MDAT_I, - DAT_O => MDAT_O_cpu, - ADDR_O => ADDR_O_cpu, - INT => INT - ); - -inst_rom_wb : rom_wb - PORT MAP - ( - CLK_I => CLK_O, - RST_I => RST_O, - CYC_I => CYC_I_rom, - STB_I => STB_O, - WE_I => WE_O, - ACK_O => ACK_O_rom, - MRDY_I => MRDY_O, - SRDY_O => SRDY_O_rom, - ADDR_I => ADDR_O, - DAT_O => SDAT_O_rom - ); - - -inst_lcd_port: lcd_port - PORT MAP - ( - clk => CLK_O, - rst => RST_O, - we => '0', - din => X"00", - dout => open, - lcd_d => sys_lcd_d, - lcd_e => sys_lcd_e, - lcd_rs => sys_lcd_rs, - lcd_rw => sys_lcd_rw - ); - -inst_gpio_wb : gpio_wb - GENERIC MAP - ( - f_sysclk => sys_freq_in - ) - PORT MAP - ( - CLK_I => CLK_O, - RST_I => RST_O, - CYC_I => CYC_I_gpio, - STB_I => STB_O, - SEL_I => SEL_O(3 downto 0), - WE_I => WE_O, - ACK_O => ACK_O_gpio, - SRDY_O => SRDY_O_gpio, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => MDAT_O(31 downto 0), - DAT_O => SDAT_O_gpio, - INT_TIM_O => int_timer, - - sys_gpi_0 => gpi_0, - sys_gpo_0 => gpo_0 - ); - -inst_flash_port : async_port_wb - GENERIC MAP - ( - f_sysclk => sys_freq_in, - addr_width => 25, - data_width => 32, - byte_sel_width => 1, - async_timespec => ts_flash - ) - PORT MAP - ( - CLK_I => CLK_O, - RST_I => RST_O, - CYC_I => CYC_I_flash, - STB_I => STB_O, - WE_I => WE_O, - ACK_O => ACK_O_flash, - SRDY_O => SRDY_O_flash, - MRDY_I => MRDY_O, - SEL_I => SEL_O(3 downto 0), - ADDR_I => ADDR_O, - DAT_I => MDAT_O(31 downto 0), - DAT_O => SDAT_O_flash, - page_mode_en => flash_page_mode_en, - async_a => flash_addr, - async_d => sys_flash_d, - async_cs => sys_flash_ce, - async_wr => sys_flash_wrn, - async_rd => sys_flash_rdn, - async_be => open, - async_rst => flash_rstn - ); - -inst_usb_port : async_port_wb - GENERIC MAP - ( - f_sysclk => sys_freq_in, - addr_width => 4, - data_width => 16, - byte_sel_width => 1, - async_timespec => ts_usb - ) - PORT MAP - ( - CLK_I => CLK_O, - RST_I => RST_O, - CYC_I => CYC_I_usb, - STB_I => STB_O, - WE_I => WE_O, - ACK_O => ACK_O_usb, - SRDY_O => SRDY_O_usb, - MRDY_I => MRDY_O, - SEL_I => SEL_O(3 downto 0), - ADDR_I => ADDR_O, - DAT_I => MDAT_O(31 downto 0), - DAT_O => SDAT_O_usb, - page_mode_en => '0', - async_a => usb_addr, - async_d => sys_usb_d, - async_cs => sys_usb_csn, - async_wr => sys_usb_wrn, - async_rd => sys_usb_rdn, - async_be => open, - async_rst => open - ); - -inst_uart_wb_0 : uart_wb - PORT MAP - ( - CLK_I => CLK_O, - RST_I => RST_O, - CYC_I => CYC_I_uart0, - STB_I => STB_O, - SEL_I => SEL_O(3 downto 0), - WE_I => WE_O, - ACK_O => ACK_O_uart0, - SRDY_O => SRDY_O_uart0, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => MDAT_O(31 downto 0), - DAT_O => SDAT_O_uart0, - INT_O => int_uart0, - ser_rx => sys_uart0_rx, - ser_tx => sys_uart0_tx - ); - -inst_uart_wb_1 : uart_wb - PORT MAP - ( - CLK_I => CLK_O, - RST_I => RST_O, - CYC_I => CYC_I_uart1, - STB_I => STB_O, - SEL_I => SEL_O(3 downto 0), - WE_I => WE_O, - ACK_O => ACK_O_uart1, - SRDY_O => SRDY_O_uart1, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => MDAT_O(31 downto 0), - DAT_O => SDAT_O_uart1, - INT_O => int_uart1, - ser_rx => uart1_rx, - ser_tx => uart1_tx - ); - - -inst_clockgen : entity work.clockgen - GENERIC MAP - ( - clk_in_freq => sys_freq_in, - cpu_clk_out_freq => cpu_freq, - vga_clk_out_freq => vga_freq, - sdr0_clk_out_phaseshift => 0, - sdr1_clk_out_phaseshift => 0 - ) - PORT MAP - ( - -- Clocks and Reset - rst_in => rst_in, -- external async reset, low active - clk_in => sys_clk_in, -- system clock (e.g. 100MHz), from board - sys_rst_out => RST_O, - sys_clk_out => CLK_O, - vga_clk_out => vga_clk, - cpu_clk_out => cpu_clk, - sdr0_clk_fb_in => sys_sdr_clk_fb, -- feedback clock - sdr0_clk0_out => sdram_clk0, -- System clock #0, dcm#0 output 0° - sdr0_clk270_out => sdram_clk270, -- System clock #0, dcm#0 output 270° - sdr1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0° - sdr1_clk270_out => sdram_clk270var -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270° - ); - -inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb - GENERIC MAP - ( - BL => BURST_LEN, - f_sysclk => sys_freq_in, - f_sdrclk => sys_freq_in, - fifo_depth => 5 - ) - PORT MAP - ( - RST_I => RST_O, - CLK_I => CLK_O, - - SDRAM_CLK0_I => sdram_clk0, - SDRAM_CLK270_I => sdram_clk270, - SDRAM_CLK270VAR_I => sdram_clk270var, - - CYC_I => CYC_I_sdram, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_O_sdram, - MRDY_I => MRDY_O, - SRDY_O => SRDY_O_sdram, - ADDR_I => ADDR_O, - DAT_I => MDAT_O, - DAT_O => SDAT_O_sdram, - - -- SDRAM signals - sd_clk_p => sys_sdr_clk_p, - sd_clk_n => sys_sdr_clk_n, - sd_cke => sys_sdr_cke_q, - sd_cs_n => sys_sdr_cs_qn, - sd_cas_n => sys_sdr_cas_qn, - sd_ras_n => sys_sdr_ras_qn, - sd_we_n => sys_sdr_we_qn, - sd_addr => sys_sdr_a_q, - sd_ba => sys_sdr_ba_q, - sd_dm => sys_sdr_dm_q, - sd_dqs => sys_sdr_dqs_q, - sd_data => sys_sdr_data - - ); - -inst_vga_frontend : vga_frontend64 - GENERIC MAP - ( - fifo_depth => 4096, - fifo_almost_full_thresh => 4000, - fifo_almost_empty_thresh => 800, - tsvga => tsvga - ) - PORT MAP - ( - -- System signals - RST_I => RST_O, - CLK_I => CLK_O, - - -- JBUS Master signals - CYC_O => CYC_O_vga, - STB_O => STB_O_vga, - WE_O => WE_O_vga, - SEL_O => SEL_O_vga, - ACK_I => ACK_I_vga, - SRDY_I => SRDY_I_vga, - MRDY_O => MRDY_O_vga, - ADDR_O => ADDR_O_vga, - MDAT_I => MDAT_I_vga, - MDAT_O => MDAT_O_vga, - - -- JBUS Slave signals - INT_O => INT_O_vga, - CYC_I => CYC_I_vga, - STB_I => STB_O, - WE_I => WE_O, - SEL_I => SEL_O(3 downto 0), - ACK_O => ACK_O_vga, - SRDY_O => SRDY_O_vga, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - SDAT_I => MDAT_O(31 downto 0), - SDAT_O => SDAT_O_vga, - - -- VGA signals - vga_clk_in => vga_clk, - vga_clk_ce => vga_ce, - vga_red => sys_vga_red, - vga_green => sys_vga_green, - vga_blue => sys_vga_blue, - vga_blank_n => sys_vga_blank_n, - vga_sync_n => sys_vga_sync_n, - vga_hsync => sys_vga_hsync, - vga_vsync => sys_vga_vsync - ); - -inst_ac97_wb : entity work.ac97_wb - GENERIC MAP - ( - fifo_depth => 8 - ) - PORT MAP - ( - -- J-Bus domain - CLK_I => CLK_O, - RST_I => RST_O, - CYC_I => CYC_I_ac97, - STB_I => STB_O, - WE_I => WE_O, - ACK_O => ACK_O_ac97, - SRDY_O => SRDY_O_ac97, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => MDAT_O(31 downto 0), - DAT_O => SDAT_O_ac97, - INT_O => INT_O_ac97, - - -- AC97 domain - ac97_sdata_in => sys_ac97_sdata_in, - ac97_bit_clk => sys_ac97_bit_clk, - ac97_reset_n => ac97_rstn, - ac97_sdata_out => sys_ac97_sdata_out, - ac97_ssync => sys_ac97_ssync - ); - -inst_ps2_wb_0: entity work.ps2_wb - GENERIC MAP - ( - f_sys_clk => sys_freq_in - ) - PORT MAP - ( - CLK_I => CLK_O, - RST_I => RST_O, - CYC_I => CYC_I_ps2_0, - STB_I => STB_O, - SEL_I => SEL_O(3 downto 0), - WE_I => WE_O, - ACK_O => ACK_O_ps2_0, - SRDY_O => SRDY_O_ps2_0, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => MDAT_O(31 downto 0), - DAT_O => SDAT_O_ps2_0, - INT_O => INT_O_ps2_0, - clk_rx => ps2_0_clk_rx, - data_rx => ps2_0_data_rx, - clk_tx => ps2_0_clk_tx, - data_tx => ps2_0_data_tx - ); - -inst_ps2_phy_0: entity work.ps2_phy - PORT MAP - ( - rst => RST_O, - clk => CLK_O, - ps2_clk => sys_ps2_0_clk, - ps2_data => sys_ps2_0_data, - rx_clk => ps2_0_clk_rx, - rx_data => ps2_0_data_rx, - tx_clk => ps2_0_clk_tx, - tx_data => ps2_0_data_tx - ); - -inst_ps2_wb_1: entity work.ps2_wb - GENERIC MAP - ( - f_sys_clk => sys_freq_in - ) - PORT MAP - ( - CLK_I => CLK_O, - RST_I => RST_O, - CYC_I => CYC_I_ps2_1, - STB_I => STB_O, - SEL_I => SEL_O(3 downto 0), - WE_I => WE_O, - ACK_O => ACK_O_ps2_1, - SRDY_O => SRDY_O_ps2_1, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => MDAT_O(31 downto 0), - DAT_O => SDAT_O_ps2_1, - INT_O => INT_O_ps2_1, - clk_rx => ps2_1_clk_rx, - data_rx => ps2_1_data_rx, - clk_tx => ps2_1_clk_tx, - data_tx => ps2_1_data_tx - ); - -inst_ps2_phy_1: entity work.ps2_phy - PORT MAP - ( - rst => RST_O, - clk => CLK_O, - ps2_clk => sys_ps2_1_clk, - ps2_data => sys_ps2_1_data, - rx_clk => ps2_1_clk_rx, - rx_data => ps2_1_data_rx, - tx_clk => ps2_1_clk_tx, - tx_data => ps2_1_data_tx - ); - -inst_emac_top_jb : entity work.emac_top_jb - PORT MAP - ( - CLK_I => CLK_O, - RST_I => RST_O, - INT_O => INT_O_emac, - CYC_I => CYC_I_emac, - STB_I => STB_O, - SEL_I => SEL_O(3 downto 0), - WE_I => WE_O, - ACK_O => ACK_O_emac, - SRDY_O => SRDY_O_emac, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => MDAT_O(31 downto 0), - DAT_O => SDAT_O_emac, - mii_rx_clk => sys_phy_rx_clk, - mii_rx_dv => sys_phy_rx_dv, - mii_rx_er => sys_phy_rx_er, - mii_rx => sys_phy_rx, - mii_tx_clk => sys_phy_tx_clk, - mii_tx_en => sys_phy_tx_en, - mii_tx_er => sys_phy_tx_er, - mii_tx => sys_phy_tx, - mii_gtx_clk => sys_phy_gtx_clk, - mii_crs => sys_phy_crs, - mii_col => sys_phy_col - - ); - - ------------------------------------------------------------------ -END; diff --git a/projects/mips_sys/src/mips_sys_sim.vhd b/projects/mips_sys/src/mips_sys_sim.vhd deleted file mode 100644 index 3e9ac87..0000000 --- a/projects/mips_sys/src/mips_sys_sim.vhd +++ /dev/null @@ -1,1049 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: system test using Xilinx ML-402 - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -Library UNISIM; -use UNISIM.vcomponents.all; - -library work; -use work.mips_types.all; -use work.sdram_config.all; -use work.sdram_types.all; -use work.vga_types.all; -use work.async_types.all; -use work.async_defs.all; - - -ENTITY mips_sys IS -GENERIC -( - sys_freq_in : real := 100.0; - cpu_freq : real := 100.0; - sdram_phaseshift : integer := 0; - tsvga : vga_timespec_t := ts_vga_800_600_72 - -); -PORT -( - sys_rst_n_in : in std_logic; - sys_clk_in : in std_logic; - - -- Buttons and LEDs - sys_btn : in unsigned(4 downto 0); - sys_dip : in unsigned(7 downto 0); - sys_led : out unsigned(8 downto 0); - - -- UART - sys_uart0_rx : in std_logic; - sys_uart0_tx : out std_logic; - sys_uart1_rx : in std_logic; - sys_uart1_tx : out std_logic; - sys_uart2_rx : in std_logic; - sys_uart2_tx : out std_logic; - - -- LCD - sys_lcd_d : inout unsigned(3 downto 0); - sys_lcd_e : out std_logic; - sys_lcd_rs : out std_logic; - sys_lcd_rw : out std_logic; - - -- DDR SDRAM - sys_sdr_clk_p : out std_logic; -- ddr_sdram_clock - sys_sdr_clk_n : out std_logic; -- /ddr_sdram_clock - sys_sdr_cke_q : out std_logic; -- clock enable - sys_sdr_cs_qn : out std_logic; -- /chip select - sys_sdr_ras_qn : out std_logic; -- /ras - sys_sdr_cas_qn : out std_logic; -- /cas - sys_sdr_we_qn : out std_logic; -- /write enable - sys_sdr_dm_q : out unsigned(DDR_DM_WIDTH-1 downto 0); -- data mask bits, set to "00" - sys_sdr_dqs_q : inout unsigned(DDR_DQS_WIDTH-1 downto 0); -- data strobe, only for write - sys_sdr_ba_q : out unsigned(DDR_BANK_WIDTH-1 downto 0); -- bank select - sys_sdr_a_q : out unsigned(DDR_ADDR_WIDTH-1 downto 0); -- address bus - sys_sdr_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus - sys_sdr_clk_fb : in std_logic; - - -- VGA - sys_vga_clk : out std_logic; - sys_vga_red : out unsigned(7 downto 0); - sys_vga_green : out unsigned(7 downto 0); - sys_vga_blue : out unsigned(7 downto 0); - sys_vga_blank_n : out std_logic; - sys_vga_sync_n : out std_logic; - sys_vga_hsync : out std_logic; - sys_vga_vsync : out std_logic; - - sys_usb_d : inout unsigned(15 downto 0); - sys_usb_a : out unsigned(1 downto 0); - sys_usb_csn : out std_logic; - sys_usb_wrn : out std_logic; - sys_usb_rdn : out std_logic; - sys_usb_rstn : out std_logic; - sys_usb_int : in std_logic; - - sys_flash_ssram_d : inout unsigned(31 downto 0); - sys_flash_ssram_a : out unsigned(24 downto 0); - sys_flash_ce : out std_logic; - sys_flash_ssram_we_n : out std_logic; - sys_flash_ssram_oe_n : out std_logic; - sys_flash_ac97_rstn : out std_logic; - sys_flash_byten : out std_logic; - - sys_ssram_clk : out std_logic; - sys_ssram_clk_fb : in std_logic; - sys_ssram_cke_n : out std_logic; - sys_ssram_ce_n : out std_logic; - sys_ssram_bw_n : out unsigned(3 downto 0); - sys_ssram_dp : inout unsigned(3 downto 0); - sys_ssram_adv : out std_logic; - sys_ssram_mode : out std_logic; - sys_ssram_zz : out std_logic; - - sys_ac97_sdata_in : in std_logic; - sys_ac97_bit_clk : in std_logic; - sys_ac97_sdata_out : out std_logic; - sys_ac97_ssync : out std_logic; - - sys_ps2_clk : inout std_logic; - sys_ps2_data : inout std_logic; - - sys_phy_rstn : out std_logic; - sys_phy_mdc : out std_logic; - sys_phy_mdio : inout std_logic; - sys_phy_int : in std_logic; - - sys_phy_rx_clk : in STD_LOGIC; - sys_phy_rx_dv : in STD_LOGIC; - sys_phy_rx_er : in STD_LOGIC; - sys_phy_rx : in unsigned(7 downto 0); - sys_phy_tx_clk : in STD_LOGIC; - sys_phy_tx_en : out STD_LOGIC; - sys_phy_tx_er : out STD_LOGIC; - sys_phy_tx : out unsigned(7 downto 0); - sys_phy_gtx_clk : out STD_LOGIC; - sys_phy_crs : in STD_LOGIC; - sys_phy_col : in STD_LOGIC; - - sys_error : out unsigned(1 downto 0) -- indicates Errors - -); --- attribute BUFFER_TYPE : string; --- attribute BUFFER_TYPE of sys_clk_in : signal is "BUFG"; --- attribute BUFFER_TYPE of sys_sdr_dcm_clk_fb : signal is "BUFG"; - -END mips_sys; - -ARCHITECTURE behavior OF mips_sys IS - - signal cpu_clk : std_logic; - signal nmi : std_logic; - signal eb : std_logic; - signal sdram_clk0 : std_logic; - signal sdram_clk270 : std_logic; - signal sdram_clk270var : std_logic; - signal vga_clk : std_logic; - signal vga_ce : std_logic; - signal rst_in : std_logic; - signal int_timer : std_logic; - signal int_uart0 : std_logic; - signal int_uart1 : std_logic; - signal int_uart2 : std_logic; - signal locked : std_logic; - signal ac97_rstn : std_logic; - signal flash_rstn : std_logic; - signal ADDR_I_usb : unsigned(31 downto 0); - signal ADDR_I_ssram : unsigned(31 downto 0); - signal ssram_clk : std_logic; - signal ssram_a : unsigned(24 downto 0); - signal ssram_do : unsigned(31 downto 0); - signal ssram_oe_n : std_logic; - signal ssram_we_n : std_logic; - signal ssram_d_drv : std_logic; - signal ssram_bsy : std_logic; - signal flash_a : unsigned(24 downto 0); - signal flash_do : unsigned(31 downto 0); - signal flash_oe_n : std_logic; - signal flash_we_n : std_logic; - signal flash_d_drv : std_logic; - signal flash_bsy : std_logic; - signal flash_page_mode_en : std_logic; - - signal ps2_clk_rx : std_logic; - signal ps2_data_rx : std_logic; - signal ps2_clk_tx : std_logic; - signal ps2_data_tx : std_logic; - - -- Arbiter - constant ARB_MAX_MASTER : natural := 2; - signal arb_idx : natural range 0 to ARB_MAX_MASTER-1; - signal arb_req : unsigned (ARB_MAX_MASTER-1 downto 0); - signal arb_gnt : unsigned (ARB_MAX_MASTER-1 downto 0); - - -- J-Bus signals - signal CLK_O : std_logic; - signal RST_O : std_logic; - signal INT : unsigned(5 downto 0); - signal MDAT_I : word_t; - signal MDAT_O : word_t; - signal ADDR_O : word_t; - signal SEL_O : unsigned(3 downto 0); - signal WE_O : std_logic; - signal CYC_O : std_logic; - signal STB_O : std_logic; - signal ACK_I : std_logic; - signal SRDY_I : std_logic; - signal MRDY_O : std_logic; - - -- CPU Master - signal MRDY_O_cpu : std_logic; - signal MDAT_O_cpu : word_t; - signal ADDR_O_cpu : word_t; - signal SEL_O_cpu : unsigned(3 downto 0); - signal WE_O_cpu : std_logic; - signal CYC_O_cpu : std_logic; - signal STB_O_cpu : std_logic; - signal SRDY_I_cpu : std_logic; - signal ACK_I_cpu : std_logic; - - -- VGA Master - signal MRDY_O_vga : std_logic; - signal ADDR_O_vga : word_t; - signal SEL_O_vga : unsigned(7 downto 0); - signal WE_O_vga : std_logic; - signal CYC_O_vga : std_logic; - signal STB_O_vga : std_logic; - signal SRDY_I_vga : std_logic; - signal ACK_I_vga : std_logic; - signal MDAT_I_vga : unsigned(63 downto 0); - signal MDAT_O_vga : unsigned(63 downto 0); - - -- Slaves - signal CYC_I_flash : std_logic; - signal ACK_O_flash : std_logic; - signal SRDY_O_flash : std_logic; - signal SDAT_O_flash : unsigned(31 downto 0); - - signal CYC_I_usb : std_logic; - signal ACK_O_usb : std_logic; - signal SRDY_O_usb : std_logic; - signal SDAT_O_usb : unsigned(31 downto 0); - - signal CYC_I_sdram : std_logic; - signal ACK_O_sdram : std_logic; - signal SRDY_O_sdram : std_logic; - signal SDAT_O_sdram : unsigned(63 downto 0); - signal SDAT_I_sdram : unsigned(63 downto 0); - signal SEL_I_sdram : unsigned(7 downto 0); - - signal CYC_I_rom : std_logic; - signal ACK_O_rom : std_logic; - signal SRDY_O_rom : std_logic; - signal SDAT_O_rom : unsigned(31 downto 0); - - signal CYC_I_gpio : std_logic; - signal ACK_O_gpio : std_logic; - signal SRDY_O_gpio : std_logic; - signal SDAT_O_gpio : unsigned(31 downto 0); - - signal CYC_I_uart0 : std_logic; - signal ACK_O_uart0 : std_logic; - signal SRDY_O_uart0 : std_logic; - signal SDAT_O_uart0 : unsigned(31 downto 0); - signal CYC_I_uart1 : std_logic; - signal ACK_O_uart1 : std_logic; - signal SRDY_O_uart1 : std_logic; - signal SDAT_O_uart1 : unsigned(31 downto 0); - signal CYC_I_uart2 : std_logic; - signal ACK_O_uart2 : std_logic; - signal SRDY_O_uart2 : std_logic; - signal SDAT_O_uart2 : unsigned(31 downto 0); - - signal CYC_I_vga : std_logic; - signal ACK_O_vga : std_logic; - signal SRDY_O_vga : std_logic; - signal SDAT_O_vga : unsigned(31 downto 0); - - signal CYC_I_ssram : std_logic; - signal ACK_O_ssram : std_logic; - signal SRDY_O_ssram : std_logic; - signal SDAT_O_ssram : unsigned(31 downto 0); - - signal INT_O_ac97 : std_logic; - signal CYC_I_ac97 : std_logic; - signal ACK_O_ac97 : std_logic; - signal SRDY_O_ac97 : std_logic; - signal SDAT_O_ac97 : unsigned(31 downto 0); - - signal INT_O_ps2 : std_logic; - signal CYC_I_ps2 : std_logic; - signal ACK_O_ps2 : std_logic; - signal SRDY_O_ps2 : std_logic; - signal SDAT_O_ps2 : unsigned(31 downto 0); - - signal INT_O_emac : std_logic; - signal CYC_I_emac : std_logic; - signal ACK_O_emac : std_logic; - signal SRDY_O_emac : std_logic; - signal SDAT_O_emac : unsigned(31 downto 0); - - signal gpi_0 : unsigned(31 downto 0); - signal gpo_0 : unsigned(31 downto 0); - - signal ac97_inten : std_logic; - signal usb_inten : std_logic; - signal phy_inten : std_logic; - - signal debug : chip_debug_t; - - -- DDR SDRAM - constant BURST_LEN : natural := 2; - constant topad : time := 3 ns; - constant vga_freq : real := real(tsvga.f_pxl_clk)/1.0E6; - --- attribute rom_style: string; --- attribute rom_style of cmd_fifo_dout: signal is "DISTRIBUTED"; --- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED"; --- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED"; - - type mem_area_t is (mem_dead, mem_flash, mem_ssram, mem_usb, mem_rom, mem_gpio, mem_uart0, mem_uart1, mem_uart2, mem_uart, mem_sdram, mem_vga, mem_ac97, mem_emac); - signal mem_area : mem_area_t; - -BEGIN - - ------------------------------------ - -- GPIO_0 bits used for - -- 8.. 0 = O: LED 8..0 - -- 11.. 9 = free - -- 12 = O: USB RST - -- 13 = O: USB INTEN - -- 14 = free - -- 15 = O: AC97 INTEN - -- 32..16 = I: DIP 7..0 - -- 28..24 = I: BTN 4..0 - -- 29 = O: PHY RESET - -- 30 = O: PHY MDC - -- 31 = IO: PHY MDIO - ------------------------------------ - gpi_0(28 downto 24) <= sys_btn; - gpi_0(23 downto 16) <= sys_dip; - gpi_0(31) <= sys_phy_mdio; - - sys_led <= gpo_0(8 downto 0); - sys_usb_rstn <= not gpo_0(12); - usb_inten <= gpo_0(13); - phy_inten <= gpo_0(14); - ac97_inten <= gpo_0(15); - sys_phy_rstn <= not gpo_0(29); - sys_phy_mdc <= gpo_0(30); - sys_phy_mdio <= gpo_0(31); - - eb <= sys_dip(7); - sys_error(0) <= debug.imem_err; - sys_error(1) <= debug.dmem_err; - nmi <= not sys_rst_n_in; - rst_in <= not sys_rst_n_in and sys_btn(0) and sys_btn(2); - sys_flash_byten <= '1'; - ADDR_I_usb <= X"0000000" & "00" & ADDR_O(3 downto 2); - ADDR_I_ssram <= ("0000000000000" & ADDR_O(19 downto 2)) & '0'; - - SDAT_I_sdram <= MDAT_O & MDAT_O; - SEL_I_sdram <= "0000" & SEL_O; - - sys_flash_ac97_rstn <= ac97_rstn and flash_rstn; - vga_ce <= not RST_O; - -sys_flash_ssram_out: - process(CLK_O) - begin - if rising_edge(CLK_O) then - sys_flash_ssram_d <= (others => 'Z') after topad; - sys_flash_ssram_oe_n <= '1'; - sys_flash_ssram_we_n <= '1'; - if flash_bsy = '1' then - sys_flash_ssram_oe_n <= flash_oe_n; - sys_flash_ssram_we_n <= flash_we_n; - sys_flash_ssram_a <= ('0' & flash_a(24 downto 2) & '0') after topad; - if flash_d_drv = '1' then - sys_flash_ssram_d <= flash_do after topad; - end if; - elsif ssram_bsy = '1' then - sys_flash_ssram_oe_n <= ssram_oe_n; - sys_flash_ssram_we_n <= ssram_we_n; - sys_flash_ssram_a <= ssram_a after topad; - if ssram_d_drv = '1' then - sys_flash_ssram_d <= ssram_do after topad; - end if; - end if; - end if; - end process; - - --------------------------------------------------------------- - -- Arbiter - MRDY_O <= MRDY_O_cpu when arb_gnt(0) = '1' else MRDY_O_vga when arb_gnt(1) = '1' else '0'; - MDAT_O <= MDAT_O_cpu when arb_gnt(0) = '1' else MDAT_O_vga(31 downto 0) when arb_gnt(1) = '1' else (others => '0'); - ADDR_O <= ADDR_O_cpu when arb_gnt(0) = '1' else ADDR_O_vga when arb_gnt(1) = '1' else (others => '0'); - SEL_O <= SEL_O_cpu when arb_gnt(0) = '1' else SEL_O_vga(3 downto 0) when arb_gnt(1) = '1' else (others => '0'); - WE_O <= WE_O_cpu when arb_gnt(0) = '1' else WE_O_vga when arb_gnt(1) = '1' else '0'; - CYC_O <= CYC_O_cpu when arb_gnt(0) = '1' else CYC_O_vga when arb_gnt(1) = '1' else '0'; - STB_O <= STB_O_cpu when arb_gnt(0) = '1' else STB_O_vga when arb_gnt(1) = '1' else '0'; - SRDY_I_cpu <= SRDY_I and arb_gnt(0); - SRDY_I_vga <= SRDY_I and arb_gnt(1); - ACK_I_cpu <= ACK_I and arb_gnt(0); - ACK_I_vga <= ACK_I and arb_gnt(1); - - arb_req(0) <= CYC_O_cpu; - arb_req(1) <= CYC_O_vga; - - MDAT_I_vga <= SDAT_O_sdram(63 downto 32) & MDAT_I; - -arbiter_proc: - process(CLK_O) - begin - if rising_edge(CLK_O) then - if RST_O = '1' then - arb_gnt <= (others => '0'); - arb_idx <= 0; - elsif arb_req(arb_idx) = '0' then - if arb_idx /= ARB_MAX_MASTER-1 then - arb_idx <= arb_idx + 1; - else - arb_idx <= 0; - end if; - else - arb_gnt <= (others => '0'); - arb_gnt(arb_idx) <= '1'; - end if; - end if; - end process; - -int_sample: - process(CLK_O) - begin - if rising_edge(CLK_O) then - INT <= int_timer & (INT_O_ps2 or INT_O_emac) & (ac97_inten and INT_O_ac97) & (usb_inten and sys_usb_int) & (int_uart0 or int_uart1 or int_uart2) & sys_btn(4); - end if; - end process; - -mem_mux: - process(ADDR_O) - begin - mem_area <= mem_dead; - flash_page_mode_en <= '0'; - if ADDR_O(31 downto 28) = X"0" then - mem_area <= mem_flash; - flash_page_mode_en <= '1'; - elsif ADDR_O(31 downto 28) = X"1" then - mem_area <= mem_emac; - elsif ADDR_O(31 downto 28) = X"A" then - if ADDR_O(27 downto 26) = "00" then - if ADDR_O(18 downto 16) = "000" then - mem_area <= mem_gpio; - elsif ADDR_O(18 downto 16) = "001" then - if ADDR_O(9 downto 8) = "00" then - mem_area <= mem_uart0; - elsif ADDR_O(9 downto 8) = "01" then - mem_area <= mem_uart1; - elsif ADDR_O(9 downto 8) = "10" then - mem_area <= mem_uart2; - end if; - elsif ADDR_O(18 downto 16) = "010" then - mem_area <= mem_usb; - elsif ADDR_O(18 downto 16) = "011" then - mem_area <= mem_vga; - elsif ADDR_O(18 downto 16) = "100" then - mem_area <= mem_ac97; - elsif ADDR_O(18 downto 16) = "101" then - mem_area <= mem_emac; - end if; - elsif ADDR_O(27 downto 26) = "01" then - mem_area <= mem_flash; - elsif ADDR_O(27 downto 26) = "10" then - mem_area <= mem_ssram; - end if; - elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then - mem_area <= mem_rom; - elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then - mem_area <= mem_sdram; - end if; - end process; - -signal_mux: - process(mem_area, CYC_O) - begin - - CYC_I_uart0 <= '0'; - CYC_I_uart1 <= '0'; - CYC_I_uart2 <= '0'; - CYC_I_gpio <= '0'; - CYC_I_flash <= '0'; - CYC_I_usb <= '0'; - CYC_I_rom <= '0'; - CYC_I_sdram <= '0'; - CYC_I_vga <= '0'; - CYC_I_ssram <= '0'; - CYC_I_ac97 <= '0'; - CYC_I_emac <= '0'; - - case mem_area is - - when mem_gpio => - CYC_I_gpio <= CYC_O; - - when mem_uart0 => - CYC_I_uart0 <= CYC_O; - - when mem_uart1 => - CYC_I_uart1 <= CYC_O; - - when mem_uart2 => - CYC_I_uart2 <= CYC_O; - - when mem_flash => - CYC_I_flash <= CYC_O; - - when mem_usb => - CYC_I_usb <= CYC_O; - - when mem_rom => - CYC_I_rom <= CYC_O; - - when mem_sdram => - CYC_I_sdram <= CYC_O; - - when mem_vga => - CYC_I_vga <= CYC_O; - - when mem_ac97 => - CYC_I_ac97 <= CYC_O; - - when mem_emac => - CYC_I_emac <= CYC_O; - - when mem_ssram => - CYC_I_ssram <= CYC_O; - - when others => null; - - end case; - - end process; - ------------------------------------------------------------------- - SRDY_I <= SRDY_O_flash or SRDY_O_ssram or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart0 or SRDY_O_uart1 or SRDY_O_uart2 or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97 or SRDY_O_emac; - ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ssram or ACK_O_rom or ACK_O_uart0 or ACK_O_uart1 or ACK_O_uart2 or ACK_O_gpio or ACK_O_vga or ACK_O_ac97 or ACK_O_emac; - MDAT_I <= SDAT_O_ssram when CYC_I_ssram = '1' else - SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else - SDAT_O_rom when CYC_I_rom = '1' else - SDAT_O_flash when CYC_I_flash = '1' else - SDAT_O_usb when CYC_I_usb = '1' else - SDAT_O_uart0 when CYC_I_uart0 = '1' else - SDAT_O_uart1 when CYC_I_uart1 = '1' else - SDAT_O_uart2 when CYC_I_uart2 = '1' else - SDAT_O_vga when CYC_I_vga = '1' else - SDAT_O_ac97 when CYC_I_ac97 = '1' else - SDAT_O_emac when CYC_I_emac = '1' else - SDAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF"; - ------------------------------------------------------------------- -inst_mips_top: entity work.mips_top - PORT MAP - ( - debug => debug, - eb => eb, - nmi => nmi, - cpu_clk => cpu_clk, - RST_I => RST_O, - CLK_I => CLK_O, - ACK_I => ACK_I_cpu, - SRDY_I => SRDY_I_cpu, - MRDY_O => MRDY_O_cpu, - CYC_O => CYC_O_cpu, - STB_O => STB_O_cpu, - WE_O => WE_O_cpu, - SEL_O => SEL_O_cpu, - DAT_I => MDAT_I, - DAT_O => MDAT_O_cpu, - ADDR_O => ADDR_O_cpu, - INT => INT - ); - -inst_rom_wb : entity work.rom_wb - PORT MAP - ( - CLK_I => CLK_O, - RST_I => RST_O, - CYC_I => CYC_I_rom, - STB_I => STB_O, - WE_I => WE_O, - ACK_O => ACK_O_rom, - MRDY_I => MRDY_O, - SRDY_O => SRDY_O_rom, - ADDR_I => ADDR_O, - DAT_O => SDAT_O_rom - ); - - -inst_lcd_port: entity work.lcd_port - PORT MAP - ( - clk => CLK_O, - rst => RST_O, - we => '0', - din => X"00", - dout => open, - lcd_d => sys_lcd_d, - lcd_e => sys_lcd_e, - lcd_rs => sys_lcd_rs, - lcd_rw => sys_lcd_rw - ); - -inst_gpio_wb : entity work.gpio_wb - GENERIC MAP - ( - f_sysclk => sys_freq_in - ) - PORT MAP - ( - CLK_I => CLK_O, - RST_I => RST_O, - CYC_I => CYC_I_gpio, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_O_gpio, - SRDY_O => SRDY_O_gpio, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => MDAT_O, - DAT_O => SDAT_O_gpio, - INT_TIM_O => int_timer, - - sys_gpi_0 => gpi_0, - sys_gpo_0 => gpo_0 - ); - -inst_flash_port : entity work.flash_port_wb - GENERIC MAP - ( - f_sysclk => sys_freq_in, - addr_width => 25, - data_width => 32, - async_timespec => ts_flash - ) - PORT MAP - ( - CLK_I => CLK_O, - RST_I => RST_O, - CYC_I => CYC_I_flash, - STB_I => STB_O, - WE_I => WE_O, - ACK_O => ACK_O_flash, - SRDY_O => SRDY_O_flash, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => MDAT_O, - DAT_O => SDAT_O_flash, - port_bsyo => flash_bsy, - port_bsyi => ssram_bsy, - port_a => flash_a, - port_di => sys_flash_ssram_d, - port_do => flash_do, - port_d_drv => flash_d_drv, - port_wr => flash_we_n, - port_rd => flash_oe_n, - flash_cs => sys_flash_ce, - flash_rst => flash_rstn - ); - -inst_usb_port : entity work.async_port_wb - GENERIC MAP - ( - f_sysclk => sys_freq_in, - addr_width => 2, - data_width => 16, - byte_sel_width => 1, - async_timespec => ts_usb - ) - PORT MAP - ( - CLK_I => CLK_O, - RST_I => RST_O, - CYC_I => CYC_I_usb, - STB_I => STB_O, - WE_I => WE_O, - ACK_O => ACK_O_usb, - SRDY_O => SRDY_O_usb, - MRDY_I => MRDY_O, - SEL_I => SEL_O, - ADDR_I => ADDR_I_usb, - DAT_I => MDAT_O, - DAT_O => SDAT_O_usb, - page_mode_en => '0', - async_a => sys_usb_a, - async_d => sys_usb_d, - async_cs => sys_usb_csn, - async_wr => sys_usb_wrn, - async_rd => sys_usb_rdn, - async_be => open, - async_rst => open - ); - -inst_uart_wb_0 : entity work.uart_wb - GENERIC MAP - ( - simulate_tx => true - ) - PORT MAP - ( - CLK_I => CLK_O, - RST_I => RST_O, - CYC_I => CYC_I_uart0, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_O_uart0, - SRDY_O => SRDY_O_uart0, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => MDAT_O, - DAT_O => SDAT_O_uart0, - INT_O => int_uart0, - ser_rx => sys_uart0_rx, - ser_tx => sys_uart0_tx - ); - -inst_uart_wb_1 : entity work.uart_wb - GENERIC MAP - ( - simulate_tx => true - ) - PORT MAP - ( - CLK_I => CLK_O, - RST_I => RST_O, - CYC_I => CYC_I_uart1, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_O_uart1, - SRDY_O => SRDY_O_uart1, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => MDAT_O, - DAT_O => SDAT_O_uart1, - INT_O => int_uart1, - ser_rx => sys_uart1_rx, - ser_tx => sys_uart1_tx - ); - -inst_uart_wb_2 : entity work.uart_wb - GENERIC MAP - ( - simulate_tx => true - ) - PORT MAP - ( - CLK_I => CLK_O, - RST_I => RST_O, - CYC_I => CYC_I_uart2, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_O_uart2, - SRDY_O => SRDY_O_uart2, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => MDAT_O, - DAT_O => SDAT_O_uart2, - INT_O => int_uart2, - ser_rx => sys_uart2_rx, - ser_tx => sys_uart2_tx - ); -inst_ssram_port_wb : entity work.ssram_port_wb - GENERIC MAP - ( - addr_width => 25, - data_width => 32, - parity_width => 4 - ) - PORT MAP - ( - -- J-Bus domain - RST_I => RST_O, - CLK_I => CLK_O, - CYC_I => CYC_I_ssram, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_O_ssram, - SRDY_O => SRDY_O_ssram, - MRDY_I => MRDY_O, - ADDR_I => ADDR_I_ssram, - DAT_I => MDAT_O, - DAT_O => SDAT_O_ssram, - - -- Sync SRAM domain - ssram_clk_o => sys_ssram_clk, - ssram_clk_fb => sys_ssram_clk_fb, - ssram_cke_n => sys_ssram_cke_n, - ssram_ce_n => sys_ssram_ce_n, - port_bsyo => ssram_bsy, - port_bsyi => flash_bsy, - port_di => sys_flash_ssram_d, - port_do => ssram_do, - port_d_drv => ssram_d_drv, - port_wr => ssram_we_n, - port_rd => ssram_oe_n, - port_a => ssram_a, - ssram_adv => sys_ssram_adv, - ssram_mode => sys_ssram_mode, - ssram_zz => sys_ssram_zz, - ssram_dp => sys_ssram_dp, - ssram_bw_n => sys_ssram_bw_n - ); - -inst_clockgen : entity work.clockgen - GENERIC MAP - ( - clk_in_freq => sys_freq_in, - cpu_clk_out_freq => cpu_freq, - vga_clk_out_freq => vga_freq, - sdr0_clk_out_phaseshift => 0, - sdr1_clk_out_phaseshift => 0 - ) - PORT MAP - ( - -- Clocks and Reset - rst_in => rst_in, -- external async reset, low active - clk_in => sys_clk_in, -- system clock (e.g. 100MHz), from board - sys_rst_out => RST_O, - sys_clk_out => CLK_O, - vga_clk_out => vga_clk, - cpu_clk_out => cpu_clk, - sdr0_clk_fb_in => sys_sdr_clk_fb, -- feedback clock - sdr0_clk0_out => sdram_clk0, -- System clock #0, dcm#0 output 0° - sdr0_clk270_out => sdram_clk270, -- System clock #0, dcm#0 output 270° - sdr1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0° - sdr1_clk270_out => sdram_clk270var -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270° - ); - - -inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb - GENERIC MAP - ( - BL => BURST_LEN, - f_sysclk => sys_freq_in, - f_sdrclk => sys_freq_in, - fifo_depth => 5 - ) - PORT MAP - ( - RST_I => RST_O, - CLK_I => CLK_O, - - SDRAM_CLK0_I => sdram_clk0, - SDRAM_CLK270_I => sdram_clk270, - SDRAM_CLK270VAR_I => sdram_clk270var, - - CYC_I => CYC_I_sdram, - STB_I => STB_O, - SEL_I => SEL_I_sdram, - WE_I => WE_O, - ACK_O => ACK_O_sdram, - MRDY_I => MRDY_O, - SRDY_O => SRDY_O_sdram, - ADDR_I => ADDR_O, - DAT_I => SDAT_I_sdram, - DAT_O => SDAT_O_sdram, - - -- SDRAM signals - sd_clk_p => sys_sdr_clk_p, - sd_clk_n => sys_sdr_clk_n, - sd_cke => sys_sdr_cke_q, - sd_cs_n => sys_sdr_cs_qn, - sd_cas_n => sys_sdr_cas_qn, - sd_ras_n => sys_sdr_ras_qn, - sd_we_n => sys_sdr_we_qn, - sd_addr => sys_sdr_a_q, - sd_ba => sys_sdr_ba_q, - sd_dm => sys_sdr_dm_q, - sd_dqs => sys_sdr_dqs_q, - sd_data => sys_sdr_data - - ); - -inst_vga_frontend : entity work.vga_frontend64 - GENERIC MAP - ( - fifo_depth => 2048, - fifo_almost_full_thresh => 1860, - fifo_almost_empty_thresh => 256, - tsvga => tsvga - ) - PORT MAP - ( - -- System signals - RST_I => RST_O, - CLK_I => CLK_O, - - -- JBUS Master signals - CYC_O => CYC_O_vga, - STB_O => STB_O_vga, - WE_O => WE_O_vga, - SEL_O => SEL_O_vga, - ACK_I => ACK_I_vga, - SRDY_I => SRDY_I_vga, - MRDY_O => MRDY_O_vga, - ADDR_O => ADDR_O_vga, - MDAT_I => MDAT_I_vga, - MDAT_O => MDAT_O_vga, - - -- JBUS Slave signals - CYC_I => CYC_I_vga, - STB_I => STB_O, - WE_I => WE_O, - SEL_I => SEL_O, - ACK_O => ACK_O_vga, - SRDY_O => SRDY_O_vga, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - SDAT_I => MDAT_O, - SDAT_O => SDAT_O_vga, - - -- VGA signals - vga_clk_in => vga_clk, - vga_clk_ce => vga_ce, - vga_red => sys_vga_red, - vga_green => sys_vga_green, - vga_blue => sys_vga_blue, - vga_blank_n => sys_vga_blank_n, - vga_sync_n => sys_vga_sync_n, - vga_hsync => sys_vga_hsync, - vga_vsync => sys_vga_vsync - ); - -inst_ac97_wb : entity work.ac97_wb - GENERIC MAP - ( - fifo_depth => 4 - ) - PORT MAP - ( - -- J-Bus domain - CLK_I => CLK_O, - RST_I => RST_O, - CYC_I => CYC_I_ac97, - STB_I => STB_O, - WE_I => WE_O, - ACK_O => ACK_O_ac97, - SRDY_O => SRDY_O_ac97, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => MDAT_O, - DAT_O => SDAT_O_ac97, - INT_O => INT_O_ac97, - - -- AC97 domain - ac97_sdata_in => sys_ac97_sdata_in, - ac97_bit_clk => sys_ac97_bit_clk, - ac97_reset_n => ac97_rstn, - ac97_sdata_out => sys_ac97_sdata_out, - ac97_ssync => sys_ac97_ssync - ); - -inst_ps2_wb: entity work.ps2_wb - GENERIC MAP - ( - f_sys_clk => sys_freq_in - ) - PORT MAP - ( - CLK_I => CLK_O, - RST_I => RST_O, - CYC_I => CYC_I_ps2, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_O_ps2, - SRDY_O => SRDY_O_ps2, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => MDAT_O, - DAT_O => SDAT_O_ps2, - INT_O => INT_O_ps2, - clk_rx => ps2_clk_rx, - data_rx => ps2_data_rx, - clk_tx => ps2_clk_tx, - data_tx => ps2_data_tx - ); - -inst_ps2_phy: entity work.ps2_phy - PORT MAP - ( - rst => RST_O, - clk => CLK_O, - ps2_clk => sys_ps2_clk, - ps2_data => sys_ps2_data, - rx_clk => ps2_clk_rx, - rx_data => ps2_data_rx, - tx_clk => ps2_clk_tx, - tx_data => ps2_data_tx - ); - -inst_emac_jb : entity work.emac_top_jb - PORT MAP - ( - CLK_I => CLK_O, - RST_I => RST_O, - INT_O => INT_O_emac, - CYC_I => CYC_I_emac, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_O_emac, - SRDY_O => SRDY_O_emac, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => MDAT_O, - DAT_O => SDAT_O_emac, - mii_rx_clk => sys_phy_rx_clk, - mii_rx_dv => sys_phy_rx_dv, - mii_rx_er => sys_phy_rx_er, - mii_rx => sys_phy_rx, - mii_tx_clk => sys_phy_tx_clk, - mii_tx_en => sys_phy_tx_en, - mii_tx_er => sys_phy_tx_er, - mii_tx => sys_phy_tx, - mii_gtx_clk => sys_phy_gtx_clk, - mii_crs => sys_phy_crs, - mii_col => sys_phy_col - - ); - - - ------------------------------------------------------------------ -END; diff --git a/projects/mips_sys/src/ram_ld.vhd b/projects/mips_sys/src/ram_ld.vhd deleted file mode 100644 index 17879e1..0000000 --- a/projects/mips_sys/src/ram_ld.vhd +++ /dev/null @@ -1,173 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -ENTITY ram IS - Port - ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - we : in unsigned(3 downto 0); - addr : in unsigned(31 downto 0); - din : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); -END ram; - -ARCHITECTURE behavior OF ram IS - - COMPONENT dpram_2w2r - Generic - ( - addr_width : integer; - data_width : integer - ); - Port - ( - clk_a : in STD_LOGIC; - clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - we_b : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - din_b : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); - END COMPONENT; - - signal jtag_clk : STD_LOGIC; - signal jtag_we : unsigned(3 downto 0); - signal jtag_addr : unsigned (15 downto 0); - signal jtag_dout : unsigned (31 downto 0); - signal jtag_din : unsigned (31 downto 0); - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (47 downto 0); - -BEGIN - -gen_sram: - for i in 0 to 3 generate - begin - inst_dpram_2w2r : dpram_2w2r - GENERIC MAP - ( - addr_width => 11, - data_width => 8 - ) - PORT MAP - ( - clk_a => clk, - en_a => ce, - we_a => we(i), - addr_a => addr(12 downto 2), - din_a => din((i+1)*8-1 downto i*8), - dout_a => dout((i+1)*8-1 downto i*8), - - clk_b => jtag_clk, - en_b => jtag_we(i), - we_b => jtag_we(i), - addr_b => jtag_addr(10 downto 0), - din_b => jtag_din((i+1)*8-1 downto i*8), - dout_b => jtag_dout((i+1)*8-1 downto i*8) - ); - end generate; - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_addr <= user_regi(user_regi'left downto jtag_dout'length); - jtag_din <= user_regi(jtag_dout'length-1 downto 0); - jtag_clk <= bs_update1; - jtag_we <= (3 downto 0 => bs_sel); - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto jtag_dout'length => '0') & jtag_dout; - end if; - end if; - end process; - --------------------------------------------------------------------------- -end behavior; diff --git a/projects/mips_sys/src/ram_sim.vhd b/projects/mips_sys/src/ram_sim.vhd deleted file mode 100644 index 6d26672..0000000 --- a/projects/mips_sys/src/ram_sim.vhd +++ /dev/null @@ -1,88 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY ram IS - Generic - ( - word_addr_width : integer := 6 - ); - Port - ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - we : in unsigned(3 downto 0); - addr : in unsigned(31 downto 0); - din : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); -END ram; - -ARCHITECTURE behavior OF ram IS - - constant depth : natural := 2**word_addr_width; - - type sram_t is array (0 to depth-1) of unsigned(31 downto 0); - - function sram_clear return sram_t is - - variable result : sram_t; - begin - for i in 0 to sram_t'length-1 loop - result(i) := (others => '0'); - end loop; - return result; - end sram_clear; - - signal sram : sram_t := sram_clear; - -BEGIN - - -SRAM_RW: - process(clk) - variable index : natural range 0 to depth-1; - begin - if rising_edge(clk) and ce = '1' then - index := to_integer(addr(word_addr_width+1 downto 2)); - if we(0) = '1' then - sram(index)(7 downto 0) <= din(7 downto 0); - end if; - if we(1) = '1' then - sram(index)(15 downto 8) <= din(15 downto 8); - end if; - if we(2) = '1' then - sram(index)(23 downto 16) <= din(23 downto 16); - end if; - if we(3) = '1' then - sram(index)(31 downto 24) <= din(31 downto 24); - end if; - dout <= sram(index); - end if; - end process; - -end behavior; diff --git a/projects/mips_sys/src/sdram_config.vhd b/projects/mips_sys/src/sdram_config.vhd deleted file mode 100644 index c964e6b..0000000 --- a/projects/mips_sys/src/sdram_config.vhd +++ /dev/null @@ -1,74 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: User SDRAM component adjustments --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -package sdram_config is - - constant DDR_DATA_WIDTH : positive := 32; -- External DDR-SDRAM Module data bus width - constant DDR_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module - constant DDR_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM - constant DDR_ROW_ADDR_WIDTH : positive := 13; -- - constant DDR_COL_ADDR_WIDTH : positive := 9; -- - - constant LMR_REG_BASE : natural := 0; - constant LMR_REG_EXTENDED : natural := 1; - constant LMR_OP_NORMAL : natural := 0; - constant LMR_OP_RES_DLL : natural := 2; - constant LMR_BT_SEQ : natural := 0; - constant LMR_BT_ILVD : natural := 1; - constant LMR_BL2 : natural := 1; - constant LMR_BL4 : natural := 2; - constant LMR_BL8 : natural := 3; - constant LMR_CL2 : natural := 2; - constant LMR_CL3 : natural := 3; - constant LMR_CL2_5 : natural := 6; - - -- DDR SDRAM Hardware defined constants - constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet) - constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet) - constant ENABLE_PRE_ALL : std_logic := '1'; - constant ENABLE_AUTO_PRE : std_logic := '0'; - - -- DDR-SDR TIMING constants ------------------------------------------------------------------ - -- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh - constant REFRESH_INTERVAL : real := 7.8125E3; -- [ns] - - -- These values are for your SDRAM part (see datasheet) - constant TCAS : positive := 2; -- CAS latency [clocks] - constant TRP : real := 20.0; -- precharge command period [ns] - constant TRAS : real := 45.0; -- active to precharge delay [ns] - constant TRFC : real := 75.0; -- auto refresh command period [ns] - constant TMRD : positive := 2; -- load mode register command cylce time [clocks] - constant TRCD : real := 20.0; -- active to read or write delay [ns] - constant TWR : real := 15.0; -- write recovery time [ns] - - constant PWR_UP_WAIT : real := 220.0E3; -- [ns] - - subtype user_tag_t is unsigned(3 downto 0); - - ---------------------------------------------------------------------------------------------- - -end sdram_config; diff --git a/projects/mips_sys/src/sdram_config_sim.vhd b/projects/mips_sys/src/sdram_config_sim.vhd deleted file mode 100644 index 5067520..0000000 --- a/projects/mips_sys/src/sdram_config_sim.vhd +++ /dev/null @@ -1,74 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: User SDRAM component adjustments --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -package sdram_config is - - constant DDR_DATA_WIDTH : positive := 32; -- External DDR-SDRAM Module data bus width - constant DDR_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module - constant DDR_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM - constant DDR_ROW_ADDR_WIDTH : positive := 13; -- - constant DDR_COL_ADDR_WIDTH : positive := 9; -- - - constant LMR_REG_BASE : natural := 0; - constant LMR_REG_EXTENDED : natural := 1; - constant LMR_OP_NORMAL : natural := 0; - constant LMR_OP_RES_DLL : natural := 2; - constant LMR_BT_SEQ : natural := 0; - constant LMR_BT_ILVD : natural := 1; - constant LMR_BL2 : natural := 1; - constant LMR_BL4 : natural := 2; - constant LMR_BL8 : natural := 3; - constant LMR_CL2 : natural := 2; - constant LMR_CL3 : natural := 3; - constant LMR_CL2_5 : natural := 6; - - -- DDR SDRAM Hardware defined constants - constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet) - constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet) - constant ENABLE_PRE_ALL : std_logic := '1'; - constant ENABLE_AUTO_PRE : std_logic := '0'; - - -- DDR-SDR TIMING constants ------------------------------------------------------------------ - -- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh - constant REFRESH_INTERVAL : real := 7.8125E3; -- [ns] - - -- These values are for your SDRAM part (see datasheet) - constant TCAS : positive := 2; -- CAS latency [clocks] - constant TRP : real := 20.0; -- precharge command period [ns] - constant TRAS : real := 45.0; -- active to precharge delay [ns] - constant TRFC : real := 75.0; -- auto refresh command period [ns] - constant TMRD : positive := 2; -- load mode register command cylce time [clocks] - constant TRCD : real := 20.0; -- active to read or write delay [ns] - constant TWR : real := 15.0; -- write recovery time [ns] - - constant PWR_UP_WAIT : real := 22.0E3; -- [ns] - - subtype user_tag_t is unsigned(3 downto 0); - - ---------------------------------------------------------------------------------------------- - -end sdram_config; diff --git a/projects/mips_sys/src/sys_types.vhd b/projects/mips_sys/src/sys_types.vhd deleted file mode 100644 index 2ff4570..0000000 --- a/projects/mips_sys/src/sys_types.vhd +++ /dev/null @@ -1,70 +0,0 @@ -------------------------------------------------------------------------- --- Project: MIPS System controller --- This file: --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -use work.async_types.all; - -package async_defs is - - constant ts_flash : async_timespec_t := - ( - T_leadin => 00.0, - T_pulse_rd => 120.0, - T_pulse_wr => 70.0, - T_leadout => 00.0, - T_release => 40.0, - T_pulse_rst => 80.0, - T_pulse_page_rd => 30.0, - can_page_rd => true, - nbits_page_rd => 4, - pol_cs => '1', - pol_oe => '0', - pol_we => '0', - pol_be => '0', - pol_rst => '0' - ); - - constant ts_usb : async_timespec_t := - ( - T_leadin => 10.0, - T_pulse_rd => 60.0, - T_pulse_wr => 60.0, - T_leadout => 10.0, - T_release => 80.0, - T_pulse_rst => 80.0, - T_pulse_page_rd => 00.0, - can_page_rd => false, - nbits_page_rd => 0, - pol_cs => '0', - pol_oe => '0', - pol_we => '0', - pol_be => '0', - pol_rst => '0' - ); - - ---------------------------------------------------------------------------------------------- - -end async_defs; diff --git a/projects/mips_sys/src/tb_mips_sys.vhd b/projects/mips_sys/src/tb_mips_sys.vhd deleted file mode 100644 index c3a0bca..0000000 --- a/projects/mips_sys/src/tb_mips_sys.vhd +++ /dev/null @@ -1,420 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: testbench for system test using Xilinx ML-402 - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.mips_types.all; -use work.sdram_config.all; -use work.sdram_types.all; -use work.vga_types.all; - -ENTITY tb_mips_sys IS -END tb_mips_sys; - -ARCHITECTURE behavior OF tb_mips_sys IS - - constant CLK_PERIOD : time := 10 ns; - constant AC97_CLK_PERIOD : time := 83 ns; - constant ETH_CLK_PERIOD : time := 7.7 ns; - constant LOOP_BACK_EN : std_logic := '1'; - signal sys_rst_n_in : std_logic := '0'; - signal sys_clk_in : std_logic := '1'; - signal dip : unsigned(7 downto 0) := (others => '0'); - signal btn : unsigned(4 downto 0) := (others => '0'); - signal led : unsigned(8 downto 0); - signal sys_rx : std_logic := '1'; - signal sys_tx : std_logic; - signal sys_rx1 : std_logic := '1'; - signal sys_tx1 : std_logic; - signal sys_rx2 : std_logic := '1'; - signal sys_tx2 : std_logic; - - signal sys_lcd_d : unsigned(3 downto 0); - signal sys_lcd_e : std_logic; - signal sys_lcd_rs : std_logic; - signal sys_lcd_rw : std_logic; - - signal refresh : boolean:= true; - - signal sys_sdr_clk_p : std_logic; -- ddr_sdram_clock - signal sys_sdr_clk_n : std_logic; -- /ddr_sdram_clock - signal sys_sdr_cke_q : std_logic; -- clock enable - signal sys_sdr_cs_qn : std_logic; -- /chip select - signal sys_sdr_ras_qn : std_logic; -- /ras - signal sys_sdr_cas_qn : std_logic; -- /cas - signal sys_sdr_we_qn : std_logic; -- /write enable - signal sys_sdr_dm_q : unsigned(DDR_DM_WIDTH-1 downto 0); -- data mask bits, set to "00" - signal sys_sdr_dqs_q : unsigned(DDR_DQS_WIDTH-1 downto 0); -- data strobe, only for write - signal sys_sdr_ba_q : unsigned(DDR_BANK_WIDTH-1 downto 0); -- bank select - signal sys_sdr_a_q : unsigned(DDR_ADDR_WIDTH-1 downto 0); -- address bus - signal sys_sdr_data : unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus - - signal sys_error : unsigned(1 downto 0); -- indicates DCM Errors - signal sys_sdr_clk_fb : std_logic; - - signal sys_usb_d : unsigned(15 downto 0) := (others => '0'); - signal sys_usb_a : unsigned(1 downto 0); - signal sys_usb_csn : std_logic; - signal sys_usb_wrn : std_logic; - signal sys_usb_rdn : std_logic; - signal sys_usb_rstn : std_logic; - signal sys_usb_int : std_logic := '0'; - - signal sys_flash_ssram_d : word_t; - signal sys_flash_ssram_a : unsigned(24 downto 0); - signal sys_flash_ssram_we_n : std_logic; - signal sys_flash_ssram_oe_n : std_logic; - - signal sys_flash_ce : std_logic; - signal sys_flash_ac97_rstn : std_logic; - signal sys_flash_byten : std_logic; - - signal sys_ssram_clk_fb : std_logic; - signal sys_ssram_clk : std_logic; - signal sys_ssram_cke_n : std_logic; - signal sys_ssram_ce_n : std_logic; - signal sys_ssram_bw_n : unsigned(3 downto 0); - signal sys_ssram_dp : unsigned(3 downto 0); - signal sys_ssram_adv : std_logic; - signal sys_ssram_mode : std_logic; - signal sys_ssram_zz : std_logic; - - SIGNAL sys_ac97_bit_clk : std_logic := '0'; - SIGNAL sys_ac97_sdata_out : std_logic; - SIGNAL sys_ac97_ssync : std_logic; - SIGNAL sys_ac97_sdata_in : std_logic; - - SIGNAL sys_ps2_clk : std_logic := 'H'; - SIGNAL sys_ps2_data : std_logic := 'H'; - - SIGNAL sys_phy_rstn : std_logic; - SIGNAL sys_phy_mdc : std_logic; - SIGNAL sys_phy_mdio : std_logic := 'H'; - SIGNAL sys_phy_int : std_logic := '0'; - - SIGNAL sys_phy_rx_clk : STD_LOGIC := '0'; - SIGNAL sys_phy_rx_dv : STD_LOGIC := '0'; - SIGNAL sys_phy_rx_er : STD_LOGIC := '0'; - SIGNAL sys_phy_rx : unsigned(7 downto 0) := (others => '0'); - SIGNAL sys_phy_tx_clk : STD_LOGIC := '0'; - SIGNAL sys_phy_tx_en : STD_LOGIC; - SIGNAL sys_phy_tx_er : STD_LOGIC; - SIGNAL sys_phy_tx : unsigned(7 downto 0); - SIGNAL sys_phy_gtx_clk : STD_LOGIC; - SIGNAL sys_phy_crs : STD_LOGIC := '0'; - SIGNAL sys_phy_col : STD_LOGIC := '0'; - - signal flash_reg : word_t; - signal eth_tx_reg : unsigned(7 downto 0); - - type flash_data_t is array (natural range 0 to 2**16-1) of word_t; - signal flash_data : flash_data_t; - - signal ac_frame_reg : unsigned(255 downto 0) := (others => '0'); - signal ac_left : unsigned(17 downto 0) := X"0000" & "00"; - signal ac_right : unsigned(17 downto 0) := X"0000" & "01"; - signal ac_synced : std_logic; - -BEGIN - -uut: entity work.mips_sys - GENERIC MAP - ( - sys_freq_in => 100.000, - cpu_freq => 100.000, - sdram_phaseshift => 0, - tsvga => ts_vga_800_600_72 - ) - PORT MAP - ( - sys_rst_n_in => sys_rst_n_in, - sys_clk_in => sys_clk_in, - sys_btn => btn, - sys_dip => dip, - sys_led => led, - - sys_uart0_rx => sys_rx, - sys_uart0_tx => sys_tx, - sys_uart1_rx => sys_rx1, - sys_uart1_tx => sys_tx1, - sys_uart2_rx => sys_rx2, - sys_uart2_tx => sys_tx2, - - sys_lcd_d => sys_lcd_d, - sys_lcd_e => sys_lcd_e, - sys_lcd_rs => sys_lcd_rs, - sys_lcd_rw => sys_lcd_rw, - - sys_sdr_clk_p => sys_sdr_clk_p, - sys_sdr_clk_n => sys_sdr_clk_n, - sys_sdr_cke_q => sys_sdr_cke_q, - sys_sdr_clk_fb => sys_sdr_clk_fb, - sys_sdr_cs_qn => sys_sdr_cs_qn, - sys_sdr_ras_qn => sys_sdr_ras_qn, - sys_sdr_cas_qn => sys_sdr_cas_qn, - sys_sdr_we_qn => sys_sdr_we_qn, - sys_sdr_dm_q => sys_sdr_dm_q, - sys_sdr_dqs_q => sys_sdr_dqs_q, - sys_sdr_ba_q => sys_sdr_ba_q, - sys_sdr_a_q => sys_sdr_a_q, - sys_sdr_data => sys_sdr_data, - - sys_usb_d => sys_usb_d, - sys_usb_a => sys_usb_a, - sys_usb_csn => sys_usb_csn, - sys_usb_wrn => sys_usb_wrn, - sys_usb_rdn => sys_usb_rdn, - sys_usb_rstn => sys_usb_rstn, - sys_usb_int => sys_usb_int, - - sys_flash_ssram_d => sys_flash_ssram_d, - sys_flash_ssram_a => sys_flash_ssram_a, - sys_flash_ssram_we_n => sys_flash_ssram_we_n, - sys_flash_ssram_oe_n => sys_flash_ssram_oe_n, - sys_flash_ce => sys_flash_ce, - sys_flash_ac97_rstn => sys_flash_ac97_rstn, - sys_flash_byten => sys_flash_byten, - - sys_ssram_clk_fb => sys_ssram_clk_fb, - sys_ssram_clk => sys_ssram_clk, - sys_ssram_cke_n => sys_ssram_cke_n, - sys_ssram_ce_n => sys_ssram_ce_n, - sys_ssram_bw_n => sys_ssram_bw_n, - sys_ssram_dp => sys_ssram_dp, - sys_ssram_adv => sys_ssram_adv, - sys_ssram_mode => sys_ssram_mode, - sys_ssram_zz => sys_ssram_zz, - - sys_ac97_bit_clk => sys_ac97_bit_clk, - sys_ac97_sdata_out => sys_ac97_sdata_out, - sys_ac97_ssync => sys_ac97_ssync, - sys_ac97_sdata_in => sys_ac97_sdata_in, - - sys_ps2_clk => sys_ps2_clk, - sys_ps2_data => sys_ps2_data, - - sys_phy_rstn => sys_phy_rstn, - sys_phy_mdc => sys_phy_mdc, - sys_phy_mdio => sys_phy_mdio, - sys_phy_int => sys_phy_int, - - sys_phy_rx_clk => sys_phy_rx_clk, - sys_phy_rx_dv => sys_phy_rx_dv, - sys_phy_rx_er => sys_phy_rx_er, - sys_phy_rx => sys_phy_rx, - sys_phy_tx_clk => sys_phy_tx_clk, - sys_phy_tx_en => sys_phy_tx_en, - sys_phy_tx_er => sys_phy_tx_er, - sys_phy_tx => sys_phy_tx, - sys_phy_gtx_clk => sys_phy_gtx_clk, - sys_phy_crs => sys_phy_crs, - sys_phy_col => sys_phy_col, - - sys_error => sys_error - ); - - sys_phy_rx <= sys_phy_tx when LOOP_BACK_EN = '1' else X"00"; - sys_phy_rx_dv <= sys_phy_tx_en when LOOP_BACK_EN = '1' else '0'; - sys_phy_rx_er <= sys_phy_tx_er when LOOP_BACK_EN = '1' else '0'; - sys_phy_crs <= '0'; - sys_phy_col <= '0'; - -inst_ssram : entity work.cy7c1354 - PORT MAP - ( - Dq => STD_LOGIC_VECTOR(sys_flash_ssram_d), -- Data I/O - Dpq => STD_LOGIC_VECTOR(sys_ssram_dp), -- Data I/O - Addr => STD_LOGIC_VECTOR(sys_flash_ssram_a(18 downto 1)), -- Address - Mode => sys_ssram_mode, -- Burst Mode - Clk => sys_ssram_clk, -- Clk - CEN_n => sys_ssram_cke_n, -- CEN# - AdvLd_n => sys_ssram_adv, -- Adv/Ld# - Bwa_n => sys_ssram_bw_n(0), -- Bwa# - Bwb_n => sys_ssram_bw_n(1), -- BWb# - Bwc_n => sys_ssram_bw_n(2), -- Bwc# - Bwd_n => sys_ssram_bw_n(3), -- BWd# - Rw_n => sys_flash_ssram_we_n, -- RW# - Oe_n => sys_flash_ssram_oe_n, -- OE# - Ce1_n => sys_ssram_ce_n, -- CE1# - Ce2 => '1', -- CE2 - Ce3_n => '0', -- CE3# - Zz => sys_ssram_zz - ); - --- MICRON DDR SDRAM Simulation Model -i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(sys_sdr_data(15 downto 0)), - dqs => std_logic_vector(sys_sdr_dqs_q(1 downto 0)), - addr => std_logic_vector(sys_sdr_a_q), - ba => std_logic_vector(sys_sdr_ba_q), - clk => sys_sdr_clk_p, - clk_n => sys_sdr_clk_n, - cke => sys_sdr_cke_q, - cs_n => sys_sdr_cs_qn, - ras_n => sys_sdr_ras_qn, - cas_n => sys_sdr_cas_qn, - we_n => sys_sdr_we_qn, - dm => std_logic_vector(sys_sdr_dm_q(1 downto 0)) - ); - --- MICRON DDR SDRAM Simulation Model -i_mt46v16m16_1 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(sys_sdr_data(31 downto 16)), - dqs => std_logic_vector(sys_sdr_dqs_q(3 downto 2)), - addr => std_logic_vector(sys_sdr_a_q), - ba => std_logic_vector(sys_sdr_ba_q), - clk => sys_sdr_clk_p, - clk_n => sys_sdr_clk_n, - cke => sys_sdr_cke_q, - cs_n => sys_sdr_cs_qn, - ras_n => sys_sdr_ras_qn, - cas_n => sys_sdr_cas_qn, - we_n => sys_sdr_we_qn, - dm => std_logic_vector(sys_sdr_dm_q(3 downto 2)) - ); - - sys_sdr_clk_fb <= sys_sdr_clk_p after 1300 ps; - sys_ssram_clk_fb <= sys_ssram_clk after 0.5 ns; - - refresh <= true when falling_edge(sys_sdr_ras_qn) and falling_edge(sys_sdr_cas_qn) and sys_sdr_we_qn='1' else false; - - sys_usb_d <= X"1234" after 20 ns when sys_usb_csn = '0' and sys_usb_rdn = '0' else (others => 'Z') after 5 ns; - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - sys_clk_in <= not sys_clk_in; - end process; - -ETH_CLK_GEN: process - begin - wait for ETH_CLK_PERIOD/2; - sys_phy_rx_clk <= not sys_phy_rx_clk; - sys_phy_tx_clk <= not sys_phy_tx_clk; - end process; - -ETH_TX_REGISTER: - PROCESS(sys_phy_tx_clk) - begin - if rising_edge(sys_phy_tx_clk) then - if (sys_phy_tx_en = '1') then - eth_tx_reg <= sys_phy_tx; - end if; - end if; - end process; - - sys_ac97_sdata_in <= ac_frame_reg(ac_frame_reg'left); --sys_ac97_sdata_out; - -ac97_data_gen : - PROCESS(sys_ac97_bit_clk) - begin - if rising_edge(sys_ac97_bit_clk) then - ac_frame_reg <= ac_frame_reg(ac_frame_reg'left-1 downto 0) & '0'; - if sys_flash_ac97_rstn = '0' then - ac_synced <= '0'; - elsif sys_ac97_ssync = '1' then - if ac_synced = '0' then - ac_frame_reg <= X"F800_00000_00000" & ac_left & "00" & ac_right & "00" & X"00000_00000_00000_00000_00000_00000_00000_00000"; - ac_left <= ac_left + 2; - ac_right <= ac_right + 2; - ac_synced <= '1'; - end if; - else - ac_synced <= '0'; - end if; - end if; - END PROCESS; - -ac97_clk_gen : PROCESS - begin - if (sys_flash_ac97_rstn = '0') then - sys_ac97_bit_clk <= '0'; - wait until sys_flash_ac97_rstn = '1'; - wait for 150 us; - end if; - wait for AC97_CLK_PERIOD/2; - sys_ac97_bit_clk <= not sys_ac97_bit_clk; - END PROCESS; - -FLASH_READ: process(sys_rst_n_in, sys_flash_ce, sys_flash_ssram_oe_n, sys_flash_ssram_a) - type file_t is file of integer; - file load_flash : file_t open read_mode is "blittertest_tb.elf.flash.bin"; - variable instr : integer; - variable index : natural; - variable temp : signed(31 downto 0); - begin - if sys_rst_n_in = '0' then - index := 0; - while not endfile(load_flash) loop - read(load_flash, instr); - temp := to_signed(instr, word_t'length); - flash_data(index) <= unsigned(temp); - index := index + 1; - end loop; - else - sys_flash_ssram_d <= (others => 'Z') after 10 ns; - if sys_flash_ssram_oe_n = '0' and sys_flash_ce = '1' then - index := to_integer(sys_flash_ssram_a(24 downto 1)); - sys_flash_ssram_d <= flash_data(index) after 10 ns; - end if; - end if; - end process; - -FLASH_WRITE: process(sys_flash_ce, sys_flash_ssram_we_n, sys_flash_ssram_d) - begin - if rising_edge(sys_flash_ssram_we_n) and sys_flash_ce = '1' then - flash_reg <= sys_flash_ssram_d; - end if; - end process; - -STIMULUS: process - - begin - - dip(7) <= '1'; -- EB - btn(0) <= '1'; - btn(2) <= '1'; - wait for 3*CLK_PERIOD; - sys_rst_n_in <= '1'; - btn(0) <= '0'; - btn(2) <= '0'; - wait for 20000000*CLK_PERIOD; - - loop - wait for 251*CLK_PERIOD; - btn(4) <= '1'; - wait for 311*CLK_PERIOD; - btn(4) <= '0'; - end loop; - wait; - - end process; - -END; diff --git a/projects/mips_sys/tools/insrom.rb b/projects/mips_sys/tools/insrom.rb deleted file mode 100644 index fdbf1ed..0000000 --- a/projects/mips_sys/tools/insrom.rb +++ /dev/null @@ -1,46 +0,0 @@ -#!/usr/bin/env ruby - -# ---------------------------------------------------------------------- -# Project: JIPS, a portable 32-bit RISC CPU written in VHDL -# This file: Insertion of code fragments into templates -# -# Copyright (C) 2008 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -arg = $* -rom_filename = arg[0].to_s -tpl_filename = arg[1].to_s - -subst_pattern = "ROM_INSERT_HERE" - -# -------------------------------------------------------- -# Open file -# -------------------------------------------------------- -romfile = File.open(rom_filename, "r") -tplfile = File.open(tpl_filename, "r") -re = Regexp.new(subst_pattern) - -while (line = tplfile.gets) - puts line - line.scan(re).each do |word| - romfile.each do |raw_line| - puts raw_line - end - end -end diff --git a/projects/mips_sys/tools/irom.vhd.tpl b/projects/mips_sys/tools/irom.vhd.tpl deleted file mode 100644 index 5ffd6d7..0000000 --- a/projects/mips_sys/tools/irom.vhd.tpl +++ /dev/null @@ -1,29 +0,0 @@ -------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - --- ROM_INSERT_HERE - diff --git a/projects/mips_sys/tools/irom_ld.vhd.tpl b/projects/mips_sys/tools/irom_ld.vhd.tpl deleted file mode 100644 index 3bd3afb..0000000 --- a/projects/mips_sys/tools/irom_ld.vhd.tpl +++ /dev/null @@ -1,147 +0,0 @@ -------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); - -END irom; - -ARCHITECTURE loadable OF irom IS - - -- JASM_ROM_INSERT_HERE - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : unsigned (15 downto 0); - signal jtag_ld_dout : unsigned (31 downto 0); - signal jtag_ld_din : unsigned (31 downto 0); - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (47 downto 0); - constant id : unsigned (47 downto 0) := X"DEAD" & X"BEEF" & "X"BABE"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length); - jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk) - begin - if rising_edge(clk) then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/projects/mips_sys/tools/make b/projects/mips_sys/tools/make deleted file mode 100644 index e7f598f..0000000 --- a/projects/mips_sys/tools/make +++ /dev/null @@ -1,50 +0,0 @@ -#!/bin/sh - -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: rom-file generation for cpu_core -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -TARGET=$2 -DSTDIR=$1 - -JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools - -$JASM_HOME/jasm.rb $TARGET.jsm - -irom_tcl_snippet="$TARGET.irom.tcl.snip" -irom_vhdl_snippet="$TARGET.irom.vhdl.snip" -irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip" -xrom_tcl_snippet="$TARGET.xrom.tcl.snip" -xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip" -xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip" - -$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl -$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl - -$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl -$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl - -cat $irom_tcl_snippet > $TARGET.tcl.snip.snip -cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip -$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl - -rm -f *.snip diff --git a/projects/mips_sys/tools/rom.tcl.tpl b/projects/mips_sys/tools/rom.tcl.tpl deleted file mode 100644 index 9f5c0dc..0000000 --- a/projects/mips_sys/tools/rom.tcl.tpl +++ /dev/null @@ -1,61 +0,0 @@ -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: The ROM file for upload to target over JTAG -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -# --------------------------------------------------------------------- -# For Chipscope 9.1 -# --------------------------------------------------------------------- -# Source JTAG/TCL frame work -cd $env(CHIPSCOPE)\\bin\\nt -source csejtag.tcl - -namespace import ::chipscope::* - -# Platform USB Cable -set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"] -# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000" - -# Create session -set handle [::chipscope::csejtag_session create 0] - -# Open JTAG and lock -set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS] -set lock_result [::chipscope::csejtag_target lock $handle 1000] - -set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT] - -# Get Device ID -set devtype "Virtex-4SX" -set devid 2 -set irlength [::chipscope::csejtag_tap get_irlength $handle $devid] -set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid] - -set CSE_OP $CSEJTAG_SHIFT_READWRITE -set CSE_ES $CSEJTAG_RUN_TEST_IDLE - -# Write Program -# JASM_ROM_INSERT_HERE - -::chipscope::csejtag_target unlock $handle -::chipscope::csejtag_target close $handle -::chipscope::csejtag_session destroy $handle -exit diff --git a/projects/mips_sys/tools/src/flashgen.c b/projects/mips_sys/tools/src/flashgen.c deleted file mode 100644 index 4b75814..0000000 --- a/projects/mips_sys/tools/src/flashgen.c +++ /dev/null @@ -1,117 +0,0 @@ -#include -#include -#include -#include - -#define INT8 char -#define INT16 short -#define INT32 long -#define UINT8 unsigned char -#define UINT16 unsigned short -#define UINT32 unsigned long -#define INT int -#define UINT unsigned int -#define FLOAT32 float -#define FLOAT64 double - -#define SDRAM_BASE 0x40000000 -#define FLASH_OFFSET 0x00000000 - -// -------------------------------------------------------------- -typedef struct _sflash_img_hdr_t -{ - UINT8 magic[4]; - UINT32 target_addr; - UINT32 img_offset; - UINT32 img_size; - UINT32 hdr_next; - UINT8 img_name[128]; - UINT8 res[108]; - -} flash_img_hdr_t; - -// -------------------------------------------------------------- -void basename(char *pSrc, char *pDst) -{ - int i, size; - - size = strlen(pSrc); - - while(pSrc[size] != '.') - size--; - - for (i=0; i < size; i++) - pDst[i] = pSrc[i]; - - pDst[i] = 0; - -} - -// -------------------------------------------------------------- -int main(int argc, char *argv[]) -{ - char *pFilenameIn; - char name_flash[1024]; - char name_prj[1024]; - char *pBuf; - flash_img_hdr_t img_hdr = {0}; - - FILE *pFile; - int filesize; - long start, end; - int i; - - if (argc < 2) - { - fprintf(stderr, "Usage: flashgen \n"); - return 1; - } - - pFilenameIn = argv[1]; - pFile = fopen(pFilenameIn, "rb"); - if (!pFile) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - basename(pFilenameIn, name_prj); - sprintf(name_flash, "%s.flash.bin", name_prj); - - // determine filesize - fseek(pFile, 0, SEEK_SET); - start = ftell(pFile); - fseek(pFile, 0, SEEK_END); - end = ftell(pFile); - fseek(pFile, 0, SEEK_SET); - filesize = (end-start); - - pBuf = (char*)malloc(filesize); - fread(pBuf, 1, filesize, pFile); - - fclose(pFile); - - pFile = fopen(name_flash, "wb"); - if (!pFile) - { - fprintf(stderr, "Error opening file %s\n", name_flash); - return 1; - } - - img_hdr.magic[0] = 'J'; - img_hdr.magic[1] = 'F'; - img_hdr.magic[2] = 'I'; - img_hdr.magic[3] = '1'; - img_hdr.target_addr = SDRAM_BASE; - img_hdr.img_size = filesize; - img_hdr.img_offset = FLASH_OFFSET + sizeof(flash_img_hdr_t); - img_hdr.hdr_next = FLASH_OFFSET; - - fwrite(&img_hdr, sizeof(flash_img_hdr_t), 1, pFile); - fwrite(pBuf, 1, filesize, pFile); - - fclose(pFile); - - return 0; -} - diff --git a/projects/mips_sys/tools/src/ramgen.c b/projects/mips_sys/tools/src/ramgen.c deleted file mode 100644 index 8f61118..0000000 --- a/projects/mips_sys/tools/src/ramgen.c +++ /dev/null @@ -1,385 +0,0 @@ -#include -#include -#include -#include - -#define ARCH_NAME "data" -#define ENT_NAME "ram" -#define JTAG_ADDR_WIDTH 16 - -// -------------------------------------------------------------- -void basename(char *pSrc, char *pDst) -{ - int i, size; - - size = strlen(pSrc); - - while(pSrc[size] != '.') - size--; - - for (i=0; i < size; i++) - pDst[i] = pSrc[i]; - - pDst[i] = 0; - -} - -int SaveRAM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, filesize, romsize; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fprintf(pFileOut, "LIBRARY IEEE;\n"); - fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); - fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); - fprintf(pFileOut, "\tPort\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\twe\t\t: in unsigned(%d downto 0);\n", nbits_data/8-1); - fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdin\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "END %s;\n", ENT_NAME); - fprintf(pFileOut, "\n"); - - - fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tconstant depth : natural := %d;\n", romsize/4); - fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); - - fprintf(pFileOut, "\tsignal sram : word_array_t :=\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - word = 0; - for (; i < romsize; i += sizeof(int)) - { - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "begin\n", ARCH_NAME); - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "RAM_RW:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(clk)\n"); - fprintf(pFileOut, "\tvariable index : natural range 0 to depth-1;\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); - fprintf(pFileOut, "\t\t\tindex := to_integer(addr(%d downto 2));\n", nbits_addr+1); - fprintf(pFileOut, "\t\t\tif we(0) = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tsram(index)(7 downto 0)\t\t<= din(7 downto 0);\n"); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\t\tif we(1) = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tsram(index)(15 downto 8)\t<= din(15 downto 8);\n"); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\t\tif we(2) = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tsram(index)(23 downto 16)\t<= din(23 downto 16);\n"); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\t\tif we(3) = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tsram(index)(31 downto 24)\t\t<= din(31 downto 24);\n"); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\t\tdout <= sram(index);\n"); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "end %s;\n", ARCH_NAME); - - return 0; -} - -int SaveRAM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, filesize, romsize; - - char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"}; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fprintf(pFileOut, "LIBRARY IEEE;\n"); - fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); - fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "library UNISIM;\n"); - fprintf(pFileOut, "use UNISIM.VComponents.all;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); - fprintf(pFileOut, "\tPort\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "END %s;\n", ENT_NAME); - fprintf(pFileOut, "\n"); - - - fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); - - fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n"); - fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n"); - fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1); - fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n"); - fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n"); - fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - word = 0; - for (; i < romsize; i += sizeof(int)) - { - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "begin\n", ARCH_NAME); - - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(clk)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); - fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "\n"); - fputs(tpl, pFileOut); - - fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n"); - fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1); - fprintf(pFileOut, "\t\t\telse\n"); - fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "end %s;\n", ARCH_NAME); - return 0; -} - -int SaveRAM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, word_addr, filesize, romsize; - char binstr_addr[33]; - char binstr_data[33]; - - char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"}; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fputs(tpl, pFileOut); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn); - fprintf(pFileOut, "# ---------------------------------------------------------------\n"); - fprintf(pFileOut, "# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA\n"); - fprintf(pFileOut, "# User 2\n"); - fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n"); - - word_addr = 0; - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word); - word_addr++; - } - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n"); - fprintf(pFileOut, "exit\n"); - - return 0; -} - -int main(int argc, char *argv[]) -{ - char *pFilenameIn; - char name_prj[1024]; - char name_rom_tcl[1024]; - char name_rom[1024]; - char name_rom_v4ld[1024]; - - FILE *pFileIn; - int filesize, romsize, nbits_addr, nbits_data; - long start, end; - int word, i; - - if (argc < 2) - { - fprintf(stderr, "Usage: ramgen \n"); - return 1; - } - - pFilenameIn = argv[1]; - if (argc == 3) - nbits_addr = atoi(argv[2]); - - - basename(pFilenameIn, name_prj); - sprintf(name_rom, "%s.vhd", name_prj); - sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj); - sprintf(name_rom_tcl, "%s.tcl", name_prj); - - SaveRAM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32); -// SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32); - SaveRAM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32); - - - return 0; -} - diff --git a/projects/mips_sys/tools/src/romgen.c b/projects/mips_sys/tools/src/romgen.c deleted file mode 100644 index a59e705..0000000 --- a/projects/mips_sys/tools/src/romgen.c +++ /dev/null @@ -1,368 +0,0 @@ -#include -#include -#include -#include - -#define ARCH_NAME "data" -#define ENT_NAME "rom" -#define JTAG_ADDR_WIDTH 16 - -// -------------------------------------------------------------- -void basename(char *pSrc, char *pDst) -{ - int i, size; - - size = strlen(pSrc); - - while(pSrc[size] != '.') - size--; - - for (i=0; i < size; i++) - pDst[i] = pSrc[i]; - - pDst[i] = 0; - -} - -int SaveROM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, filesize, romsize; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fprintf(pFileOut, "LIBRARY IEEE;\n"); - fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); - fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); - fprintf(pFileOut, "\tPort\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "END %s;\n", ENT_NAME); - fprintf(pFileOut, "\n"); - - - fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); - - fprintf(pFileOut, "\tconstant word_array : word_array_t :=\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - word = 0; - for (; i < romsize; i += sizeof(int)) - { - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "begin\n", ARCH_NAME); - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(clk)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); - fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "end %s;\n", ARCH_NAME); - - return 0; -} - -int SaveROM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, filesize, romsize; - - char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"}; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fprintf(pFileOut, "LIBRARY IEEE;\n"); - fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); - fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "library UNISIM;\n"); - fprintf(pFileOut, "use UNISIM.VComponents.all;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); - fprintf(pFileOut, "\tPort\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "END %s;\n", ENT_NAME); - fprintf(pFileOut, "\n"); - - - fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); - - fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n"); - fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n"); - fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1); - fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n"); - fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n"); - fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - word = 0; - for (; i < romsize; i += sizeof(int)) - { - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "begin\n", ARCH_NAME); - - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(clk)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); - fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "\n"); - fputs(tpl, pFileOut); - - fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n"); - fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1); - fprintf(pFileOut, "\t\t\telse\n"); - fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "end %s;\n", ARCH_NAME); - return 0; -} - -int SaveROM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, word_addr, filesize, romsize; - char binstr_addr[33]; - char binstr_data[33]; - - char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"}; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fputs(tpl, pFileOut); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn); - fprintf(pFileOut, "# ---------------------------------------------------------------\n"); - fprintf(pFileOut, "# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA\n"); - fprintf(pFileOut, "# User 1\n"); - fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n"); - - word_addr = 0; - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word); - word_addr++; - } - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n"); - fprintf(pFileOut, "exit\n"); - - return 0; -} - -int main(int argc, char *argv[]) -{ - char *pFilenameIn; - char name_prj[1024]; - char name_rom[1024]; - char name_rom_v4ld[1024]; - char name_rom_tcl[1024]; - - FILE *pFileIn; - int filesize, romsize, nbits_addr, nbits_data; - long start, end; - int word, i; - - if (argc < 2) - { - fprintf(stderr, "Usage: romgen \n"); - return 1; - } - - pFilenameIn = argv[1]; - if (argc == 3) - nbits_addr = atoi(argv[2]); - - - basename(pFilenameIn, name_prj); - sprintf(name_rom, "%s.vhd", name_prj); - sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj); - sprintf(name_rom_tcl, "%s.tcl", name_prj); - - SaveROM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32); - SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32); - SaveROM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32); - - - return 0; -} -