- added reset gen
- improved IFG counter Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@836 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
+44
-26
@@ -48,7 +48,7 @@ ARCHITECTURE behavior OF emac_tx IS
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signal cmd_fifo_empty : std_logic;
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signal cmd_fifo_full : std_logic;
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signal flush_en : std_logic;
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signal reset_en : std_logic;
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signal fill_base : word_ptr_t;
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signal fill_size : word_ptr_t;
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@@ -104,15 +104,18 @@ ARCHITECTURE behavior OF emac_tx IS
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signal piso_dout : unsigned(7 downto 0);
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signal piso_dout_vld : std_logic;
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signal piso_10mbps_din_rdy : std_logic;
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signal tx_en : std_logic;
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subtype inter_frame_gap_cnt_t is natural range 0 to natural(1.0*f_sysclk)-1;
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signal reset_pipe : unsigned(31 downto 0);
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subtype inter_frame_gap_cnt_t is natural range 0 to 95;
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signal inter_frame_gap_cnt : inter_frame_gap_cnt_t;
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signal inter_frame_gap_rdy : std_logic;
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type host_state_t is (host_init, host_flush, host_idle, host_alloc, host_setup, host_arm, host_fill, host_commit);
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signal host_s, host_sn : host_state_t;
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type xfer_state_t is (xfer_init, xfer_idle, xfer_setup, xfer_wait, xfer_active, xfer_free);
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type xfer_state_t is (xfer_init, xfer_idle, xfer_setup, xfer_wait, xfer_active, xfer_uncommit, xfer_free);
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signal xfer_s, xfer_sn : xfer_state_t;
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type piso_byte_mask_array_t is array (0 to 3) of unsigned (3 downto 0);
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@@ -129,6 +132,7 @@ begin
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ctrl_out.pkt_alloc_req <= alloc_req;
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ctrl_out.pkt_done <= cmd_fifo_empty;
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ctrl_out.reset_busy <= reset_en;
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mii_tx_er <= ctrl_in.tx_er;
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@@ -152,12 +156,26 @@ begin
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ram_addr_b <= xfer_ptr;
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xfer_tag <= cmd_fifo_dout(35 downto 32);
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reset_en <= reset_pipe(reset_pipe'left);
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------------------------------------------------------------------
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reset_gen:
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' or ctrl_in.reset = '1' then
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reset_pipe <= (others => '1');
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else
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reset_pipe <= reset_pipe(reset_pipe'left-1 downto 0) & '0';
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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host_state_next:
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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if reset_en = '1' then
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host_s <= host_init;
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else
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host_s <= host_sn;
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@@ -169,7 +187,6 @@ host_state:
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process(host_s, alloc_req, alloc_OK, fill_rdy, din_vld, ctrl_in.pkt_commit_en)
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begin
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flush_en <= '0';
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fill_cnt_set <= '0';
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fill_cnt_adv <= '0';
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fill_ptr_set <= '0';
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@@ -183,13 +200,8 @@ host_state:
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case host_s is
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when host_init =>
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flush_en <= '1';
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host_sn <= host_flush;
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host_sn <= host_idle;
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when host_flush =>
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flush_en <= '1';
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host_sn <= host_idle;
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when host_idle =>
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if alloc_req = '1' then
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host_sn <= host_alloc;
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@@ -237,7 +249,7 @@ alloc_request_logic:
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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if reset_en = '1' then
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alloc_req <= '0';
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elsif ctrl_in.pkt_alloc_en = '1' and alloc_req = '0' then
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alloc_req <= '1';
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@@ -260,7 +272,7 @@ fill_base_logic:
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process(clk)
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begin
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if rising_edge(clk) then
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if flush_en = '1' then
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if reset_en = '1' then
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fill_base <= (others => '0');
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elsif commit_en = '1' then
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fill_base <= fill_ptr;
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@@ -287,7 +299,7 @@ nwords_free_counter:
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process(clk)
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begin
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if rising_edge(clk) then
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if flush_en = '1' then
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if reset_en = '1' then
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nwords_free <= (others => '1');
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elsif mem_alloc_en = '1' then
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nwords_free <= nwords_free - fill_size;
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@@ -336,7 +348,7 @@ xfer_state_next:
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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if reset_en = '1' then
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xfer_s <= xfer_init;
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else
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xfer_s <= xfer_sn;
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@@ -391,14 +403,19 @@ xfer_state:
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xfer_cnt_adv <= '0';
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xfer_ptr_adv <= '0';
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if mii_fifo_full = '0' then
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xfer_sn <= xfer_free;
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xfer_sn <= xfer_uncommit;
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end if;
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end if;
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when xfer_free =>
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when xfer_uncommit =>
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mem_free_en <= not mem_alloc_en;
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if mem_alloc_en = '0' then
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uncommit_en <= '1';
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xfer_sn <= xfer_free;
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end if;
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when xfer_free =>
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if inter_frame_gap_rdy = '0' then
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xfer_sn <= xfer_idle;
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end if;
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@@ -410,12 +427,12 @@ xfer_state:
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------------------------------------------------------------------
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interframe_gap_counter:
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process(clk)
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process(mii_tx_clk)
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begin
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if rising_edge(clk) then
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if flush_en = '1' then
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if rising_edge(mii_tx_clk) then
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if reset_en = '1' then
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inter_frame_gap_rdy <= '1';
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elsif mii_fifo_empty = '0' then
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elsif tx_en = '1' then
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inter_frame_gap_rdy <= '0';
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inter_frame_gap_cnt <= inter_frame_gap_cnt_t'high;
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elsif inter_frame_gap_cnt /= 0 then
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@@ -495,7 +512,7 @@ inst_cmd_fifo: entity work.fifo_sync
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)
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PORT MAP
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(
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rst => flush_en,
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rst => reset_en,
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clk => clk,
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we => cmd_fifo_we,
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re => cmd_fifo_re,
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@@ -517,7 +534,7 @@ inst_mii_fifo: entity work.fifo_async
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)
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PORT MAP
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(
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rst => rst,
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rst => reset_en,
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clk_w => clk,
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clk_r => mii_tx_clk,
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we => mii_fifo_we,
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@@ -539,7 +556,7 @@ inst_piso : entity work.piso
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)
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PORT MAP
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(
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rst => rst,
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rst => reset_en,
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clk => mii_tx_clk,
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din_vld => data_vld,
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din_rdy => piso_din_rdy,
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@@ -560,18 +577,19 @@ inst_piso_10mbps : entity work.piso
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)
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PORT MAP
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(
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rst => rst,
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rst => reset_en,
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clk => mii_tx_clk,
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din_vld => piso_dout_vld,
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din_rdy => piso_10mbps_din_rdy,
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din_be => "11",
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din => piso_dout,
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dout_vld => mii_tx_en,
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dout_vld => tx_en,
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dout_en => '1',
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dout => mii_tx(3 downto 0)
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);
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mii_tx_en <= tx_en;
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mii_tx(7 downto 4) <= "0000";
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end behavior;
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