diff --git a/lib/emac/src/piso.vhd b/lib/emac/src/piso.vhd
index fe05fa2..8efe620 100644
--- a/lib/emac/src/piso.vhd
+++ b/lib/emac/src/piso.vhd
@@ -16,10 +16,11 @@ ENTITY piso IS
 	(
 		rst			: in  STD_LOGIC;
 		clk			: in  STD_LOGIC;
-		din_rdy		: out STD_LOGIC;
 		din_vld		: in  STD_LOGIC;
+		din_rdy		: out STD_LOGIC;
+		din_be		: in  unsigned(data_width_in/data_width_out-1 downto 0);
 		din			: in  unsigned(data_width_in-1 downto 0);
-		dout_vld	: out STD_LOGIC;
+		dout_en		: out STD_LOGIC;
 		dout		: out unsigned(data_width_out-1 downto 0)
 		
 	);
@@ -32,6 +33,7 @@ ARCHITECTURE behavior OF piso IS
 	signal rdy				: STD_LOGIC;
 	signal shift_cnt_pipe	: unsigned(num_shifts-2 downto 0);
 	signal shift_pipe		: unsigned(data_width_in-1 downto 0);
+	signal vld_pipe			: unsigned(num_shifts-1 downto 0);
 	
 --------------------------------------------------------------------------
 begin
@@ -41,6 +43,8 @@ begin
 	din_rdy		<= rdy;
 	dout		<= 		shift_pipe(shift_pipe'left downto shift_pipe'left-data_width_out+1) when msb_first
 				else	shift_pipe(data_width_out-1 downto 0);
+
+	dout_en		<= vld_pipe(vld_pipe'left) when msb_first else vld_pipe(0);
 	
 --------------------------------------------------------------------------
 process(clk)
@@ -51,10 +55,22 @@ begin
 		elsif rdy = '1' then
 			if din_vld = '1' then
 				shift_cnt_pipe	<= (others => '0');
-				shift_pipe		<= din;
 			end if;
 		else
 			shift_cnt_pipe	<= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0)  & '1';
+		end if;
+	end if;
+end process;
+
+--------------------------------------------------------------------------
+process(clk)
+begin
+	if rising_edge(clk) then
+		if rdy = '1' then
+			if din_vld = '1' then
+				shift_pipe		<= din;
+			end if;
+		else
 			if (msb_first) then
 				shift_pipe		<= shift_pipe(shift_pipe'left-data_width_out downto 0) & (data_width_out-1 downto 0 => '0');
 			else
@@ -65,19 +81,35 @@ begin
 	end if;
 end process;
 
+--------------------------------------------------------------------------
+process(clk)
+begin
+	if rising_edge(clk) then
+		if rdy = '1' then
+			vld_pipe	<= (others => '0');
+			if din_vld = '1' then
+				vld_pipe		<= din_be;
+			end if;
+		else
+			if (msb_first) then
+				vld_pipe		<= vld_pipe(vld_pipe'left-1 downto 0) & '0';
+			else
+				vld_pipe		<= '0' & vld_pipe(vld_pipe'left downto 1);
+			end if;
+		end if;
+	end if;
+end process;
+
 --------------------------------------------------------------------------
 process(clk)
 begin
 	if rising_edge(clk) then
 		if rst = '1' then
 			rdy	<= '0';
-			dout_vld	<= '0';
 		elsif rdy = '1' then
 			if pre_fin = '1' then
-				dout_vld	<= '0';
 				if din_vld = '1' then
 					rdy	<= '0';
-					dout_vld	<= '1';
 				end if;
 			end if;
 		elsif pre_fin = '1' then