From 419ccc4edf6e7683a15704b3a50f2feef88ba28d Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Mon, 20 Oct 2008 19:11:30 +0000 Subject: [PATCH] Minor changes git-svn-id: http://moon:8086/svn/vhdl/trunk@85 cc03376c-175c-47c8-b038-4cd826a8556b --- projects/mips_sys/src/mips_sys_sim.vhd | 63 +++++--------------------- 1 file changed, 11 insertions(+), 52 deletions(-) diff --git a/projects/mips_sys/src/mips_sys_sim.vhd b/projects/mips_sys/src/mips_sys_sim.vhd index b72f12d..8c79aac 100644 --- a/projects/mips_sys/src/mips_sys_sim.vhd +++ b/projects/mips_sys/src/mips_sys_sim.vhd @@ -345,8 +345,6 @@ ARCHITECTURE behavior OF mips_sys IS signal ssram_we_n : std_logic; signal flash_oe_n : std_logic; signal flash_we_n : std_logic; - signal dcm_locked : std_logic; - signal dcm_clk0 : std_logic; -- Arbiter constant ARB_MAX_MASTER : natural := 2; @@ -476,7 +474,6 @@ BEGIN sys_flash_ssram_a <= flash_a when CYC_I_flash = '1' else ssram_a; sys_flash_ssram_we_n <= ssram_we_n and flash_we_n; sys_flash_ssram_oe_n <= ssram_oe_n and flash_oe_n; - sys_ssram_clk <= clk; --------------------------------------------------------------- -- Arbiter @@ -531,9 +528,8 @@ mem_mux: if ADDR_O(31 downto 28) = X"0" then mem_area <= mem_urom; elsif ADDR_O(31 downto 28) = X"A" then - if ADDR_O(26) = '1' then - mem_area <= mem_flash; - elsif ADDR_O(17 downto 16) = "00" then + if ADDR_O(27 downto 26) = "00" then + if ADDR_O(17 downto 16) = "00" then mem_area <= mem_gpio; elsif ADDR_O(17 downto 16) = "01" then mem_area <= mem_uart; @@ -542,11 +538,16 @@ mem_mux: elsif ADDR_O(17 downto 16) = "11" then mem_area <= mem_vga; end if; + elsif ADDR_O(27 downto 26) = "01" then + mem_area <= mem_flash; + elsif ADDR_O(27 downto 26) = "10" then + mem_area <= mem_ssram; + end if; elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then mem_area <= mem_rom; elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then - mem_area <= mem_ssram; --- mem_area <= mem_ram; + mem_area <= mem_ram; +-- mem_area <= mem_ssram; elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then mem_area <= mem_sdram; end if; @@ -824,7 +825,8 @@ inst_ssram_frontend_wb : entity work.ssram_frontend_wb DAT_O => SDAT_O_ssram, -- Sync SRAM domain - ssram_clk_i => ssram_clk, + ssram_clk_o => sys_ssram_clk, + ssram_clk_fb => sys_ssram_clk_fb, ssram_cke_n => sys_ssram_cke_n, ssram_ce_n => sys_ssram_ce_n, ssram_oe_n => ssram_oe_n, @@ -949,48 +951,5 @@ inst_vga_frontend : vga_frontend vga_vsync => sys_vga_vsync ); -ssram_bufg: bufg - port map - ( - o => ssram_clk, - i => dcm_clk0 - ); - -inst_DCM_BASE_0 : DCM_BASE - generic map ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => 10.0 , -- Specify period of input clock in ns from 1.25 to 1000.00 - CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X - DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE - DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE - DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" - PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023 - STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - port map ( - CLK0 => dcm_clk0, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => open, -- 270 degree DCM CLK output - CLK2X => open, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => open, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => dcm_locked, -- DCM LOCK status output - CLKFB => sys_ssram_clk_fb, -- DCM clock feedback - CLKIN => clk, -- Clock input (from IBUFG, BUFG or DCM) - RST => rst -- DCM asynchronous reset input - ); - ------------------------------------------------------------------ END;