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- cleaned up

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git-svn-id: http://moon:8086/svn/vhdl/branches/BRANCH_MIPS_TLB@1025 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2013-08-25 17:59:12 +00:00
parent 8a6d599836
commit 41939cf290
4 changed files with 16 additions and 40 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/CPUs/MIPS/src/core/mips_cop.vhd
-4
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@@ -235,10 +235,6 @@ architecture Behavioral of cop is
--------------------------------------------------------------------------
begin
-- Pass to pipeline TLB status
ctrl_out.pipe.ITLB_stat <= ctrl_in.itlb_ctrl.stat;
ctrl_out.pipe.DTLB_stat <= ctrl_in.dtlb_ctrl.stat;
-- I-TLB stuff
ctrl_out.itlb_ctrl.entry_re <= '1'; -- cop_pipe_ID.TLBR and not tlb_sel; -- on tlbr
ctrl_out.itlb_ctrl.entry_we <= (cop_pipe_EX.TLBWI or cop_pipe_EX.TLBWR) and not tlb_sel; -- on tlbwi or tlbwr
lib/CPUs/MIPS/src/core/mips_pipeline.vhd
+6 -6
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@@ -445,9 +445,9 @@ proc_ID_except:
ID_stage.events <= events_clr;
ID_stage.events.inst_load_err <= not ctrl_in.exc_pending and (ID_stage.pcn(1) or ID_stage.pcn(0));
ID_stage.events.inst_priv_addr <= not ctrl_in.exc_pending and (ID_stage.pcn(word_t'left) and ctrl_in.user_mode);
ID_stage.events.ITLB_LOAD <= ctrl_in.ITLB_stat.vld and ctrl_in.ITLB_stat.exc_miss and not ctrl_in.ITLB_stat.write;
ID_stage.events.ITLB_STORE <= ctrl_in.ITLB_stat.vld and ctrl_in.ITLB_stat.exc_miss and ctrl_in.ITLB_stat.write;
ID_stage.events.ITLB_MOD <= ctrl_in.ITLB_stat.vld and ctrl_in.ITLB_stat.exc_dirty;
ID_stage.events.ITLB_LOAD <= itlb_qry_in.vld and itlb_qry_in.miss and not itlb_qry_in.write;
ID_stage.events.ITLB_STORE <= itlb_qry_in.vld and itlb_qry_in.miss and itlb_qry_in.write;
ID_stage.events.ITLB_MOD <= itlb_qry_in.vld and itlb_qry_in.dirty;
end process;
proc_stage_hdu:
@@ -881,9 +881,9 @@ proc_stage_MEM_except:
MEM_stage.events <= MEM_stage.events_in;
MEM_stage.events.Int <= ctrl_in.int;
MEM_stage.events.NMI <= ctrl_in.NMI;
MEM_stage.events.DTLB_LOAD <= ctrl_in.DTLB_stat.vld and ctrl_in.DTLB_stat.exc_miss and not ctrl_in.DTLB_stat.write;
MEM_stage.events.DTLB_STORE <= ctrl_in.DTLB_stat.vld and ctrl_in.DTLB_stat.exc_miss and ctrl_in.DTLB_stat.write;
MEM_stage.events.DTLB_MOD <= ctrl_in.DTLB_stat.vld and ctrl_in.DTLB_stat.exc_dirty;
MEM_stage.events.DTLB_LOAD <= dtlb_qry_in.vld and dtlb_qry_in.miss and not dtlb_qry_in.write;
MEM_stage.events.DTLB_STORE <= dtlb_qry_in.vld and dtlb_qry_in.miss and dtlb_qry_in.write;
MEM_stage.events.DTLB_MOD <= dtlb_qry_in.vld and dtlb_qry_in.dirty;
end process;
MEM_stage.exc <= event_is_active(MEM_stage.events);
lib/CPUs/MIPS/src/core/mips_tlb.vhd
+7 -12
View File
@@ -48,7 +48,6 @@ ARCHITECTURE behavior OF tlb IS
signal hit_umuc : STD_LOGIC;
signal entry_lo_res : tlb_entry_lo_t;
signal qry_res : tlb_query_out_t;
signal stat_res : tlb_status_t;
signal pa : word_t;
signal hit : STD_LOGIC;
@@ -58,6 +57,7 @@ ARCHITECTURE behavior OF tlb IS
signal cam_hit_vld : STD_LOGIC;
signal vaddr_reg : word_t;
signal write_reg : STD_LOGIC;
subtype reg_lo_t is unsigned(23 downto 0);
subtype reg_hi_t is unsigned(25 downto 0);
@@ -151,22 +151,16 @@ begin
clk_rd <= clk;
rdy <= cam_rdy;
stat_res.vld <= vld_r;
stat_res.exc_miss <= not hit;
stat_res.exc_dirty <= hit and qry_res.flags.D and query_in.write;
stat_res.write <= query_in.write;
qry_res.paddr <= pa;
qry_res.hit <= hit;
qry_res.vld <= vld_r;
qry_res.miss <= not hit;
qry_res.dirty <= hit and qry_res.flags.D and write_reg;
qry_res.write <= write_reg;
qry_res.flags.N <= entry_lo_res.N;
qry_res.flags.D <= entry_lo_res.D;
qry_res.flags.V <= entry_lo_res.V;
qry_res.exc <= stat_res.exc_miss or stat_res.exc_dirty;
qry_res.vld <= vld_r;
qry_res.idx <= (hit_umc or hit_umuc) & reg_qry_entry_lo_addr;
qry_res.paddr <= pa;
query_out <= qry_res;
ctrl_out.stat <= stat_res;
pa <= entry_lo_res.PFN & vaddr_reg(lg2(TLB_PAGE_SIZE)-1 downto 0);
@@ -186,6 +180,7 @@ registered_ctrl_out:
if rising_edge(clk) then
if query_in.vld = '1' then
vaddr_reg <= query_in.vaddr;
write_reg <= query_in.write;
end if;
vld_r <= query_in.vld;
if ce = '1' then
lib/CPUs/MIPS/src/core/mips_types.vhd
+3 -18
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@@ -332,23 +332,15 @@ package mips_types is
vld : std_logic;
write : std_logic;
vaddr : word_t;
idx : unsigned (lg2(TLB_NUM_ENTRIES) downto 0);
end record;
type tlb_query_out_t is record
vld : std_logic;
exc : STD_LOGIC;
hit : STD_LOGIC;
paddr : word_t;
flags : tlb_flags_t;
idx : unsigned (lg2(TLB_NUM_ENTRIES) downto 0);
end record;
type tlb_status_t is record
vld : std_logic;
exc_miss : std_logic;
exc_dirty : std_logic;
miss : STD_LOGIC;
dirty : std_logic;
write : std_logic;
flags : tlb_flags_t;
end record;
type tlb_ctrl_in_t is record
@@ -365,7 +357,6 @@ package mips_types is
entry_lo : tlb_entry_lo_t;
entry_hi : tlb_entry_hi_t;
entry_prb_idx : unsigned (lg2(TLB_NUM_ENTRIES)-1 downto 0);
stat : tlb_status_t;
end record;
type biu_ctrl_in_t is record
@@ -398,10 +389,6 @@ package mips_types is
NMI : STD_LOGIC;
int : STD_LOGIC;
exc_vec : word_t;
ITLB_stat : tlb_status_t;
DTLB_stat : tlb_status_t;
-- itlb_qry : tlb_query_out_t;
-- dtlb_qry : tlb_query_out_t;
end record;
type pipe_ctrl_out_t is record
@@ -413,8 +400,6 @@ package mips_types is
dmem_addr : word_t;
exc_req : STD_LOGIC;
exc_ack : STD_LOGIC;
-- itlb_qry : tlb_query_in_t;
-- dtlb_qry : tlb_query_in_t;
end record;
type cop0_ctrl_in_t is record