diff --git a/lib/misc/async_port_wb.vhd b/lib/misc/async_port_wb.vhd
index 04d2861..1c5d3c3 100644
--- a/lib/misc/async_port_wb.vhd
+++ b/lib/misc/async_port_wb.vhd
@@ -1,5 +1,5 @@
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.7 2009-10-28 22:44:07 Jens Exp $
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.8 2009-10-29 22:56:20 Jens Exp $
 -----------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
@@ -180,8 +180,7 @@ architecture Behavioral of async_port_wb is
 				ack				<= not WE_I_r;
 				rdy				<= do_page_read;
 				if en = '1' and do_page_read = '1' then
-					as.cs			<= '1';
-					cycle_reload	<= async_timespec.ncyc_pulse_page_rd;
+					cycle_reload	<= async_timespec.ncyc_pulse_page_rd-1;
 					sn				<= pulse;
 				elsif async_timespec.ncyc_leadout = 0 then
 					if async_timespec.ncyc_release = 0 then