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- Removed read data mask

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git-svn-id: http://moon:8086/svn/vhdl/trunk@56 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-10-14 17:07:48 +00:00
parent 959217a81c
commit 40d96126e7
2 changed files with 5 additions and 28 deletions
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lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd
+3 -22
View File
@@ -43,9 +43,7 @@ entity ddr_phy is
phy_ctrl : in phy_ctrl_t; phy_ctrl : in phy_ctrl_t;
part_ctrl : in part_ctrl_t; part_ctrl : in part_ctrl_t;
sdr_data_w : in unsigned(SDR_DATA_WIDTH-1 downto 0); sdr_data_w : in unsigned(SDR_DATA_WIDTH-1 downto 0);
sdr_dm_wr_in : in unsigned(SDR_DM_WIDTH-1 downto 0); sdr_dm : in unsigned(SDR_DM_WIDTH-1 downto 0);
sdr_dm_rd_in : in unsigned(SDR_DM_WIDTH-1 downto 0);
sdr_dm_rd_out : out unsigned(SDR_DM_WIDTH-1 downto 0);
sdr_data_r : out unsigned(SDR_DATA_WIDTH-1 downto 0); sdr_data_r : out unsigned(SDR_DATA_WIDTH-1 downto 0);
sdr_data_vld : out STD_LOGIC; sdr_data_vld : out STD_LOGIC;
sdr_data_req_w : out STD_LOGIC; sdr_data_req_w : out STD_LOGIC;
@@ -83,9 +81,6 @@ architecture tech of ddr_phy is
type u_tag_array_t is array (natural range 0 to 4) of user_tag_t; type u_tag_array_t is array (natural range 0 to 4) of user_tag_t;
signal u_tag_pipe : u_tag_array_t; signal u_tag_pipe : u_tag_array_t;
type dm_out_array_t is array (natural range 0 to 4) of unsigned(SDR_DM_WIDTH-1 downto 0);
signal dm_out_pipe : dm_out_array_t;
begin begin
------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------
@@ -102,19 +97,6 @@ utag_pipe:
end if; end if;
end process; end process;
dmout_pipe:
process(sys_rst, sys_clk0)
begin
if rising_edge(sys_clk0) then
for i in dm_out_pipe'length-1 downto 1 loop
dm_out_pipe(i) <= dm_out_pipe(i-1);
end loop;
if phy_ctrl.utag_we = '1' then
dm_out_pipe(0) <= sdr_dm_rd_in;
end if;
end if;
end process;
WE_REGISTER: WE_REGISTER:
process(sys_rst, sys_clk0) process(sys_rst, sys_clk0)
begin begin
@@ -239,8 +221,8 @@ gen_ddr_dm_out:
Q => part_dm(n), -- 1-bit DDR output Q => part_dm(n), -- 1-bit DDR output
C => sys_clk270, -- 1-bit clock input C => sys_clk270, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input CE => '1', -- 1-bit clock enable input
D1 => sdr_dm_wr_in(n + DDR_DM_WIDTH), -- 1-bit data input (positive edge) D1 => sdr_dm(n + DDR_DM_WIDTH), -- 1-bit data input (positive edge)
D2 => sdr_dm_wr_in(n), -- 1-bit data input (negative edge) D2 => sdr_dm(n), -- 1-bit data input (negative edge)
R => '0', -- 1-bit reset input R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input S => '0' -- 1-bit set input
); );
@@ -368,7 +350,6 @@ misc_flags_and_data_out:
sdr_data_r <= data_reg_r; sdr_data_r <= data_reg_r;
if p(3) = '1' then if p(3) = '1' then
u_tag_rd <= u_tag_pipe(4); u_tag_rd <= u_tag_pipe(4);
sdr_dm_rd_out <= dm_out_pipe(4);
end if; end if;
if phy_ctrl.we = '1' then if phy_ctrl.we = '1' then
u_tag_wr <= u_tag_pipe(0); u_tag_wr <= u_tag_pipe(0);
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd
+2 -6
View File
@@ -53,9 +53,7 @@ entity sdram_ctrl_top is
u_cmd : in user_cmd_t; u_cmd : in user_cmd_t;
u_cmd_we : in STD_LOGIC; u_cmd_we : in STD_LOGIC;
u_data_wr : in unsigned(SDR_DATA_WIDTH-1 downto 0); u_data_wr : in unsigned(SDR_DATA_WIDTH-1 downto 0);
u_dm_wr_in : in unsigned(SDR_DM_WIDTH-1 downto 0); u_dm : in unsigned(SDR_DM_WIDTH-1 downto 0);
u_dm_rd_in : in unsigned(SDR_DM_WIDTH-1 downto 0);
u_dm_rd_out : out unsigned(SDR_DM_WIDTH-1 downto 0);
u_data_rd : out unsigned(SDR_DATA_WIDTH-1 downto 0); u_data_rd : out unsigned(SDR_DATA_WIDTH-1 downto 0);
-- SDRAM signals -- SDRAM signals
@@ -225,9 +223,7 @@ begin
sdr_data_req_w => u_data_req_w, sdr_data_req_w => u_data_req_w,
sdr_data_req_r => u_data_req_r, sdr_data_req_r => u_data_req_r,
sdr_data_w => u_data_wr, sdr_data_w => u_data_wr,
sdr_dm_wr_in => u_dm_wr_in, sdr_dm => u_dm,
sdr_dm_rd_in => u_dm_rd_in,
sdr_dm_rd_out => u_dm_rd_out,
sdr_data_r => u_data_rd, sdr_data_r => u_data_rd,
sdr_data_vld => u_data_vld, sdr_data_vld => u_data_vld,
part_clk_p => sd_clk_p, part_clk_p => sd_clk_p,