- simplified CMD FSM

git-svn-id: http://moon:8086/svn/vhdl/trunk@1230 cc03376c-175c-47c8-b038-4cd826a8556b
2015-05-25 11:37:41 +00:00
parent d1893931ed
commit 3edba6d5a7
3 changed files with 26 additions and 50 deletions
@@ -79,9 +79,9 @@ add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/
 add wave -noupdate -format Literal -expand /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/phy_ctrl
 add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/st_sdr
 add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/st_sdr_next
-add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/cc_preset
 add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/cc_load_en
 add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/cycle_finished
+add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/cycle_cnt
 add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/burst_load_en
 add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/burst_finished
 add wave -noupdate -format Literal /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_cmd/burst_cnt
@@ -132,7 +132,7 @@ add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/
 add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/bank_activate
 add wave -noupdate -format Logic /tb_ctrl_sdr_wb32/uut/sdram_ctrl_frontend_wb16/inst_sdram_ctrl_top/inst_sdram_ctrl/bank_clr
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {119525000 ps} 0}
+WaveRestoreCursors {{Cursor 1} {82985000 ps} 0}
 configure wave -namecolwidth 150
 configure wave -valuecolwidth 100
 configure wave -justifyvalue left
@@ -54,7 +54,6 @@ architecture behaviour of sdram_cmd is
 	subtype cycle_cnt_t is natural range 0 to 15;
 	subtype burst_cnt_t is natural range 0 to 2**(LMR_BL_CURR)-1;

-	signal cc_preset : cycle_cnt_t;
 	signal cc_load_en : std_logic;
 	signal cycle_finished : std_logic;
 	signal cycle_cnt : cycle_cnt_t;
@@ -92,7 +91,6 @@ fsm_sdr_state:
 		phy_ctrl.part.cke	<= enable;
 		phy_ctrl.u_tag		<= tag;
 		cc_load_en			<= '0';
-		cc_preset			<= TIMING(cmd);
 		burst_load_en		<= '0';
 		cmd_ack				<= '0';
 		phy_ctrl.re			<= '0';
@@ -110,11 +108,15 @@ fsm_sdr_state:
 			end if;	
 			
 		when PRECHARGE =>
-			if cycle_finished = '1' then
-				st_sdr_next <= IDLE;
-			end if;	
+			st_sdr_next <= IDLE_WAIT;

 		when MODE =>
+			st_sdr_next <= IDLE_WAIT;
+
+		when ROW_ACT =>
+			st_sdr_next <= IDLE_WAIT;
+
+		when IDLE_WAIT =>
 			if cycle_finished = '1' then
 				st_sdr_next <= IDLE;
 			end if;	
@@ -123,7 +125,7 @@ fsm_sdr_state:
 			if cmd_we = '1' then
 				cmd_ack <= '1';
 				cc_load_en <= '1';
-				cc_preset <= TIMING(cmd);
+				burst_load_en <= '1';
 				phy_ctrl.part.cmd <= COMMAND(cmd);
 				case cmd is
 					when SD_PRE =>
@@ -134,21 +136,6 @@ fsm_sdr_state:
 						st_sdr_next <= ROW_ACT;
 					when SD_AR =>
 						st_sdr_next <= AUTO_REF;
-					when others	=> null;
-					end case;	
-			end if;	
-				
-		when ROW_ACT =>
-			if cycle_finished = '1' then
-				if cmd_we = '1' then
-					cmd_ack <= '1';
-					burst_load_en <= '1';
-					cc_load_en <= '1';
-					cc_preset <= TIMING(cmd);
-					phy_ctrl.part.cmd <= COMMAND(cmd);
-					case cmd is
-					when SD_PRE =>
-						st_sdr_next <= PRECHARGE;
 					when SD_READ =>
 						phy_ctrl.utag_we <= '1';
 						st_sdr_next <= READ;
@@ -160,7 +147,6 @@ fsm_sdr_state:
 						phy_ctrl.part.addr(col_addr_t'range) <= col_addr;
 					when others	=> null;
 					end case;	
-				end if;	
 			end if;	
 				
 		when WRITE =>
@@ -168,6 +154,7 @@ fsm_sdr_state:
 			phy_ctrl.we <= '1';
 			phy_ctrl.part.cmd <= COMMAND(SD_NOP);
 			if cmd_we = '1' and cmd = SD_WRITE then
+				cc_load_en <= '1';
 				cmd_ack <= '1';
 				phy_ctrl.utag_we <= '1';
 				phy_ctrl.part.addr(col_addr_t'range) <= col_addr;
@@ -177,15 +164,14 @@ fsm_sdr_state:
 				end if;
 			else	
 				phy_ctrl.drive_en <= '0';
-				cc_load_en <= '1';
-				cc_preset <= TIMING(SD_WRITE)+1;
-				st_sdr_next <= ROW_ACT;
+				st_sdr_next <= IDLE_WAIT;
 			end if;

 		when READ =>
 			phy_ctrl.re <= '1';
 			phy_ctrl.part.cmd <= COMMAND(SD_NOP);
 			if cmd_we = '1' and cmd = SD_READ then
+				cc_load_en <= '1';
 				cmd_ack <= '1';
 				phy_ctrl.utag_we <= '1';
 				phy_ctrl.part.addr(col_addr_t'range) <= col_addr;
@@ -194,39 +180,29 @@ fsm_sdr_state:
 					phy_ctrl.part.cmd <= COMMAND(cmd);
 				end if;
 			else
-				cc_load_en <= '1';
-				cc_preset <= TIMING(SD_READ);
-				st_sdr_next <= ROW_ACT;
+				st_sdr_next <= IDLE_WAIT;
 			end if;

 		when WRITE_A =>			-- not implemented yet
-			cmd_ack <= '1';
-			st_sdr_next <= IDLE;
+			st_sdr_next <= IDLE_WAIT;

 		when READ_A =>			-- not implemented yet
-			cmd_ack <= '1';
-			st_sdr_next <= IDLE;
+			st_sdr_next <= IDLE_WAIT;

 		when BURST_STOP =>		-- not implemented yet
-			cmd_ack <= '1';
-			st_sdr_next <= IDLE;
+			st_sdr_next <= IDLE_WAIT;
 			
 		when SELF_REF =>		-- not implemented yet
-			cmd_ack <= '1';
-			st_sdr_next <= IDLE;
+			st_sdr_next <= IDLE_WAIT;
 			
 		when PRE_PWR_DOWN =>	-- not implemented yet
-			cmd_ack <= '1';
-			st_sdr_next <= IDLE;
+			st_sdr_next <= IDLE_WAIT;

 		when ACT_PWR_DOWN =>	-- not implemented yet
-			cmd_ack <= '1';
-			st_sdr_next <= IDLE;
+			st_sdr_next <= IDLE_WAIT;
 		
 		when AUTO_REF =>
-			if cycle_finished = '1' then
-				st_sdr_next <= IDLE;
-			end if;	
+			st_sdr_next <= IDLE_WAIT;
 			
 		when others =>
 			st_sdr_next <= IDLE;
@@ -251,9 +227,9 @@ cycle_counter:
 	process (clk)
 	begin
 		if rising_edge(clk) then
-			cycle_finished	<= '0';
 			if cc_load_en = '1' then
-				cycle_cnt <= cc_preset;
+				cycle_finished	<= '0';
+				cycle_cnt <= TIMING(cmd);
 			elsif cycle_cnt /= 0 then
 				cycle_cnt <= cycle_cnt - 1;
 			else
@@ -36,7 +36,7 @@ package sdram_types is

 	-- Derived constants from sdram_config

-	type sdr_state_t is (PWR_DOWN, PRECHARGE, MODE, IDLE, ROW_ACT, WRITE, WRITE_A, READ, READ_A, BURST_STOP, SELF_REF, AUTO_REF, PRE_PWR_DOWN, ACT_PWR_DOWN);
+	type sdr_state_t is (PWR_DOWN, PRECHARGE, MODE, IDLE_WAIT, IDLE, ROW_ACT, WRITE, WRITE_A, READ, READ_A, BURST_STOP, SELF_REF, AUTO_REF, PRE_PWR_DOWN, ACT_PWR_DOWN);
 	subtype user_addr_t is unsigned(PART_BANK_WIDTH+PART_ROW_ADDR_WIDTH+PART_COL_ADDR_WIDTH-1 downto 0);
 	subtype sdr_addr_t is unsigned(PART_ADDR_WIDTH-1 downto 0);
 	subtype sdr_ba_t is unsigned(PART_BANK_WIDTH-1 downto 0);