From 3ecd76f1857d4df719cc67e8c0c7637facafb490 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Tue, 7 Oct 2008 17:20:44 +0000 Subject: [PATCH] Minor changes git-svn-id: http://moon:8086/svn/vhdl/trunk@26 cc03376c-175c-47c8-b038-4cd826a8556b --- .../sim/tb_sdram_ctrl_frontend_wb.fdo | 2 +- .../sim/tb_sdram_ctrl_frontend_wb.wdo | 17 +- .../src/tb_sdram_ctrl_frontend_wb.vhd | 224 +++++++++--------- 3 files changed, 132 insertions(+), 111 deletions(-) diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.fdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.fdo index c7f5f7f..a8b4cc0 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.fdo +++ b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.fdo @@ -25,4 +25,4 @@ do {tb_sdram_ctrl_frontend_wb.wdo} view wave view structure view signals -run 40us +run 10us diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.wdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.wdo index f2b1282..75a8580 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.wdo +++ b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.wdo @@ -7,14 +7,25 @@ add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/stb_o add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/we_o add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/sel_o add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/ack_i -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/rdy_i +add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/mrdy_o +add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/srdy_i add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/addr_o add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dat_i add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dat_o add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dout_reg add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/dout_cnt +add wave -noupdate -divider Part +add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_cs_n +add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_we_n +add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_ras_n +add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_cas_n +add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_ba +add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_dm +add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_dqs +add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/part_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/part_data TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {7168067 ps} 0} +WaveRestoreCursors {{Cursor 1} {8165533 ps} 0} configure wave -namecolwidth 150 configure wave -valuecolwidth 100 configure wave -justifyvalue left @@ -28,4 +39,4 @@ configure wave -gridperiod 1 configure wave -griddelta 40 configure wave -timeline 0 update -WaveRestoreZoom {7132020 ps} {7288781 ps} +WaveRestoreZoom {7279048 ps} {8233593 ps} diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd index b55ced0..1357c98 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd @@ -66,10 +66,12 @@ architecture struct of tb_sdram_ctrl_frontend_wb is signal WE_O : std_logic := '0'; signal SEL_O : unsigned(3 downto 0) := (others => '1'); signal ACK_I : std_logic; - signal RDY_I : std_logic; + signal MRDY_O : std_logic := '1'; + signal SRDY_I : std_logic; signal ADDR_O : unsigned(31 downto 0) := (others => '-'); signal DAT_I : unsigned(31 downto 0); signal DAT_O : unsigned(31 downto 0) := (others => '-'); + signal dout_rst : std_logic := '0'; signal dout_reg : unsigned(31 downto 0); signal dout_cnt : natural range 0 to 255; @@ -106,7 +108,7 @@ inst_clockgen : entity work.clockgen ( BL => BURST_LEN, f_sysclk => 100E6, - fifo_depth => 2 + fifo_depth => 3 ) PORT MAP ( @@ -120,7 +122,8 @@ inst_clockgen : entity work.clockgen SEL_I => SEL_O, WE_I => WE_O, ACK_O => ACK_I, - RDY_O => RDY_I, + SRDY_O => SRDY_I, + MRDY_I => MRDY_O, ADDR_I => ADDR_O, DAT_I => DAT_O, DAT_O => DAT_I, @@ -187,7 +190,7 @@ STIMULUS: process wait for 3*CLK_PERIOD; rst <= '0'; - + wait until RST_O = '0'; -- 8 single cycles CYC_O <= '1'; @@ -195,119 +198,120 @@ STIMULUS: process WE_O <= '1'; DAT_O <= X"1234_0000"; ADDR_O <= X"0000_0000"; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; DAT_O <= DAT_O + 1; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '0'; + wait until rising_edge(CLK_O) and ACK_I = '1'; CYC_O <= '0'; @@ -320,21 +324,21 @@ STIMULUS: process STB_O <= '1'; WE_O <= '0'; ADDR_O <= X"0000_0000"; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '0'; wait until rising_edge(CLK_O) and dout_cnt = 7; @@ -349,8 +353,9 @@ STIMULUS: process SEL_O <= "0011"; ADDR_O <= X"0000_0080"; DAT_O <= X"DEADBEEF"; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '0'; + wait until rising_edge(CLK_O) and ACK_I = '1'; CYC_O <= '0'; wait for 3*CLK_PERIOD; @@ -360,7 +365,7 @@ STIMULUS: process STB_O <= '1'; WE_O <= '0'; ADDR_O <= X"0000_0080"; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '0'; wait until rising_edge(CLK_O) and ACK_I = '1'; CYC_O <= '0'; @@ -374,115 +379,120 @@ STIMULUS: process STB_O <= '1'; WE_O <= '0'; ADDR_O <= X"0000_0000"; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + STB_O <= '0'; + MRDY_O <= '0'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; + STB_O <= '1'; + MRDY_O <= '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and RDY_I = '1'; + wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '0'; wait until rising_edge(CLK_O) and dout_cnt = 54;