From 3e81496d67c47dcb57f21cf22e8365b1771dd549 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sat, 10 Apr 2010 07:41:57 +0000 Subject: [PATCH] - different IFG for gigabit and 10/100mbps - combines MII-FIFO read delay with IFG-Function - removed IFG-counter Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@903 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/emac/src/emac_tx.vhd | 77 ++++++++++++++++++++++------------------ 1 file changed, 42 insertions(+), 35 deletions(-) diff --git a/lib/emac/src/emac_tx.vhd b/lib/emac/src/emac_tx.vhd index f559b12..e397843 100644 --- a/lib/emac/src/emac_tx.vhd +++ b/lib/emac/src/emac_tx.vhd @@ -116,13 +116,9 @@ ARCHITECTURE behavior OF emac_tx IS signal mii_fifo_re : std_logic; signal mii_fifo_full : std_logic; signal mii_fifo_empty : std_logic; - signal mii_fifo_re_dly : unsigned(7 downto 0); + signal mii_fifo_re_dly : unsigned(23 downto 0); - subtype ifg_cnt_t is natural range 0 to 23; -- 10/100 mbps --- subtype ifg_cnt_t is natural range 0 to 11; -- 1000 mbps - - signal ifg_cnt : ifg_cnt_t; - signal ifg_idle : std_logic; + signal mii_bsy : std_logic; type host_state_t is (host_init, host_idle, host_alloc, host_setup, host_arm, host_fill, host_commit); signal host_s, host_sn : host_state_t; @@ -340,6 +336,7 @@ mem_free_counter: end if; end process; +------------------------------------------------------------------ mem_free_mii: process(mii_tx_clk) begin @@ -356,6 +353,7 @@ mem_free_mii: end if; end process; +------------------------------------------------------------------ mem_free_host: process(clk) begin @@ -373,15 +371,6 @@ mem_free_host: end if; end process; -host2xfer_sync_register: - process(mii_tx_clk) - begin - if rising_edge(mii_tx_clk) then - Gbps_en <= ctrl_in.Gbps_en; - fcs_gen_en <= ctrl_in.fcs_gen_en; - end if; - end process; - ------------------------------------------------------------------ -- Fill stuff ------------------------------------------------------------------ @@ -411,6 +400,7 @@ fill_counter: end if; end process; +------------------------------------------------------------------ fill_pointer: process(clk) begin @@ -426,20 +416,14 @@ fill_pointer: ------------------------------------------------------------------ -- Transfer stuff ------------------------------------------------------------------ -interframe_gap_counter: +host2xfer_sync_register: process(mii_tx_clk) begin if rising_edge(mii_tx_clk) then - ifg_idle <= '0'; - if reset_en = '1' or mii_fifo_empty = '0' then - ifg_cnt <= ifg_cnt_t'high; - elsif ifg_cnt /= 0 then - ifg_cnt <= ifg_cnt - 1; - else - ifg_idle <= '1'; - end if; - end if; - end process; + Gbps_en <= ctrl_in.Gbps_en; + fcs_gen_en <= ctrl_in.fcs_gen_en; + end if; + end process; ------------------------------------------------------------------ xfer_counter: @@ -465,6 +449,7 @@ xfer_counter: end process; +------------------------------------------------------------------ xfer_pointer: process(mii_tx_clk) begin @@ -494,7 +479,7 @@ xfer_state_next: end process; xfer_state: - process(xfer_s, ifg_idle, cmd_fifo_empty, piso32_din_rdy, piso32_dout_vld, xfer_bsy, fcs_gen_en) + process(xfer_s, mii_bsy, cmd_fifo_empty, piso32_din_rdy, piso32_dout_vld, xfer_bsy, fcs_gen_en) begin piso32_din_vld <= '0'; @@ -515,12 +500,12 @@ xfer_state: xfer_sn <= xfer_idle; when xfer_idle => - if cmd_fifo_empty = '0' then + if cmd_fifo_empty = '0' and mii_bsy = '0' then xfer_sn <= xfer_start; end if; when xfer_start => - if cmd_fifo_empty = '0' and ifg_idle = '1' then + if cmd_fifo_empty = '0' then xfer_sn <= xfer_preamble0; end if; @@ -596,6 +581,7 @@ inst_ram : entity work.dpram_1w1r dout_b => ram_dout_b ); +------------------------------------------------------------------ -- Instantiate synchronous FIFO inst_cmd_fifo: entity work.fifo_async GENERIC MAP @@ -619,6 +605,7 @@ inst_cmd_fifo: entity work.fifo_async data_r => cmd_fifo_dout ); +------------------------------------------------------------------ inst_piso32 : entity work.piso GENERIC MAP ( @@ -642,6 +629,7 @@ inst_piso32 : entity work.piso piso32_dout_en <= not mii_fifo_full; --'1' when Gbps_en = '1' else piso8_din_rdy; +------------------------------------------------------------------ fcs_enable_gen: process(mii_tx_clk) begin @@ -653,8 +641,8 @@ fcs_enable_gen: end if; end if; end process; - fcs_din_vld <= fcs_en(fcs_en'left) and piso32_dout_vld and piso32_dout_en; - + +------------------------------------------------------------------ inst_fcs: entity work.crc32 GENERIC MAP ( @@ -671,17 +659,29 @@ inst_fcs: entity work.crc32 ); + fcs_din_vld <= fcs_en(fcs_en'left) and piso32_dout_vld and piso32_dout_en; + +------------------------------------------------------------------ +-- ensures continous MII-data stream and also acts as Inter Frame Gap delay mii_fifo_re_dly_gen: process(mii_tx_clk) begin if rising_edge(mii_tx_clk) then - mii_fifo_re_dly <= mii_fifo_re_dly(mii_fifo_re_dly'left-1 downto 0) & not mii_fifo_empty; + if mii_fifo_empty = '1' then + if Gbps_en = '0' then + mii_fifo_re_dly <= X"000000"; -- 100 mbps + else + mii_fifo_re_dly <= X"000FFF"; -- Gigabit + end if; + else + mii_fifo_re_dly <= mii_fifo_re_dly(mii_fifo_re_dly'left-1 downto 0) & not mii_fifo_empty; + end if; end if; end process; - mii_fifo_re <= mii_fifo_re_dly(mii_fifo_re_dly'left) when Gbps_en = '1' else (piso8_din_rdy and mii_fifo_re_dly(mii_fifo_re_dly'left)); - mii_fifo_we <= piso32_dout_vld; + mii_bsy <= mii_fifo_re_dly(mii_fifo_re_dly'left); +------------------------------------------------------------------ -- Instantiate synchronous FIFO inst_mii_fifo: entity work.fifo_sync GENERIC MAP @@ -704,6 +704,10 @@ inst_mii_fifo: entity work.fifo_sync data_r => piso8_din ); + mii_fifo_re <= mii_bsy when Gbps_en = '1' else (piso8_din_rdy and mii_bsy); + mii_fifo_we <= piso32_dout_vld; + +------------------------------------------------------------------ inst_piso8 : entity work.piso GENERIC MAP ( @@ -724,8 +728,10 @@ inst_piso8 : entity work.piso dout => piso8_dout ); - piso8_din_vld <= not mii_fifo_empty and mii_fifo_re_dly(mii_fifo_re_dly'left); + + piso8_din_vld <= not mii_fifo_empty and mii_bsy; +------------------------------------------------------------------ mii_output_register: process(mii_tx_clk) begin @@ -741,4 +747,5 @@ mii_output_register: end if; end process; +------------------------------------------------------------------ end behavior;