diff --git a/lib/FIFO/src/tb_fifo_async.vhd b/lib/FIFO/src/tb_fifo_async.vhd
index e0c2b62..c285ec7 100644
--- a/lib/FIFO/src/tb_fifo_async.vhd
+++ b/lib/FIFO/src/tb_fifo_async.vhd
@@ -38,7 +38,7 @@ ARCHITECTURE behavior OF tb_fifo_async IS
 
 	--Constants
 	constant PERIOD_W 	: time := 10 ns;
-	constant PERIOD_R 	: time := 22.1 ns;
+	constant PERIOD_R 	: time := 7.5 ns;
 	constant ADDR_WIDTH : integer := 3;
 	constant DATA_WIDTH : integer := 8;
 
@@ -71,7 +71,10 @@ BEGIN
 		addr_width			=> ADDR_WIDTH,
 		data_width			=> DATA_WIDTH,
 		almost_full_thresh	=> 6,
-		almost_empty_thresh	=> 2
+		almost_empty_thresh	=> 2,
+		allow_full_writes	=> false,
+		allow_empty_reads	=> false,
+		do_last_read_update	=> false
 	)
 	PORT MAP
 	(
@@ -188,7 +191,7 @@ BEGIN
 		
 	END PROCESS;
 	
-	we <= write_en and not fifo_full;
+	we <= write_en;
 	
  	tb_w : PROCESS(rst, clk_w)
 	BEGIN
@@ -196,14 +199,14 @@ BEGIN
 		if rst = '1' then
 			din <= (others => '0');
 		elsif rising_edge(clk_w) then
-			if we = '1' then
+			if we = '1' and fifo_full = '0' then
 				din <= din + 1;
 			end if;				
 		end if;	
 
 	END PROCESS;
 	
-	re	<= read_en and not fifo_empty;
+	re	<= read_en;
 	
  	tb_r : PROCESS(rst, clk_r)
 	BEGIN
@@ -211,7 +214,7 @@ BEGIN
 		if rst = '1' then
 			ref_r <= (others => '0');
 		elsif rising_edge(clk_r) then
-			if re = '1' then
+			if re = '1' and fifo_empty = '0' then
 				assert ref_r = dout report "FIFO read error!" severity failure;
 				ref_r <= ref_r + 1;
 			end if;