From 3be3800dc7adc26b61d65bd4b51f56337c4682b0 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 12 Oct 2008 14:12:14 +0000 Subject: [PATCH] Registered rdy (better timing) git-svn-id: http://moon:8086/svn/vhdl/trunk@53 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/misc/async_port_wb.vhd | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/lib/misc/async_port_wb.vhd b/lib/misc/async_port_wb.vhd index 7ad8964..3eb2ed1 100644 --- a/lib/misc/async_port_wb.vhd +++ b/lib/misc/async_port_wb.vhd @@ -1,5 +1,5 @@ ----------------------------------------------------------------------- --- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.2 2008-10-11 20:13:52 Jens Exp $ +-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.3 2008-10-12 14:12:14 Jens Exp $ ----------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; @@ -55,13 +55,14 @@ architecture Behavioral of async_port_wb is signal cycle_cnt : natural range 0 to 15; signal cycle_reload : natural range 0 to 15; signal rdy : std_logic; + signal rdyo : std_logic; signal en : std_logic; signal data_reg : unsigned(data_width-1 downto 0); ------------------------------------------------------------------ begin - SRDY_O <= CYC_I and rdy; + SRDY_O <= CYC_I and rdyo; en <= CYC_I and STB_I; proc_cycle_counter: @@ -246,6 +247,19 @@ architecture Behavioral of async_port_wb is end if; end process; + ------------------------------------------------------------------ + output_SRDY: + process(CLK_I) + begin + if rising_edge(CLK_I) then + if RST_I = '1' then + rdyo <= '1'; + elsif en = '1' then + rdyo <= rdy and not rdyo; + end if; + end if; + end process; + ------------------------------------------------------------------ output_ACK: process(CLK_I)