- refactored

git-svn-id: http://moon:8086/svn/vhdl/trunk@1555 cc03376c-175c-47c8-b038-4cd826a8556b

lib/VGA_ctrl/ghdl/tb_vga_frontend_jb32.make

@@ -0,0 +1,19 @@
+# -----------------------------------------------------------
+include $(VHDL_HOME)/make/defs.mk
+# -----------------------------------------------------------
+include vga_frontend_jb32.inc
+
+# -----------------------------------------------------------
+SRCS := $(VGA_FRONTEND_JB32_SRCS)
+SRCS += ../src/tb_vga_frontend_jb32.vhd
+
+# -----------------------------------------------------------
+# Compile
+TARGET := tb_vga_frontend_jb32
+ENTITY := tb_vga_frontend_jb32
+WITH_FST := y
+RUN_TIME := 20ms
+
+include $(VHDL_HOME)/make/ghdl.mk
+# -----------------------------------------------------------
+

lib/VGA_ctrl/ghdl/tb_vga_frontend_jb64.make

@@ -0,0 +1,19 @@
+# -----------------------------------------------------------
+include $(VHDL_HOME)/make/defs.mk
+# -----------------------------------------------------------
+include vga_frontend_jb64.inc
+
+# -----------------------------------------------------------
+SRCS := $(VGA_FRONTEND_JB64_SRCS)
+SRCS += ../src/tb_vga_frontend_jb64.vhd
+
+# -----------------------------------------------------------
+# Compile
+TARGET := tb_vga_frontend_jb64
+ENTITY := tb_vga_frontend_jb64
+WITH_FST := y
+RUN_TIME := 2ms
+
+include $(VHDL_HOME)/make/ghdl.mk
+# -----------------------------------------------------------
+

lib/VGA_ctrl/ghdl/vga_frontend_jb32.inc

@@ -0,0 +1,15 @@
+# -----------------------------------------------------------
+include $(VHDL_HOME)/make/defs.mk
+include vga_backend.inc
+include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
+
+# -----------------------------------------------------------
+PKG_NAME := VGA_FRONTEND_JB32
+
+# -----------------------------------------------------------
+$(PKG_NAME)_SRCS := $(VGA_BACKEND_SRCS)
+$(PKG_NAME)_SRCS += $(FIFO_ASYNC_SRCS)
+$(PKG_NAME)_SRCS += ../src/vga_frontend_jb32.vhd
+
+# -----------------------------------------------------------
+

lib/VGA_ctrl/ghdl/vga_frontend_jb64.inc

@@ -0,0 +1,17 @@
+# -----------------------------------------------------------
+include $(VHDL_HOME)/make/defs.mk
+include vga_backend.inc
+include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
+include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
+
+# -----------------------------------------------------------
+PKG_NAME := VGA_FRONTEND_JB64
+
+# -----------------------------------------------------------
+$(PKG_NAME)_SRCS := $(VGA_BACKEND_SRCS)
+$(PKG_NAME)_SRCS += $(FIFO_SYNC_SRCS)
+$(PKG_NAME)_SRCS += $(FIFO_ASYNC_SRCS)
+$(PKG_NAME)_SRCS += ../src/vga_frontend_jb64.vhd
+
+# -----------------------------------------------------------
+

lib/VGA_ctrl/sim/tb_vga_frontend_jb32.fdo

@@ -17,11 +17,11 @@ vcom -explicit  -93 "../src/char_gen.vhd"
 vcom -explicit  -93 "../src/vga_sync.vhd"
 vcom -explicit  -93 "../src/vga_timing.vhd"
 vcom -explicit  -93 "../src/vga_backend.vhd"
-vcom -explicit  -93 "../src/vga_frontend.vhd"
+vcom -explicit  -93 "../src/vga_frontend_jb32.vhd"
-vcom -explicit  -93 "../src/tb_vga_frontend.vhd"
+vcom -explicit  -93 "../src/tb_vga_frontend_jb32.vhd"
-vsim -t 1ps   -lib work tb_vga_frontend
+vsim -t 1ps   -lib work tb_vga_frontend_jb32
 view wave
-do {tb_vga_frontend.wdo}
+do {tb_vga_frontend_jb32.wdo}
 view structure
 view signals
 

lib/VGA_ctrl/sim/tb_vga_frontend_jb64.fdo

@@ -19,11 +19,11 @@ vcom -explicit  -93 "../src/char_gen.vhd"
 vcom -explicit  -93 "../src/vga_sync.vhd"
 vcom -explicit  -93 "../src/vga_timing.vhd"
 vcom -explicit  -93 "../src/vga_backend.vhd"
-vcom -explicit  -93 "../src/vga_frontend64.vhd"
+vcom -explicit  -93 "../src/vga_frontend_jb64.vhd"
-vcom -explicit  -93 "../src/tb_vga_frontend64.vhd"
+vcom -explicit  -93 "../src/tb_vga_frontend_jb64.vhd"
-vsim -t 1ps   -lib work tb_vga_frontend64
+vsim -t 1ps   -lib work tb_vga_frontend_jb64
 view wave
-do {tb_vga_frontend64.wdo}
+do {tb_vga_frontend_jb64.wdo}
 view structure
 view signals
 

lib/VGA_ctrl/src/tb_vga_frontend_jb32.vhd

@@ -28,10 +28,10 @@ USE ieee.numeric_std.ALL;
 
 use work.vga_types.all;
 
-ENTITY tb_vga_frontend IS
+ENTITY tb_vga_frontend_jb32 IS
-END tb_vga_frontend;
+END tb_vga_frontend_jb32;
 
-ARCHITECTURE behavior OF tb_vga_frontend IS 
+ARCHITECTURE behavior OF tb_vga_frontend_jb32 IS 
 
 	constant tsvga			: vga_timespec_t := ts_vga_testbench;
 	constant CLK_PERIOD		: time := 10 ns;
@@ -77,7 +77,7 @@ ARCHITECTURE behavior OF tb_vga_frontend IS
 
 BEGIN
 
-inst_vga_frontend : entity work.vga_frontend
+inst_vga_frontend_jb32 : entity work.vga_frontend_jb32
 	GENERIC MAP
 	(
 		fifo_depth					=> 256,

lib/VGA_ctrl/src/tb_vga_frontend_jb64.vhd

@@ -28,10 +28,10 @@ USE ieee.numeric_std.ALL;
 
 use work.vga_types.all;
 
-ENTITY tb_vga_frontend64 IS
+ENTITY tb_vga_frontend_jb64 IS
-END tb_vga_frontend64;
+END tb_vga_frontend_jb64;
 
-ARCHITECTURE behavior OF tb_vga_frontend64 IS 
+ARCHITECTURE behavior OF tb_vga_frontend_jb64 IS 
 
 	constant tsvga			: vga_timespec_t := ts_vga_testbench;
 	constant CLK_PERIOD		: time := 10 ns;
@@ -371,7 +371,7 @@ ARCHITECTURE behavior OF tb_vga_frontend64 IS
 
 BEGIN
 
-inst_vga_frontend64 : entity work.vga_frontend64
+inst_vga_frontend_jb64 : entity work.vga_frontend_jb64
 	GENERIC MAP
 	(
 		fifo_depth					=> 64,

lib/VGA_ctrl/src/vga_frontend_jb32.vhd

@@ -24,7 +24,7 @@ use IEEE.NUMERIC_STD.ALL;
 use work.utils_pkg.all;
 use work.vga_types.all;
 
-entity vga_frontend is
+entity vga_frontend_jb32 is
 	Generic
 	(
 		fifo_depth					: integer    		:= 2048;
@@ -73,9 +73,9 @@ entity vga_frontend is
 		vga_hsync		: out std_logic;
 		vga_vsync		: out std_logic
 	);
-end vga_frontend;
+end vga_frontend_jb32;
 
-architecture Behavioral of vga_frontend is
+architecture Behavioral of vga_frontend_jb32 is
 
 	signal vga_clk				: std_logic;
 

lib/VGA_ctrl/src/vga_frontend_jb64.vhd

@@ -24,7 +24,7 @@ use IEEE.NUMERIC_STD.ALL;
 use work.utils_pkg.all;
 use work.vga_types.all;
 
-entity vga_frontend64 is
+entity vga_frontend_jb64 is
 	Generic
 	(
 		fifo_depth					: integer    		:= 4096;
@@ -76,9 +76,9 @@ entity vga_frontend64 is
 		vga_hsync		: out std_logic;
 		vga_vsync		: out std_logic
 	);
-end vga_frontend64;
+end vga_frontend_jb64;
 
-architecture Behavioral of vga_frontend64 is
+architecture Behavioral of vga_frontend_jb64 is
 
 	-- Color FIFO signals
 	signal fifo_full					: std_logic;
@@ -624,7 +624,7 @@ vga_master:
 		request_cnt_rst	<= '1';
 		if fifo_almost_empty = '1' and vga_scan_dma_en2 = '1' then
 			sn				<= scan_bus_request;
-		elsif blit_request = '1' then	-- ToDo: richtig prüfen anhand eines states wer dran ist. Nicht auf FIFO state prüfen
+		elsif blit_request = '1' then	-- ToDo: richtig pr\FCfen anhand eines states wer dran ist. Nicht auf FIFO state pr\FCfen
 			sn	<= blit_dst_bus_request;
 			if blitfifo_dout_vld = '0' or blit_dst_suspend = '1' then
 				sn	<= blit_src_bus_request;