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- modifications for improved SIPOs and PISOs

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git-svn-id: http://moon:8086/svn/vhdl/trunk@818 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-03-25 09:34:01 +00:00
parent 80f57311e4
commit 3b014c19ca
2 changed files with 111 additions and 44 deletions
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lib/emac/src/emac_rx.vhd
+75 -33
View File
@@ -59,11 +59,11 @@ ARCHITECTURE behavior OF emac_rx IS
signal commit_en : std_logic; signal commit_en : std_logic;
signal uncommit_en : std_logic; signal uncommit_en : std_logic;
signal xfer_ram_limit : word_ptr_t;
signal xfer_ram_full : std_logic; signal xfer_ram_full : std_logic;
signal xfer_base : word_ptr_t; signal xfer_base : word_ptr_t;
signal xfer_size : word_ptr_t; signal xfer_size : word_ptr_t;
signal xfer_ptr : word_ptr_t; signal xfer_ptr : word_ptr_t;
signal xfer_ptr_next : word_ptr_t;
signal xfer_cnt : word_ptr_t; signal xfer_cnt : word_ptr_t;
signal xfer_ptr_set : std_logic; signal xfer_ptr_set : std_logic;
signal xfer_ptr_adv : std_logic; signal xfer_ptr_adv : std_logic;
@@ -89,8 +89,16 @@ ARCHITECTURE behavior OF emac_rx IS
signal sipo_dout : unsigned(31 downto 0); signal sipo_dout : unsigned(31 downto 0);
signal sipo_dout_be : unsigned(3 downto 0); signal sipo_dout_be : unsigned(3 downto 0);
signal sipo_dout_vld : std_logic; signal sipo_dout_vld : std_logic;
signal sipo_dout_en : std_logic;
signal sipo_rst : std_logic; signal sipo_rst : std_logic;
signal sipo_10mbps_dout : unsigned(7 downto 0);
signal sipo_10mbps_rst : std_logic;
signal sipo_10mbps_dout_vld : std_logic;
signal sipo_10mbps_dout_en : std_logic;
signal byte_active_r : std_logic;
signal word_active_r : std_logic;
signal byte_count : word_ptr_t; signal byte_count : word_ptr_t;
signal byte_count_reg : word_ptr_t; signal byte_count_reg : word_ptr_t;
signal byte_count_reg_s : word_ptr_t; signal byte_count_reg_s : word_ptr_t;
@@ -102,8 +110,6 @@ ARCHITECTURE behavior OF emac_rx IS
signal word_count_ack : std_logic; signal word_count_ack : std_logic;
signal word_count_vld : std_logic; signal word_count_vld : std_logic;
signal rx_dv_r : std_logic;
type host_state_t is (host_init, host_flush, host_idle, host_setup, host_arm, host_fill, host_uncommit); type host_state_t is (host_init, host_flush, host_idle, host_setup, host_arm, host_fill, host_uncommit);
signal host_s, host_sn : host_state_t; signal host_s, host_sn : host_state_t;
@@ -117,10 +123,10 @@ begin
ctrl_out.rx_er <= mii_rx_er; ctrl_out.rx_er <= mii_rx_er;
dout <= ram_dout_a; dout <= ram_dout_a;
mii_fifo_din <= sipo_dout_be & sipo_dout; mii_fifo_din <= "0000" & sipo_dout;
mii_fifo_we <= sipo_dout_vld; mii_fifo_we <= sipo_dout_vld;
ram_en_a <= ctrl_in.data_read; ram_en_a <= '1';
ram_din_a <= (others => '-'); ram_din_a <= (others => '-');
ram_addr_a <= fill_ptr; ram_addr_a <= fill_ptr;
ram_we_a <= '0'; ram_we_a <= '0';
@@ -283,6 +289,21 @@ xfer_state:
end process; end process;
------------------------------------------------------------------ ------------------------------------------------------------------
xfer_limit_register:
process(clk)
begin
if rising_edge(clk) then
if xfer_ptr_set = '1' then
if cmd_fifo_empty = '1' then
xfer_ram_limit <= xfer_base - 1;
else
xfer_ram_limit <= resize(cmd_fifo_dout(15 downto 0), word_ptr_t'length) - 1;
end if;
end if;
end if;
end process;
xfer_ram_full_detect: xfer_ram_full_detect:
process(clk) process(clk)
begin begin
@@ -290,7 +311,7 @@ xfer_ram_full_detect:
if xfer_ptr_set = '1' or flush_en = '1' then if xfer_ptr_set = '1' or flush_en = '1' then
xfer_ram_full <= '0'; xfer_ram_full <= '0';
elsif xfer_ptr_adv = '1' then elsif xfer_ptr_adv = '1' then
if xfer_ptr_next = resize(cmd_fifo_dout(15 downto 0), word_ptr_t'length) then if xfer_ptr = xfer_ram_limit then
xfer_ram_full <= '1'; xfer_ram_full <= '1';
end if; end if;
end if; end if;
@@ -321,10 +342,8 @@ xfer_pointer:
if rising_edge(clk) then if rising_edge(clk) then
if xfer_ptr_set = '1' then if xfer_ptr_set = '1' then
xfer_ptr <= xfer_base; xfer_ptr <= xfer_base;
xfer_ptr_next <= xfer_base + 1;
elsif xfer_ptr_adv = '1' then elsif xfer_ptr_adv = '1' then
xfer_ptr <= xfer_ptr_next; xfer_ptr <= xfer_ptr + 1;
xfer_ptr_next <= xfer_ptr_next + 1;
end if; end if;
end if; end if;
@@ -347,12 +366,12 @@ byte_counter:
process(mii_rx_clk) process(mii_rx_clk)
begin begin
if rising_edge(mii_rx_clk) then if rising_edge(mii_rx_clk) then
if mii_rx_dv = '0' then if sipo_10mbps_dout_en = '0' then
byte_count <= (others => '0'); byte_count <= (others => '0');
else elsif sipo_10mbps_dout_vld = '1' then
byte_count <= byte_count + 1; byte_count <= byte_count + 1;
end if; end if;
rx_dv_r <= mii_rx_dv; byte_active_r <= sipo_10mbps_dout_en;
end if; end if;
end process; end process;
@@ -362,7 +381,7 @@ byte_count_register:
if rising_edge(mii_rx_clk) then if rising_edge(mii_rx_clk) then
if rst = '1' then if rst = '1' then
byte_count_reg <= (others => '0'); byte_count_reg <= (others => '0');
elsif rx_dv_r = '1' and mii_rx_dv = '0' then elsif byte_active_r = '1' and sipo_10mbps_dout_vld = '0' then
byte_count_reg <= byte_count; byte_count_reg <= byte_count;
end if; end if;
end if; end if;
@@ -372,6 +391,7 @@ word_counter:
process(mii_rx_clk) process(mii_rx_clk)
begin begin
if rising_edge(mii_rx_clk) then if rising_edge(mii_rx_clk) then
word_active_r <= sipo_dout_en;
if rst = '1' or word_count_clr = '1' then if rst = '1' or word_count_clr = '1' then
word_count <= (others => '0'); word_count <= (others => '0');
elsif sipo_dout_vld = '1' then elsif sipo_dout_vld = '1' then
@@ -387,7 +407,7 @@ word_count_set_logic:
if rising_edge(mii_rx_clk) then if rising_edge(mii_rx_clk) then
if rst = '1' or word_count_clr = '1' then if rst = '1' or word_count_clr = '1' then
word_count_set <= '0'; word_count_set <= '0';
elsif sipo_dout_vld = '1' and mii_rx_dv = '0' then elsif word_active_r = '1' and sipo_dout_en = '0' then
word_count_set <= '1'; word_count_set <= '1';
end if; end if;
end if; end if;
@@ -424,7 +444,6 @@ word_count_register:
end if; end if;
end process; end process;
sipo_rst <= not mii_rx_dv;
------------------------------------------------------------------ ------------------------------------------------------------------
-- Instantiate synchronous FIFO -- Instantiate synchronous FIFO
inst_cmd_fifo: entity work.fifo_sync inst_cmd_fifo: entity work.fifo_sync
@@ -448,7 +467,7 @@ inst_cmd_fifo: entity work.fifo_sync
data_r => cmd_fifo_dout data_r => cmd_fifo_dout
); );
inst_ram : entity work.dpram_2w2r inst_ram : entity work.dpram_1w1r
GENERIC MAP GENERIC MAP
( (
addr_width => RAM_ADDR_WIDTH, addr_width => RAM_ADDR_WIDTH,
@@ -456,18 +475,15 @@ inst_ram : entity work.dpram_2w2r
) )
PORT MAP PORT MAP
( (
clk_a => clk, clka => clk,
clk_b => clk, clkb => clk,
en_a => ram_en_a, en_a => ram_en_b,
en_b => ram_en_b, en_b => ram_en_a,
we_a => ram_we_a, we_a => ram_we_b,
we_b => ram_we_b, addr_a => ram_addr_b,
addr_a => ram_addr_a, addr_b => ram_addr_a,
addr_b => ram_addr_b, din_a => ram_din_b,
din_a => ram_din_a, dout_b => ram_dout_a
din_b => ram_din_b,
dout_a => ram_dout_a,
dout_b => ram_dout_b
); );
-- Instantiate synchronous FIFO -- Instantiate synchronous FIFO
@@ -498,19 +514,45 @@ inst_sipo : entity work.sipo
( (
data_width_in => 8, data_width_in => 8,
data_width_out => 32, data_width_out => 32,
msb_first => false msb_first => true
) )
PORT MAP PORT MAP
( (
rst => sipo_rst, rst => sipo_rst,
clk => mii_rx_clk, clk => mii_rx_clk,
enable => '1', din_vld => sipo_10mbps_dout_vld,
din_en => mii_rx_dv, din_en => sipo_10mbps_dout_en,
din => mii_rx, din => sipo_10mbps_dout,
dout_be => sipo_dout_be, dout_be => sipo_dout_be,
dout_vld => sipo_dout_vld, dout_vld => sipo_dout_vld,
dout => sipo_dout dout => sipo_dout,
dout_en => sipo_dout_en
);
sipo_rst <= rst or word_count_set;
inst_sipo_10mbps : entity work.sipo
GENERIC MAP
(
data_width_in => 4,
data_width_out => 8,
msb_first => false
)
PORT MAP
(
rst => sipo_10mbps_rst,
clk => mii_rx_clk,
din_vld => mii_rx_dv,
din_en => mii_rx_dv,
din => mii_rx(3 downto 0),
dout_be => open,
dout_vld => sipo_10mbps_dout_vld,
dout => sipo_10mbps_dout,
dout_en => sipo_10mbps_dout_en
); );
sipo_10mbps_rst <= rst or word_count_set;
end behavior; end behavior;
lib/emac/src/emac_tx.vhd
+36 -11
View File
@@ -101,6 +101,10 @@ ARCHITECTURE behavior OF emac_tx IS
signal piso_din_be : unsigned(3 downto 0); signal piso_din_be : unsigned(3 downto 0);
signal piso_din_rdy : std_logic; signal piso_din_rdy : std_logic;
signal data_vld : std_logic; signal data_vld : std_logic;
signal piso_dout : unsigned(7 downto 0);
signal piso_dout_vld : std_logic;
signal piso_10mbps_din_rdy : std_logic;
subtype inter_frame_gap_cnt_t is natural range 0 to natural(1.0*f_sysclk)-1; subtype inter_frame_gap_cnt_t is natural range 0 to natural(1.0*f_sysclk)-1;
signal inter_frame_gap_cnt : inter_frame_gap_cnt_t; signal inter_frame_gap_cnt : inter_frame_gap_cnt_t;
@@ -134,7 +138,7 @@ begin
ram_din_a <= din; ram_din_a <= din;
ram_addr_a <= fill_ptr; ram_addr_a <= fill_ptr;
piso_din_be <= (others => '1'); piso_din_be <= mii_fifo_dout(35 downto 32);
mii_fifo_re <= piso_din_rdy; mii_fifo_re <= piso_din_rdy;
data_vld <= not mii_fifo_empty; data_vld <= not mii_fifo_empty;
@@ -474,7 +478,7 @@ xfer_pointer:
end process; end process;
------------------------------------------------------------------ ------------------------------------------------------------------
inst_ram : entity work.dpram_2w2r inst_ram : entity work.dpram_1w1r
GENERIC MAP GENERIC MAP
( (
addr_width => RAM_ADDR_WIDTH, addr_width => RAM_ADDR_WIDTH,
@@ -482,17 +486,14 @@ inst_ram : entity work.dpram_2w2r
) )
PORT MAP PORT MAP
( (
clk_a => clk, clka => clk,
clk_b => clk, clkb => clk,
en_a => ram_en_a, en_a => ram_en_a,
en_b => ram_en_b, en_b => ram_en_b,
we_a => ram_we_a, we_a => ram_we_a,
we_b => ram_we_b,
addr_a => ram_addr_a, addr_a => ram_addr_a,
addr_b => ram_addr_b, addr_b => ram_addr_b,
din_a => ram_din_a, din_a => ram_din_a,
din_b => ram_din_b,
dout_a => ram_dout_a,
dout_b => ram_dout_b dout_b => ram_dout_b
); );
@@ -546,7 +547,7 @@ inst_piso : entity work.piso
( (
data_width_in => 32, data_width_in => 32,
data_width_out => 8, data_width_out => 8,
msb_first => false msb_first => true
) )
PORT MAP PORT MAP
( (
@@ -554,11 +555,35 @@ inst_piso : entity work.piso
clk => mii_tx_clk, clk => mii_tx_clk,
din_vld => data_vld, din_vld => data_vld,
din_rdy => piso_din_rdy, din_rdy => piso_din_rdy,
din_be => mii_fifo_dout(35 downto 32), din_be => piso_din_be,
din => mii_fifo_dout(31 downto 0), din => mii_fifo_dout(31 downto 0),
dout_en => mii_tx_en, dout_vld => piso_dout_vld,
dout => mii_tx dout_en => piso_10mbps_din_rdy,
dout => piso_dout
); );
inst_piso_10mbps : entity work.piso
GENERIC MAP
(
data_width_in => 8,
data_width_out => 4,
msb_first => false
)
PORT MAP
(
rst => rst,
clk => mii_tx_clk,
din_vld => piso_dout_vld,
din_rdy => piso_10mbps_din_rdy,
din_be => "11",
din => piso_dout,
dout_vld => mii_tx_en,
dout_en => '1',
dout => mii_tx(3 downto 0)
);
mii_tx(7 downto 4) <= "0000";
end behavior; end behavior;