- modifications for improved SIPOs and PISOs

Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@818 cc03376c-175c-47c8-b038-4cd826a8556b

lib/emac/src/emac_tx.vhd

@@ -101,6 +101,10 @@ ARCHITECTURE behavior OF emac_tx IS
 	signal piso_din_be		: unsigned(3 downto 0);
 	signal piso_din_rdy		: std_logic;
 	signal data_vld			: std_logic;
+
+	signal piso_dout			: unsigned(7 downto 0);
+	signal piso_dout_vld		: std_logic;
+	signal piso_10mbps_din_rdy	: std_logic;
 	
 	subtype inter_frame_gap_cnt_t is natural range 0 to natural(1.0*f_sysclk)-1;
 	signal inter_frame_gap_cnt	: inter_frame_gap_cnt_t;
@@ -134,7 +138,7 @@ begin
 	ram_din_a				<= din;
 	ram_addr_a				<= fill_ptr;
 	
-	piso_din_be				<= (others => '1');
+	piso_din_be				<= mii_fifo_dout(35 downto 32);
 	mii_fifo_re				<= piso_din_rdy;
 	data_vld				<= not mii_fifo_empty;
 	
@@ -474,7 +478,7 @@ xfer_pointer:
 	end process;	
 	
 ------------------------------------------------------------------
-inst_ram : entity work.dpram_2w2r
+inst_ram : entity work.dpram_1w1r
 	GENERIC MAP 
 	(
 		addr_width	=> RAM_ADDR_WIDTH,
@@ -482,17 +486,14 @@ inst_ram : entity work.dpram_2w2r
 	)
 	PORT MAP 
 	(
-		clk_a		=> clk,
-		clk_b		=> clk,
+		clka		=> clk,
+		clkb		=> clk,
 		en_a		=> ram_en_a,
 		en_b		=> ram_en_b,
 		we_a		=> ram_we_a,
-		we_b		=> ram_we_b,
 		addr_a		=> ram_addr_a,
 		addr_b		=> ram_addr_b,
 		din_a		=> ram_din_a,
-		din_b		=> ram_din_b,
-		dout_a		=> ram_dout_a,
 		dout_b		=> ram_dout_b
 	);
 
@@ -546,7 +547,7 @@ inst_piso : entity work.piso
 	(
 		data_width_in	=> 32,
 		data_width_out	=> 8,
-		msb_first		=> false
+		msb_first		=> true
 	)
 	PORT MAP
 	(
@@ -554,11 +555,35 @@ inst_piso : entity work.piso
 		clk			=> mii_tx_clk,
 		din_vld		=> data_vld,
 		din_rdy		=> piso_din_rdy,
-		din_be		=> mii_fifo_dout(35 downto 32),
+		din_be		=> piso_din_be,
 		din			=> mii_fifo_dout(31 downto 0),
-		dout_en		=> mii_tx_en,
-		dout		=> mii_tx
+		dout_vld	=> piso_dout_vld,
+		dout_en		=> piso_10mbps_din_rdy,
+		dout		=> piso_dout
 		
 	);
 
+inst_piso_10mbps : entity work.piso
+	GENERIC MAP
+	(
+		data_width_in	=> 8,
+		data_width_out	=> 4,
+		msb_first		=> false
+	)
+	PORT MAP
+	(
+		rst			=> rst,
+		clk			=> mii_tx_clk,
+		din_vld		=> piso_dout_vld,
+		din_rdy		=> piso_10mbps_din_rdy,
+		din_be		=> "11",
+		din			=> piso_dout,
+		dout_vld	=> mii_tx_en,
+		dout_en		=> '1',
+		dout		=> mii_tx(3 downto 0)
+		
+	);
+
+	mii_tx(7 downto 4)	<= "0000";
+
 end behavior;