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- simplified xfer-fsm, preamble, sipo32, etc

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git-svn-id: http://moon:8086/svn/vhdl/trunk@872 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-04-07 17:55:26 +00:00
parent 4b88e122f2
commit 3a58fbb7af
1 changed files with 29 additions and 32 deletions
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lib/emac/src/emac_rx.vhd
+29 -32
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@@ -85,12 +85,11 @@ ARCHITECTURE behavior OF emac_rx IS
signal sipo8_en : std_logic;
signal byte_count_rst : std_logic;
signal byte_count_en : std_logic;
signal byte_count : word_ptr_t;
signal reset_pipe : unsigned(31 downto 0);
signal preamble_rst : std_logic;
signal preamble_en : std_logic;
signal preamble_rdy : std_logic;
signal preamble_bsy : std_logic;
signal preamble_OK : std_logic;
@@ -98,7 +97,6 @@ ARCHITECTURE behavior OF emac_rx IS
signal mac_chk_rdy : std_logic;
signal mac_chk_BC : std_logic;
signal mac_chk_OK : std_logic;
signal mac_chk_rst : std_logic;
signal mac_chk_num_OK : natural range 0 to 6;
signal mac_chk_num_BC : natural range 0 to 6;
signal mac_chk_cnt : natural range 0 to 5;
@@ -106,11 +104,12 @@ ARCHITECTURE behavior OF emac_rx IS
signal mac_chk_addr : mac_addr_t;
signal Gbps_en : std_logic;
signal rx_en : std_logic;
type host_state_t is (host_init, host_flush, host_idle);
signal host_s, host_sn : host_state_t;
type xfer_state_t is (xfer_init, xfer_reset, xfer_idle, xfer_setup, xfer_active, xfer_finish, xfer_commit);
type xfer_state_t is (xfer_init, xfer_idle, xfer_preamble, xfer_setup, xfer_active, xfer_finish, xfer_commit);
signal xfer_s, xfer_sn : xfer_state_t;
alias cmd_mac_ok_in is cmd_fifo_din(cmd_fifo_din'left);
@@ -261,7 +260,7 @@ byte_counter:
if rising_edge(mii_rx_clk) then
if byte_count_rst = '1' then
byte_count <= (others => '0');
elsif byte_count_en = '1' and sipo32_din_vld = '1' then
elsif sipo32_en = '1' and sipo32_din_vld = '1' then
byte_count <= byte_count + 1;
end if;
end if;
@@ -271,7 +270,7 @@ preamble_sync_logic:
process(mii_rx_clk)
begin
if rising_edge(mii_rx_clk) then
if preamble_rst = '1' then
if preamble_en = '0' then
preamble_rdy <= '0';
preamble_bsy <= '0';
preamble_OK <= '0';
@@ -295,7 +294,7 @@ mac_check_logic:
process(mii_rx_clk)
begin
if rising_edge(mii_rx_clk) then
if mac_chk_rst = '1' then
if byte_count_rst = '1' then
mac_chk_rdy <= '0';
mac_chk_OK <= '0';
mac_chk_BC <= '0';
@@ -310,7 +309,7 @@ mac_check_logic:
if mac_chk_num_BC = 6 then
mac_chk_BC <= '1';
end if;
elsif sipo32_din_vld = '1' then
elsif sipo32_din_vld = '1' and sipo32_en = '1' then
if sipo32_din = mac_chk_addr(mac_chk_cnt) then
mac_chk_num_OK <= mac_chk_num_OK + 1;
end if;
@@ -340,58 +339,56 @@ xfer_state_next:
end process;
xfer_state:
process(xfer_s, sipo32_en, sipo32_dout_en, preamble_rdy, preamble_OK, xfer_ram_full)
process(xfer_s, rx_en, sipo32_dout_en, preamble_bsy, preamble_OK, xfer_ram_full)
begin
commit_en <= '0';
xfer_set <= '0';
xfer_en <= '0';
sipo32_rst <= '0';
sipo32_en <= '0';
byte_count_rst <= '0';
preamble_rst <= '0';
mac_chk_rst <= '0';
byte_count_en <= '0';
preamble_en <= '0';
xfer_sn <= xfer_s;
case xfer_s is
when xfer_init =>
if sipo32_en = '0' then
xfer_sn <= xfer_reset;
sipo32_rst <= '1';
if rx_en = '0' then
xfer_sn <= xfer_idle;
end if;
when xfer_reset =>
sipo32_rst <= '1';
preamble_rst <= '1';
byte_count_rst <= '1';
xfer_sn <= xfer_idle;
when xfer_idle =>
if preamble_rdy = '1' then
preamble_en <= rx_en;
if preamble_bsy = '1' then
xfer_sn <= xfer_preamble;
end if;
when xfer_preamble =>
preamble_en <= rx_en;
byte_count_rst <= preamble_bsy;
sipo32_en <= rx_en and not preamble_bsy;
if preamble_bsy = '0' then
xfer_sn <= xfer_init;
if preamble_OK = '1' then
byte_count_en <= sipo32_en;
mac_chk_rst <= '1';
sipo32_rst <= '1';
xfer_sn <= xfer_setup;
end if;
end if;
when xfer_setup =>
xfer_set <= '1';
byte_count_en <= sipo32_en;
sipo32_en <= rx_en;
xfer_en <= sipo32_dout_en;
xfer_sn <= xfer_active;
when xfer_active =>
byte_count_en <= sipo32_en;
xfer_en <= sipo32_dout_en;
byte_count_en <= sipo32_en;
sipo32_en <= rx_en;
if xfer_ram_full = '1' then
xfer_sn <= xfer_init;
elsif sipo32_en = '0' then
elsif rx_en = '0' then
xfer_sn <= xfer_finish;
end if;
@@ -481,12 +478,12 @@ mii_input_register:
if rising_edge(mii_rx_clk) then
if Gbps_en = '1' then
sipo32_din <= mii_rx;
sipo32_din_vld <= mii_rx_dv;
sipo32_en <= not mii_rx_er;
sipo32_din_vld <= not mii_rx_er;
rx_en <= mii_rx_dv;
else
sipo32_din <= sipo8_dout;
sipo32_din_vld <= sipo8_dout_vld;
sipo32_en <= sipo8_dout_en;
rx_en <= sipo8_dout_en;
end if;
end if;
end process;