diff --git a/lib/uart/uart_wb.vhd b/lib/uart/uart_wb.vhd
index 0d69a0d..1aa646b 100644
--- a/lib/uart/uart_wb.vhd
+++ b/lib/uart/uart_wb.vhd
@@ -55,7 +55,7 @@ ARCHITECTURE behavior OF uart_wb IS
 	END COMPONENT;
 
 	-- Signals for UART connections
-	signal baud_count		: unsigned(7 downto 0);
+	signal baud_count		: unsigned(15 downto 0);
 	signal en_16_x_baud		: std_logic;
 	signal reg_we_uart_tx	: std_logic;
 	signal tx_full			: std_logic;
@@ -67,7 +67,7 @@ ARCHITECTURE behavior OF uart_wb IS
 	signal rx_full			: std_logic;
 	signal rx_half_full		: std_logic;
 	signal uart_status_port	: unsigned(7 downto 0);
-	signal reg_uart_baud	: unsigned(7 downto 0);
+	signal reg_uart_baud	: unsigned(15 downto 0);
 	signal rx_int_en		: std_logic;
 	signal tx_int_en		: std_logic;
 
@@ -97,7 +97,7 @@ registers_write:
 					tx_int_en		<= DAT_I(5);
 
 				when "0010" =>
-					reg_uart_baud	<= DAT_I(7 downto 0);
+					reg_uart_baud	<= DAT_I(15 downto 0);
 
 				when others => null;
 				end case;
@@ -124,7 +124,7 @@ registers_read:
 					DAT_O(7 downto 0)	<= uart_status_port;
 
 				when "0010" =>
-					DAT_O(7 downto 0)	<= reg_uart_baud;
+					DAT_O(15 downto 0)	<= reg_uart_baud;
 
 				when others => null;
 				end case;