diff --git a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
index 2021c44..8ccd526 100644
--- a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
+++ b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
@@ -309,20 +309,22 @@ proc_stage_pc_next:
 			branch_ce	<= '0';
 			cop_ctrl.exc_left		<= '0';
 			if rst = '1' then
-				pc.nxt	<= RESET_VECTOR;
-				pc.last	<= RESET_VECTOR;
-			elsif cop_stat.exc_commit = '1' then
-				pc.nxt	<= cop_stat.exc_vec;
-			elsif sdu.ID_stall = '0' then
-				cop_ctrl.exc_left		<= cop_stat.exc_exit;
-				branch_ce	<= '1';
+				pc.nxt	<= pc.curr;
 				pc.last	<= pc.curr;
-				if ID_stage.ctrl.jump = '1' then
-					pc.nxt	<= ID_stage.jimm32;
-				elsif ID_stage.ctrl.jump_long = '1' then
-					pc.nxt	<= ID_stage.reg_a;
-				else
-					pc.nxt	<= pc.curr + 4;
+			else
+				if cop_stat.exc_commit = '1' then
+					pc.nxt	<= cop_stat.exc_vec;
+				elsif sdu.ID_stall = '0' then
+					cop_ctrl.exc_left		<= cop_stat.exc_exit;
+					branch_ce	<= '1';
+					pc.last	<= pc.curr;
+					if ID_stage.ctrl.jump = '1' then
+						pc.nxt	<= ID_stage.jimm32;
+					elsif ID_stage.ctrl.jump_long = '1' then
+						pc.nxt	<= ID_stage.reg_a;
+					else
+						pc.nxt	<= pc.curr + 4;
+					end if;
 				end if;
 			end if;
 		end if;