- Intital revision
git-svn-id: http://moon:8086/svn/vhdl/trunk@179 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
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vmap ieee_proposed ../../../Common/sim/ieee_proposed
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vlib work
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vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd"
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vcom -explicit -93 "../../../lib/fixed/fixed_util_pkg.vhd"
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vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
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vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
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vcom -explicit -93 "../src/filter_pkg.vhd"
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vcom -explicit -93 "../src/fir_stage_pkg.vhd"
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vcom -explicit -93 "../src/fir_stage_sys.vhd"
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vcom -explicit -93 "../src/tb_fir_stage_sys.vhd"
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vsim -t 1ps -lib work tb_fir_stage_sys
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do {tb_fir_stage_sys.wdo}
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view wave
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view structure
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view signals
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run 2us
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@@ -0,0 +1,28 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -format Logic /tb_fir_stage_sys/clk
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add wave -noupdate -divider Input
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add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/x_in
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add wave -noupdate -format Literal /tb_fir_stage_sys/xi
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add wave -noupdate -divider Output
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add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/y_out
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add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_fir_stage_sys/yo
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add wave -noupdate -divider {Stage signals}
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add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/x
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add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/y
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {1060000 ps} 0}
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configure wave -namecolwidth 140
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configure wave -valuecolwidth 100
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configure wave -justifyvalue left
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configure wave -signalnamewidth 1
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 1
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configure wave -griddelta 40
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configure wave -timeline 0
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update
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WaveRestoreZoom {706931 ps} {1268317 ps}
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@@ -0,0 +1,125 @@
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--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 12:16:14 10/02/05
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-- Design Name:
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-- Module Name: fir_stage - Behavioral
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-- Project Name:
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.MATH_REAL.ALL;
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USE ieee.numeric_std.ALL;
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library ieee_proposed;
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use ieee_proposed.math_utility_pkg.all;
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use ieee_proposed.fixed_pkg.all;
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library work;
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use work.utils_pkg.all;
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use work.fixed_util_pkg.all;
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use work.fir_stage_pkg.all;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity fir_stage_sys is
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Generic
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(
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nbits_in : integer := 12;
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nbits_in_frac : integer := 12;
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nbits_out : integer := 12;
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nbits_out_frac : integer := 12;
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input_latency : integer := 1;
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pipe_latency : integer := 2
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);
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Port
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(
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clk : in std_logic;
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x_in : in sfixed;
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y_in : in sfixed;
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h_in : in sfixed;
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x_out : out sfixed;
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y_out : out sfixed
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);
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end fir_stage_sys;
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architecture Behavioral of fir_stage_sys is
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constant min_input_lat : integer := 1;
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constant min_pipe_lat : integer := 2;
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constant mult_latency : integer := pipe_latency-1;
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subtype in_t is sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
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subtype out_t is sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
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type input_pipe_t is array (0 to input_latency) of in_t;
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type mult_pipe_t is array (0 to mult_latency) of out_t;
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signal x_pipe : input_pipe_t;
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signal mult_pipe : mult_pipe_t;
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signal xin : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
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signal yin : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
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signal hin : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
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signal prod : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
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------------------------------------------------------------
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begin
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assert input_latency >= min_input_lat report "Input latency must be greater than " & natural'image(min_input_lat-1) & "!" severity error;
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assert pipe_latency >= min_pipe_lat report "Pipe latency must be greater than " & natural'image(min_pipe_lat-1) & "!" severity error;
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prod <= mult_pipe(mult_latency);
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yin <= resize(y_in, yin);
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hin <= resize(h_in, hin);
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xin <= x_pipe(input_latency);
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x_out <= resize(xin, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac));
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------------------------------------------------------------
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proc_in_reg: process(clk, x_in)
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begin
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x_pipe(0) <= resize(x_in, x_pipe(0));
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if rising_edge(clk) then
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for i in 1 to input_latency loop
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x_pipe(i) <= x_pipe(i-1);
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end loop;
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end if;
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end process;
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------------------------------------------------------------
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proc_pipe_reg: process(clk, xin, hin)
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begin
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mult_pipe(0) <= resize(xin * hin, mult_pipe(0));
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if rising_edge(clk) then
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for i in 1 to mult_latency loop
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mult_pipe(i) <= mult_pipe(i-1);
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end loop;
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end if;
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end process;
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------------------------------------------------------------
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proc_out_reg: process(clk)
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variable yout : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
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begin
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if rising_edge(clk) then
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yout := resize(yin + prod, yout, fixed_wrap, fixed_truncate);
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y_out <= yout;
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end if;
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end process;
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------------------------------------------------------------
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end Behavioral;
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@@ -0,0 +1,222 @@
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--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 17:16:42 13.05.2007
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-- Design Name: tb_fir_stage
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-- Module Name: tb_fir_stage.vhd
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-- Project Name: fir_stage
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.MATH_REAL.ALL;
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USE ieee.numeric_std.ALL;
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use std.textio.all; -- Imports the standard textio package.
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library ieee_proposed;
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use ieee_proposed.math_utility_pkg.all;
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use ieee_proposed.fixed_pkg.all;
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library work;
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use work.fixed_util_pkg.all;
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use work.fir_stage_pkg.all;
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use work.filter_pkg.all;
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use work.PCK_FIO.all;
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ENTITY tb_fir_stage_sys IS
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Generic
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(
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ntaps : integer := 33;
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nbits_in : integer := 24;
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nbits_in_frac : integer := 23;
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nbits_stages : integer := 25;
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nbits_stages_frac : integer := 23;
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nbits_out : integer := 24;
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nbits_out_frac : integer := 22
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);
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END tb_fir_stage_sys;
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ARCHITECTURE behavior OF tb_fir_stage_sys IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT fir_stage_sys
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GENERIC
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(
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nbits_in : integer;
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nbits_in_frac : integer;
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nbits_out : integer;
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nbits_out_frac : integer;
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input_latency : integer;
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pipe_latency : integer
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);
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PORT
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(
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clk : in std_logic;
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x_in : in sfixed;
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y_in : in sfixed;
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h_in : in sfixed;
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x_out : out sfixed;
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y_out : out sfixed
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);
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END COMPONENT;
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type stages_t is array (natural range <>) of sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
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--Constants
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constant PERIOD : time := 10 ns;
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constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac);
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--Inputs
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SIGNAL clk : std_logic := '0';
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SIGNAL x_in : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
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--Outputs
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SIGNAL x_out : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
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SIGNAL y_out : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
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SIGNAL x : stages_t(0 to ntaps-2);
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SIGNAL y : stages_t(0 to ntaps-2);
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SIGNAL fileout_enable : std_logic := '1';
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-- Test coefficients
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function to_sfixed(x_real : real_array_t) return stages_t is
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variable res : stages_t(x_real'range);
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begin
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for i in x_real'range loop
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res(i) := to_sfixed(x_real(i), res(i), fixed_wrap, fixed_round);
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end loop;
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return res;
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end to_sfixed;
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constant h : stages_t(0 to ntaps-1) := to_sfixed(FilterCoef_Lowpass(ntaps, 0.25, 1.0));
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SIGNAL xi, yo : real := 0.0;
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BEGIN
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xi <= to_real(x_in);
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yo <= to_real(y_out);
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----------------------------------------
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-- Instantiate the Unit Under Test (UUT)
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----------------------------------------
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uut_first_stage_sys: fir_stage_sys
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GENERIC MAP
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(
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nbits_in => nbits_in,
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nbits_in_frac => nbits_in_frac,
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nbits_out => nbits_stages,
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nbits_out_frac => nbits_stages_frac,
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input_latency => 1,
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pipe_latency => 2
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)
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PORT MAP
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(
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clk => clk,
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x_in => x_in,
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y_in => zero_in,
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h_in => h(ntaps-1),
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x_out => x(0),
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y_out => y(0)
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);
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----------------------------------------
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gen_stages:
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for i in 1 to ntaps-2 generate
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uut_stages: fir_stage_sys
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GENERIC MAP
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(
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nbits_in => nbits_stages,
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nbits_in_frac => nbits_stages_frac,
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nbits_out => nbits_stages,
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nbits_out_frac => nbits_stages_frac,
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input_latency => 2,
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pipe_latency => 2
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)
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PORT MAP
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(
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clk => clk,
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x_in => x(i-1),
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y_in => y(i-1),
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h_in => h(ntaps-i-1),
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x_out => x(i),
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y_out => y(i)
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);
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end generate;
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----------------------------------------
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uut_last_stage: fir_stage_sys
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GENERIC MAP
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(
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nbits_in => nbits_stages,
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nbits_in_frac => nbits_stages_frac,
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nbits_out => nbits_out,
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nbits_out_frac => nbits_out_frac,
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input_latency => 2,
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pipe_latency => 2
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)
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PORT MAP
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(
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clk => clk,
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x_in => x(ntaps-2),
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y_in => y(ntaps-2),
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h_in => h(0),
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x_out => x_out,
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y_out => y_out
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);
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----------------------------------------
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-- Finished instantiation
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----------------------------------------
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tb_clk : PROCESS
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BEGIN
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clk <= not clk;
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wait for PERIOD/2;
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END PROCESS;
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tb : PROCESS
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BEGIN
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-- Wait 100 ns for global reset to finish
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wait for 4*PERIOD;
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x_in <= to_sfixed(0.0, x_in);
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wait for 40*PERIOD;
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wait until rising_edge(clk);
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x_in <= to_sfixed(0.0, x_in);
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wait until rising_edge(clk);
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x_in <= to_sfixed(1.0, x_in);
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wait until rising_edge(clk);
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x_in <= to_sfixed(0.0, x_in);
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wait until rising_edge(clk);
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x_in <= to_sfixed(0.0, x_in);
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wait until rising_edge(clk);
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x_in <= to_sfixed(0.0, x_in);
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wait for 150*PERIOD;
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assert false report "Test finished" severity error;
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wait;
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END PROCESS;
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tb_fo : PROCESS(clk, fileout_enable)
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file RESULT_FIR: text open write_mode is "fir.txt";
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variable L: line;
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BEGIN
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if rising_edge(clk) and fileout_enable = '1' then
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fprint(RESULT_FIR, L,"%s\n", REAL'image(yo));
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end if;
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END PROCESS;
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END;
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Reference in New Issue
Block a user