diff --git a/lib/filter/src/delay_line.vhd b/lib/filter/src/delay_line.vhd
index a05e317..c33ad60 100644
--- a/lib/filter/src/delay_line.vhd
+++ b/lib/filter/src/delay_line.vhd
@@ -83,18 +83,17 @@ counter:
 		end if;
 	end process;
 
-	inst_dpram_1w1r: entity work.dpram_1w1r
+	inst_dpram_1w1r: entity work.dpram_1w1r2c_ro
 	GENERIC MAP
 	(
 		addr_width	=> NextExpBaseTwo(ntaps),
 		data_width	=> nbits
 	)
 	PORT MAP (
-		clka	=> clk,
-		clkb	=> clk,
-		en_a	=> '1',
-		en_b	=> '1',
+		clk_a	=> clk,
+		clk_b	=> clk,
 		we_a	=> shift_en,
+		re_b	=> '1',
 		addr_a	=> addr_w,
 		addr_b	=> addr_r,
 		din_a	=> ram_w,
diff --git a/lib/filter/src/fir_semi_parallel.vhd b/lib/filter/src/fir_semi_parallel.vhd
index 68493c1..948a947 100644
--- a/lib/filter/src/fir_semi_parallel.vhd
+++ b/lib/filter/src/fir_semi_parallel.vhd
@@ -209,18 +209,17 @@ gen_coef_ram:
 	begin
 		addr_a	<= coef_addr(addr_a'length-1 downto 0);
 		addr_b <= to_unsigned(count_array(i), addr_b'length);
-		inst_coef_ram: entity work.dpram_1w1r
+		inst_coef_ram: entity work.dpram_1w1r2c_ro
 		GENERIC MAP 
 		(
 			addr_width	=> NextExpBaseTwo(ntaps_per_stage),
 			data_width	=> nbits_stages
 		)
 		PORT MAP (
-			clka	=> clk,
-			clkb	=> clk,
-			en_a	=> '1',
-			en_b	=> '1',
+			clk_a	=> clk,
+			clk_b	=> clk,
 			we_a	=> coef_we(i),
+			re_b	=> '1',
 			addr_a	=> addr_a,
 			addr_b	=> addr_b,
 			din_a	=> coef_din,