From 36e1738f34710eec7cf9946d97c6811648de80bb Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Wed, 24 Mar 2021 09:31:51 +0000 Subject: [PATCH] - added COMPONENT declaration for mt46v16m16 git-svn-id: http://moon:8086/svn/vhdl/trunk@1508 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb32.vhd | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb32.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb32.vhd index 87d0e88..18509b8 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb32.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb32.vhd @@ -71,6 +71,23 @@ architecture struct of tb_ctrl_ddr_wb32 is type sd_cmd_t is (nop, lmr, ar, pre, act, write, read, bst); signal sd_cmd : sd_cmd_t; + + COMPONENT mt46v16m16 + PORT ( + Dq : INOUT STD_LOGIC_VECTOR (PART_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS => 'Z'); + Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; + Addr : IN STD_LOGIC_VECTOR (PART_ADDR_WIDTH - 1 DOWNTO 0); + Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + Clk : IN STD_LOGIC; + Clk_n : IN STD_LOGIC; + Cke : IN STD_LOGIC; + Cs_n : IN STD_LOGIC; + Ras_n : IN STD_LOGIC; + Cas_n : IN STD_LOGIC; + We_n : IN STD_LOGIC; + Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + END COMPONENT; begin