diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb32.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb32.vhd
index 87d0e88..18509b8 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb32.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb32.vhd
@@ -71,6 +71,23 @@ architecture struct of tb_ctrl_ddr_wb32 is
 
 	type sd_cmd_t is (nop, lmr, ar, pre, act, write, read, bst);
 	signal sd_cmd : sd_cmd_t;
+
+	COMPONENT mt46v16m16
+		PORT (
+		    Dq    : INOUT STD_LOGIC_VECTOR (PART_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS => 'Z');
+		    Dqs   : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
+		    Addr  : IN    STD_LOGIC_VECTOR (PART_ADDR_WIDTH - 1 DOWNTO 0);
+		    Ba    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0);
+		    Clk   : IN    STD_LOGIC;
+		    Clk_n : IN    STD_LOGIC;
+		    Cke   : IN    STD_LOGIC;
+		    Cs_n  : IN    STD_LOGIC;
+		    Ras_n : IN    STD_LOGIC;
+		    Cas_n : IN    STD_LOGIC;
+		    We_n  : IN    STD_LOGIC;
+		    Dm    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0)
+		);
+	END COMPONENT;
 	
 begin