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- refactored clockgen for De0-nano

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1383 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2017-02-05 10:47:45 +00:00
parent 43e83aa8df
commit 364a66b1d3
2 changed files with 21 additions and 33 deletions
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lib/SDRAM/ddr_sdr_v1_5/src/sdr_clk_cycloneive.vhd
+20 -12
View File
@@ -56,9 +56,9 @@ entity sdram_clk is
rst : in std_logic; -- external async reset, low active
clk_in : in std_logic; -- system clock (e.g. 100MHz), from board
clk_fb_in : in std_logic; -- feedback clock
clk0_0_out : out std_logic; -- System clock #0, dcm#0 output 0°
clk1_0_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
locked_out : out std_logic -- DCM locked status
clk0_0_out : out std_logic; -- System clock #0, dcm#0 output 0�
clk1_0_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0�
rst0_0_out : out std_logic -- Reset output
);
end;
@@ -69,9 +69,9 @@ ARCHITECTURE SYN OF sdram_clk IS
SIGNAL sub_wire2_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL clk0 : STD_LOGIC ;
SIGNAL clk1 : STD_LOGIC ;
SIGNAL locked : STD_LOGIC ;
@@ -150,11 +150,10 @@ BEGIN
sub_wire2 <= To_stdlogicvector(sub_wire2_bv);
sub_wire0 <= clk_in;
sub_wire1 <= sub_wire2(0 DOWNTO 0) & sub_wire0;
sub_wire5 <= sub_wire3(1);
sub_wire4 <= sub_wire3(0);
clk0_0_out <= sub_wire4;
clk1_0_out <= sub_wire5;
locked_out <= sub_wire6;
clk1 <= sub_wire3(1);
clk0 <= sub_wire3(0);
clk0_0_out <= clk0;
clk1_0_out <= clk1;
altpll_component : altpll
GENERIC MAP (
@@ -222,9 +221,18 @@ BEGIN
areset => rst,
inclk => sub_wire1,
clk => sub_wire3,
locked => sub_wire6
locked => locked
);
rst0_gen:
process(locked, clk0)
begin
if locked = '0' then
rst0_0_out <= '1';
elsif rising_edge(clk0) then
rst0_0_out <= '0';
end if;
end process;
END SYN;
lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_de0nano.vhd
+1 -21
View File
@@ -72,11 +72,6 @@ architecture tech of sdram_phy is
signal rst0 : std_logic;
signal clk0_rd : std_logic;
signal locked : std_logic;
signal error : std_logic;
signal reset_counter : unsigned(7 downto 0) := (others => '1');
signal reset : STD_LOGIC := '1';
signal re_cl_pipe : unsigned(TCAS+1 downto 0); -- +2 = number of pipe registers used here
type u_tag_array_t is array (natural range 0 to TCAS+2) of user_tag_t;
@@ -115,24 +110,9 @@ inst_sdram_clk : entity work.sdram_clk
clk_in => clk, -- system clock (e.g. 100MHz), from board
clk_fb_in => clk_fb, -- feedback clock
clk0_0_out => clk0_temp, -- System clock #0, dcm#0 output 0°
clk1_0_out => clk0_rd, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
clk1_0_out => clk0_rd, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
rst0_0_out => rst0 -- Reset out
);
rst0_gen:
process(locked, clk0)
begin
if locked = '0' then
rst0 <= '1';
reset_counter <= (others => '1');
elsif rising_edge(clk0) then
if (reset_counter /= 0) then
reset_counter <= reset_counter - 1;
else
rst0 <= '0';
end if;
end if;
end process;
------------------------------------------------------------------------------------------------------------------------------------------------
utag_pipe: