- added J-UART

git-svn-id: http://moon:8086/svn/vhdl/trunk@1341 cc03376c-175c-47c8-b038-4cd826a8556b
2016-12-17 17:54:33 +00:00
parent c8567cfede
commit 3638a97abf
8 changed files with 610 additions and 0 deletions
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+-- UART Receiver
+--
+-- Version : 1.00 
+-- Version Date : 15 December 2016
+--
+------------------------------------------------------------------------------------
+--
+-- Library declarations
+--
+-- The Unisim Library is used to define Xilinx primitives. It is also used during
+-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+--
+------------------------------------------------------------------------------------
+--
+-- Main Entity
+--
+entity juart_rx is
+    Port (      serial_in : in std_logic;  
+                 data_out : out unsigned(7 downto 0);
+              data_strobe : out std_logic;
+             en_16_x_baud : in std_logic;
+                      clk : in std_logic;
+                      rst : in std_logic);
+    end juart_rx;
+--
+------------------------------------------------------------------------------------
+--
+-- Start of Main Architecture
+--	 
+architecture behavior of juart_rx is
+--
+------------------------------------------------------------------------------------
+--
+------------------------------------------------------------------------------------
+--
+-- Signals used
+--
+------------------------------------------------------------------------------------
+--
+signal bit_count_rst	    : std_logic;
+signal bit_count			: natural range 0 to 15;
+signal data_valid		    : std_logic;
+signal shiftreg_en		    : std_logic;
+signal shiftreg				: unsigned (7 downto 0);
+signal sample_count_rst		: std_logic;
+signal sample_count			: unsigned (15 downto 0);
+signal idle_count			: natural range 0 to 15;
+signal is_idle				: std_logic;
+signal bit_sample		    : std_logic;
+
+type state_t is	(idle, wait_start, start, shift, stop);
+
+signal state		: state_t;
+signal state_next	: state_t;
+--
+--	
+begin
+
+bit_sample	<= sample_count(8);
+is_idle		<= '1' when idle_count = 0 else '0';
+
+data_out_reg:
+process(clk)
+begin
+	if rising_edge(clk) then
+		data_strobe	<= '0';
+		if data_valid = '1' then
+			data_out 	<= shiftreg;
+			data_strobe	<= '1';
+		end if;
+	end if;
+end process;
+
+proc_state_next:
+process(clk)
+begin
+	if rising_edge(clk) then
+		if rst = '1' then
+			state		<= idle;
+		else
+			state	<= state_next;
+		end if;
+	end if;
+end process;
+
+statemachine:
+process(state, is_idle, bit_count, bit_sample, serial_in)
+begin
+	state_next	<= state;
+	sample_count_rst	<= '1';
+	bit_count_rst		<= '1';
+	shiftreg_en			<= '0';
+	data_valid			<= '0';
+	
+	case state is
+	when idle =>
+		if is_idle = '1' then
+			state_next	<= wait_start;
+		end if;
+	when wait_start =>
+		if serial_in = '0' then
+			sample_count_rst	<= '0';
+			state_next	<= start;
+		end if;
+	when start =>
+		sample_count_rst	<= '0';
+		if bit_sample = '1' then
+			state_next	<= shift;
+		end if;
+	when shift =>
+		shiftreg_en			<= '1';
+		sample_count_rst	<= '0';
+		bit_count_rst		<= '0';
+		if bit_count = 8 then
+			state_next	<= stop;
+		end if;
+	when stop =>
+		state_next	<= idle;
+		data_valid	<= '1';
+		
+	when others =>
+		state_next	<= idle;
+	end case;
+end process;
+
+shift_register:
+process(clk)
+begin
+	if rising_edge(clk) then
+		if rst = '1' then
+			shiftreg	<= (others => '0');
+		elsif shiftreg_en = '1' and bit_sample = '1' then
+			shiftreg <= shiftreg(shiftreg'left-1 downto 0) & serial_in;
+		end if;
+	end if;
+end process;
+
+sample_counter:
+process(clk)
+begin
+	if rising_edge(clk) then
+		if sample_count_rst = '1' then
+			sample_count <= (sample_count'left downto 1 => '0') & '1';
+		elsif en_16_x_baud = '1' then
+			sample_count	<= sample_count(sample_count'left-1 downto 0) & sample_count(sample_count'left);
+		end if;
+	end if;
+end process;
+
+bit_counter:
+process(clk)
+begin
+	if rising_edge(clk) then
+		if bit_count_rst = '1' then
+			bit_count <= 0;
+		elsif bit_count /= 15 and bit_sample = '1' then
+			bit_count <= bit_count + 1;
+		end if;
+	end if;
+end process;
+
+idle_detector:
+process(clk)
+begin
+	if rising_edge(clk) then
+		if serial_in = '0' then
+			idle_count <= 15;
+		elsif idle_count /= 0 then
+			idle_count <= idle_count - 1;
+		else
+			idle_count <= 15;
+		end if;
+	end if;
+end process;
+
+end behavior;
+
+------------------------------------------------------------------------------------
+--
+-- END OF FILE
+--
+------------------------------------------------------------------------------------
+
+