From 360bd90d0fbb8bbf9af91151a2623ff38fe0ddef Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Thu, 4 Jun 2015 16:16:18 +0000 Subject: [PATCH] - fixed read fifo clocks git-svn-id: http://moon:8086/svn/vhdl/trunk@1286 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/spi/src/spi_master.vhd | 4 ++-- lib/spi/src/tb_spi_master.vhd | 5 +++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/lib/spi/src/spi_master.vhd b/lib/spi/src/spi_master.vhd index 5f2b164..e4b89b1 100644 --- a/lib/spi/src/spi_master.vhd +++ b/lib/spi/src/spi_master.vhd @@ -161,8 +161,8 @@ begin PORT MAP ( rst => spi_rst, - clk_w => clk, - clk_r => spi_clk, + clk_w => spi_clk, + clk_r => clk, we => read_fifo_we, re => dout_re, fifo_full => read_fifo_full, diff --git a/lib/spi/src/tb_spi_master.vhd b/lib/spi/src/tb_spi_master.vhd index fe4df17..15211d3 100644 --- a/lib/spi/src/tb_spi_master.vhd +++ b/lib/spi/src/tb_spi_master.vhd @@ -178,14 +178,15 @@ STIMULUS: process wait until rising_edge(CLK) and mst_cmd_rdy = '1'; mst_cmd_vld <= '0'; +-------------------------------------------------------- wait until rising_edge(CLK); - mst_din <= X"9000_0000"; + mst_din <= X"9F00_0000"; mst_din_vld <= '1'; wait until rising_edge(CLK) and mst_din_rdy = '1'; mst_din_vld <= '0'; wait until rising_edge(CLK); - mst_cmd <= to_cmd(16, 8); + mst_cmd <= to_cmd(32, 8); mst_cmd_vld <= '1'; wait until rising_edge(CLK) and mst_cmd_rdy = '1'; mst_cmd_vld <= '0';