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- derive sys_clk from PLL

git-svn-id: http://moon:8086/svn/vhdl/trunk@1384 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2017-02-05 11:10:29 +00:00
parent 364a66b1d3
commit 35c1a4e010
3 changed files with 41 additions and 32 deletions
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projects/mips_de0_nano/quartus/mips/JMips.qsf
+4 -2
View File
@@ -134,8 +134,6 @@ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_RO
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_clk set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_clk
set_location_assignment PIN_R8 -to sys_clk
set_location_assignment PIN_J15 -to sys_rst_n
set_location_assignment PIN_E1 -to sys_nmi_n set_location_assignment PIN_E1 -to sys_nmi_n
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_nmi_n set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_nmi_n
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_rst_n set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_rst_n
@@ -315,4 +313,8 @@ set_location_assignment PIN_M1 -to dip_sw[0]
set_location_assignment PIN_T8 -to dip_sw[1] set_location_assignment PIN_T8 -to dip_sw[1]
set_location_assignment PIN_B9 -to dip_sw[2] set_location_assignment PIN_B9 -to dip_sw[2]
set_location_assignment PIN_M15 -to dip_sw[3] set_location_assignment PIN_M15 -to dip_sw[3]
set_location_assignment PIN_R8 -to clk_brd
set_location_assignment PIN_J15 -to rst_brd_n
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_brd
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rst_brd_n
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
projects/mips_de0_nano/quartus/mips/JMips.sdc
+2 -2
View File
@@ -39,9 +39,9 @@ set_time_format -unit ns -decimal_places 3
# Create Clock # Create Clock
#************************************************************** #**************************************************************
create_clock -name {sys_clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports { sys_clk }] create_clock -name {sys_clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports { clk_brd }]
create_clock -name {SDRAM_clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {sys_sdram_clk}] create_clock -name {SDRAM_clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {sys_sdram_clk}]
create_clock -name {spi_clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {spi_clk}] create_clock -name {spi_clk} -period 15.000 -waveform { 0.000 7.500 } [get_ports {spi_clk}]
#************************************************************** #**************************************************************
projects/mips_de0_nano/quartus/mips/mips_sys.vhd
+35 -28
View File
@@ -35,13 +35,14 @@ ENTITY mips_sys IS
( (
ICACHE_SIZE : natural := 4096; -- words ICACHE_SIZE : natural := 4096; -- words
DCACHE_SIZE : natural := 4096; -- words DCACHE_SIZE : natural := 4096; -- words
F_SYSCLK : real := 50.0 F_CLK_BRD : real := 50.0;
F_CLK_SYS : real := 64.0
); );
PORT PORT
( (
sys_nmi_n : in std_logic; sys_nmi_n : in std_logic;
sys_rst_n : in std_logic; rst_brd_n : in std_logic;
sys_clk : in std_logic; clk_brd : in std_logic;
-- SDRAM signals -- SDRAM signals
sys_sdram_clk : out STD_LOGIC; sys_sdram_clk : out STD_LOGIC;
@@ -131,38 +132,44 @@ ARCHITECTURE behavior OF mips_sys IS
signal gpi0 : unsigned(31 downto 0) := (others => '0'); signal gpi0 : unsigned(31 downto 0) := (others => '0');
signal sys_nmi : STD_LOGIC; signal sys_nmi : STD_LOGIC;
signal cpu_rst : STD_LOGIC := '1'; -- pre-init for POR signal sys_rst : STD_LOGIC;
signal sys_rst : STD_LOGIC := '1'; -- pre-init for POR signal sys_clk : STD_LOGIC;
signal rst_brd : STD_LOGIC;
signal cpu_rst : STD_LOGIC := '1'; -- pre-init for POR
signal cpu_rst_count : unsigned(24 downto 0) := (others => '1'); -- pre-init for POR signal cpu_rst_count : unsigned(24 downto 0) := (others => '1'); -- pre-init for POR
signal sys_rst_count : unsigned(7 downto 0) := (others => '1'); -- pre-init for POR
BEGIN BEGIN
rst_brd <= not rst_brd_n;
sys_nmi <= not sys_nmi_n; sys_nmi <= not sys_nmi_n;
sys_leds <= cpu_debug & gpo0(5 downto 0); sys_leds <= cpu_debug & gpo0(5 downto 0);
spi_ss_n <= not spi_ss; spi_ss_n <= not spi_ss;
gpi0(11 downto 8) <= dip_sw; gpi0(11 downto 8) <= dip_sw;
sys_reset: inst_sys_clk : entity work.sdram_clk
process(sys_clk) GENERIC MAP
begin (
if rising_edge(sys_clk) then F_SDRCLK_IN => F_CLK_BRD,
if sys_rst_n = '0' then F_SDRCLK_OUT => F_CLK_SYS,
sys_rst <= '1'; clk0_out_phaseshift_ps => 0,
sys_rst_count <= (others => '1'); clk1_out_phaseshift_ps => 3000
elsif (sys_rst_count /= 0) then )
sys_rst_count <= sys_rst_count - 1; PORT MAP
else (
sys_rst <= '0'; -- Clocks and Reset
end if; rst => rst_brd, -- external async reset, low active
end if; clk_in => clk_brd, -- system clock (e.g. 100MHz), from board
end process; clk_fb_in => clk_brd, -- feedback clock
clk0_0_out => sys_clk, -- System clock #0, dcm#0 output 0°
clk1_0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
rst0_0_out => sys_rst -- Reset out
);
cpu_reset: cpu_reset:
process(sys_clk) process(sys_clk)
begin begin
if rising_edge(sys_clk) then if rising_edge(sys_clk) then
if sys_rst_n = '0' then if sys_rst = '1' then
cpu_rst <= '1'; cpu_rst <= '1';
cpu_rst_count <= (others => '1'); cpu_rst_count <= (others => '1');
elsif (cpu_rst_count /= 0) then elsif (cpu_rst_count /= 0) then
@@ -295,7 +302,7 @@ inst_rom : entity work.rom_wb
inst_gpio : entity work.gpio_wb inst_gpio : entity work.gpio_wb
GENERIC MAP GENERIC MAP
( (
f_sysclk => F_SYSCLK f_sysclk => F_CLK_SYS
) )
PORT MAP PORT MAP
( (
@@ -319,7 +326,7 @@ inst_gpio : entity work.gpio_wb
inst_uart0 : entity work.uart_wb inst_uart0 : entity work.uart_wb
GENERIC MAP GENERIC MAP
( (
f_sysclk => F_SYSCLK, f_sysclk => F_CLK_SYS,
baudrate_default => 460800.0, baudrate_default => 460800.0,
fifo_depth_bits => 4 fifo_depth_bits => 4
) )
@@ -345,7 +352,7 @@ inst_uart0 : entity work.uart_wb
inst_uart1 : entity work.uart_wb inst_uart1 : entity work.uart_wb
GENERIC MAP GENERIC MAP
( (
f_sysclk => F_SYSCLK, f_sysclk => F_CLK_SYS,
baudrate_default => 460800.0, baudrate_default => 460800.0,
fifo_depth_bits => 4 fifo_depth_bits => 4
) )
@@ -400,8 +407,8 @@ inst_spi_flash : entity work.spi_flash_wb
inst_ctrl_sdr_wb32 : entity work.ctrl_sdr_wb32 inst_ctrl_sdr_wb32 : entity work.ctrl_sdr_wb32
GENERIC MAP GENERIC MAP
( (
F_SYSCLK => F_SYSCLK, F_SYSCLK => F_CLK_SYS,
F_SDRCLK_IN => F_SYSCLK, F_SDRCLK_IN => F_CLK_BRD,
F_SDRCLK => 100.000, F_SDRCLK => 100.000,
FIFO_DEPTH => 4, FIFO_DEPTH => 4,
TPD_BOARD_SIM => 3100 ps TPD_BOARD_SIM => 3100 ps
@@ -410,8 +417,8 @@ inst_ctrl_sdr_wb32 : entity work.ctrl_sdr_wb32
( (
RST_I => sys_rst, RST_I => sys_rst,
CLK_I => sys_clk, CLK_I => sys_clk,
SDRAM_CLK_I => sys_clk, SDRAM_CLK_I => clk_brd,
SDRAM_CLK_FB_I => sys_clk, SDRAM_CLK_FB_I => clk_brd,
CYC_I => CYC_I_ram, CYC_I => CYC_I_ram,
STB_I => STB_O, STB_I => STB_O,