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[DE0-Nano]

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- derive sys_clk from PLL

git-svn-id: http://moon:8086/svn/vhdl/trunk@1384 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2017-02-05 11:10:29 +00:00
parent 364a66b1d3
commit 35c1a4e010
3 changed files with 41 additions and 32 deletions
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projects/mips_de0_nano/quartus/mips/mips_sys.vhd
+35 -28
View File
@@ -35,13 +35,14 @@ ENTITY mips_sys IS
(
ICACHE_SIZE : natural := 4096; -- words
DCACHE_SIZE : natural := 4096; -- words
F_SYSCLK : real := 50.0
F_CLK_BRD : real := 50.0;
F_CLK_SYS : real := 64.0
);
PORT
(
sys_nmi_n : in std_logic;
sys_rst_n : in std_logic;
sys_clk : in std_logic;
rst_brd_n : in std_logic;
clk_brd : in std_logic;
-- SDRAM signals
sys_sdram_clk : out STD_LOGIC;
@@ -131,38 +132,44 @@ ARCHITECTURE behavior OF mips_sys IS
signal gpi0 : unsigned(31 downto 0) := (others => '0');
signal sys_nmi : STD_LOGIC;
signal cpu_rst : STD_LOGIC := '1'; -- pre-init for POR
signal sys_rst : STD_LOGIC := '1'; -- pre-init for POR
signal sys_rst : STD_LOGIC;
signal sys_clk : STD_LOGIC;
signal rst_brd : STD_LOGIC;
signal cpu_rst : STD_LOGIC := '1'; -- pre-init for POR
signal cpu_rst_count : unsigned(24 downto 0) := (others => '1'); -- pre-init for POR
signal sys_rst_count : unsigned(7 downto 0) := (others => '1'); -- pre-init for POR
BEGIN
rst_brd <= not rst_brd_n;
sys_nmi <= not sys_nmi_n;
sys_leds <= cpu_debug & gpo0(5 downto 0);
spi_ss_n <= not spi_ss;
gpi0(11 downto 8) <= dip_sw;
sys_reset:
process(sys_clk)
begin
if rising_edge(sys_clk) then
if sys_rst_n = '0' then
sys_rst <= '1';
sys_rst_count <= (others => '1');
elsif (sys_rst_count /= 0) then
sys_rst_count <= sys_rst_count - 1;
else
sys_rst <= '0';
end if;
end if;
end process;
inst_sys_clk : entity work.sdram_clk
GENERIC MAP
(
F_SDRCLK_IN => F_CLK_BRD,
F_SDRCLK_OUT => F_CLK_SYS,
clk0_out_phaseshift_ps => 0,
clk1_out_phaseshift_ps => 3000
)
PORT MAP
(
-- Clocks and Reset
rst => rst_brd, -- external async reset, low active
clk_in => clk_brd, -- system clock (e.g. 100MHz), from board
clk_fb_in => clk_brd, -- feedback clock
clk0_0_out => sys_clk, -- System clock #0, dcm#0 output 0°
clk1_0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
rst0_0_out => sys_rst -- Reset out
);
cpu_reset:
process(sys_clk)
begin
if rising_edge(sys_clk) then
if sys_rst_n = '0' then
if sys_rst = '1' then
cpu_rst <= '1';
cpu_rst_count <= (others => '1');
elsif (cpu_rst_count /= 0) then
@@ -295,7 +302,7 @@ inst_rom : entity work.rom_wb
inst_gpio : entity work.gpio_wb
GENERIC MAP
(
f_sysclk => F_SYSCLK
f_sysclk => F_CLK_SYS
)
PORT MAP
(
@@ -319,7 +326,7 @@ inst_gpio : entity work.gpio_wb
inst_uart0 : entity work.uart_wb
GENERIC MAP
(
f_sysclk => F_SYSCLK,
f_sysclk => F_CLK_SYS,
baudrate_default => 460800.0,
fifo_depth_bits => 4
)
@@ -345,7 +352,7 @@ inst_uart0 : entity work.uart_wb
inst_uart1 : entity work.uart_wb
GENERIC MAP
(
f_sysclk => F_SYSCLK,
f_sysclk => F_CLK_SYS,
baudrate_default => 460800.0,
fifo_depth_bits => 4
)
@@ -400,8 +407,8 @@ inst_spi_flash : entity work.spi_flash_wb
inst_ctrl_sdr_wb32 : entity work.ctrl_sdr_wb32
GENERIC MAP
(
F_SYSCLK => F_SYSCLK,
F_SDRCLK_IN => F_SYSCLK,
F_SYSCLK => F_CLK_SYS,
F_SDRCLK_IN => F_CLK_BRD,
F_SDRCLK => 100.000,
FIFO_DEPTH => 4,
TPD_BOARD_SIM => 3100 ps
@@ -410,8 +417,8 @@ inst_ctrl_sdr_wb32 : entity work.ctrl_sdr_wb32
(
RST_I => sys_rst,
CLK_I => sys_clk,
SDRAM_CLK_I => sys_clk,
SDRAM_CLK_FB_I => sys_clk,
SDRAM_CLK_I => clk_brd,
SDRAM_CLK_FB_I => clk_brd,
CYC_I => CYC_I_ram,
STB_I => STB_O,