jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

[DE0-Nano]

Browse Source 
- derive sys_clk from PLL

git-svn-id: http://moon:8086/svn/vhdl/trunk@1384 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2017-02-05 11:10:29 +00:00
parent 364a66b1d3
commit 35c1a4e010
3 changed files with 41 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/mips_de0_nano/quartus/mips/JMips.sdc
+2 -2
View File
@@ -39,9 +39,9 @@ set_time_format -unit ns -decimal_places 3
# Create Clock
#**************************************************************
create_clock -name {sys_clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports { sys_clk }]
create_clock -name {sys_clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports { clk_brd }]
create_clock -name {SDRAM_clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {sys_sdram_clk}]
create_clock -name {spi_clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {spi_clk}]
create_clock -name {spi_clk} -period 15.000 -waveform { 0.000 7.500 } [get_ports {spi_clk}]
#**************************************************************