From 3419540ef7e3619bc14cb1575ded8c541048647a Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 5 Feb 2017 11:24:50 +0000 Subject: [PATCH] [DE0-Nano] - use PLL clock output for feed back git-svn-id: http://moon:8086/svn/vhdl/trunk@1385 cc03376c-175c-47c8-b038-4cd826a8556b --- projects/mips_de0_nano/quartus/mips/mips_sys.vhd | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/projects/mips_de0_nano/quartus/mips/mips_sys.vhd b/projects/mips_de0_nano/quartus/mips/mips_sys.vhd index fd49a0d..9a2ab03 100644 --- a/projects/mips_de0_nano/quartus/mips/mips_sys.vhd +++ b/projects/mips_de0_nano/quartus/mips/mips_sys.vhd @@ -138,6 +138,7 @@ ARCHITECTURE behavior OF mips_sys IS signal cpu_rst : STD_LOGIC := '1'; -- pre-init for POR signal cpu_rst_count : unsigned(24 downto 0) := (others => '1'); -- pre-init for POR + signal sdram_clk : STD_LOGIC; BEGIN rst_brd <= not rst_brd_n; @@ -145,6 +146,7 @@ BEGIN sys_leds <= cpu_debug & gpo0(5 downto 0); spi_ss_n <= not spi_ss; gpi0(11 downto 8) <= dip_sw; + sys_sdram_clk <= sdram_clk; inst_sys_clk : entity work.sdram_clk GENERIC MAP @@ -159,7 +161,7 @@ inst_sys_clk : entity work.sdram_clk -- Clocks and Reset rst => rst_brd, -- external async reset, low active clk_in => clk_brd, -- system clock (e.g. 100MHz), from board - clk_fb_in => clk_brd, -- feedback clock + clk_fb_in => sys_clk, -- feedback clock clk0_0_out => sys_clk, -- System clock #0, dcm#0 output 0° clk1_0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0° rst0_0_out => sys_rst -- Reset out @@ -418,7 +420,7 @@ inst_ctrl_sdr_wb32 : entity work.ctrl_sdr_wb32 RST_I => sys_rst, CLK_I => sys_clk, SDRAM_CLK_I => clk_brd, - SDRAM_CLK_FB_I => clk_brd, + SDRAM_CLK_FB_I => sdram_clk, CYC_I => CYC_I_ram, STB_I => STB_O, @@ -432,7 +434,7 @@ inst_ctrl_sdr_wb32 : entity work.ctrl_sdr_wb32 DAT_O => DAT_O_ram, -- SDRAM signals - sd_clk => sys_sdram_clk, + sd_clk => sdram_clk, sd_cke => sys_sdram_cke, sd_cs_n => sys_sdram_cs_n, sd_cas_n => sys_sdram_cas_n,