diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/ctrl_sdr_wb32.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/ctrl_sdr_wb32.vhd
index 3083829..0e5e66c 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/ctrl_sdr_wb32.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/ctrl_sdr_wb32.vhd
@@ -35,7 +35,8 @@ entity ctrl_sdr_wb32 is
 		BURST_LEN		: natural	:= 2;
 		F_SYSCLK		: real		:= 100.0;
 		F_SDRCLK	 	: real		:= 100.0;
-		FIFO_DEPTH		: integer	:= 4
+		FIFO_DEPTH		: integer	:= 4;
+		TPD_BOARD_SIM	: time		:= 0 ns
 	);
 	Port
 	(
@@ -118,7 +119,8 @@ begin
 	inst_sdram_phy : entity work.sdram_phy
 	Generic map
 	(
-		F_SDRCLK		=> F_SDRCLK
+		F_SDRCLK		=> F_SDRCLK,
+		TPD_BOARD_SIM	=> TPD_BOARD_SIM
 	)
 	Port map
 	(
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_virtex4.vhd
index cf2c08f..18a6c27 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_virtex4.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_virtex4.vhd
@@ -34,7 +34,8 @@ use UNISIM.vcomponents.all;
 entity sdram_phy is
 	Generic
 	(
-		F_SDRCLK		: real		:= 100.0
+		F_SDRCLK		: real		:= 100.0;
+		TPD_BOARD_SIM	: time		:= 0 ns
 	);
 	Port
 	(
@@ -110,7 +111,7 @@ inst_sdram_clk : entity work.sdram_clk
 	);
 
 	clk_wr	<= clk0;
-	clk_rd	<= clk0;
+	clk_rd	<= clk_fb;
 	
 rst0_gen:
 	process(clk0)
@@ -156,16 +157,16 @@ DATA_DRIVE_GEN:
 
 ------------------------------------------------------------------------------------------------------------------------------------------------
 -- SDRAM Clock
-part_clk	<= clk0;
+part_clk		<= clk0 after TPD_BOARD_SIM;
 
 ------------------------------------------------------------------------------------------------------------------------------------------------
 -- Data OUT FFs
 	process (clk_wr) is
 	begin  
 		if falling_edge(clk_wr) then
-			part_data <= (others => 'Z');
+			part_data <= (others => 'Z') after TPD_BOARD_SIM;
 			if (drive = '1') then
-				part_data	<= phy_in.wr_data;
+				part_data	<= phy_in.wr_data after TPD_BOARD_SIM;
 			end if;
 		end if;
 	end process;
@@ -175,7 +176,7 @@ part_clk	<= clk0;
 	process (clk_wr) is
 	begin  
 		if falling_edge(clk_wr) then
-			part_dqm	<= phy_in.wr_dm;
+			part_dqm	<= phy_in.wr_dm after TPD_BOARD_SIM;
 		end if;
 	end process;
 
@@ -197,13 +198,13 @@ part_clk	<= clk0;
 	process (clk0) is
 	begin  
 		if falling_edge(clk0) then
-			part_ras_n		<= part_ctrl_reg.cmd.ras_n;
-			part_cas_n		<= part_ctrl_reg.cmd.cas_n; 
-			part_we_n 		<= part_ctrl_reg.cmd.we_n; 
-			part_cs_n 		<= part_ctrl_reg.cmd.cs_n; 
-			part_ba   		<= part_ctrl_reg.ba; 
-			part_addr    	<= part_ctrl_reg.addr;
-			part_cke  		<= part_ctrl_reg.cke;
+			part_ras_n		<= part_ctrl_reg.cmd.ras_n after TPD_BOARD_SIM;
+			part_cas_n		<= part_ctrl_reg.cmd.cas_n after TPD_BOARD_SIM;
+			part_we_n 		<= part_ctrl_reg.cmd.we_n after TPD_BOARD_SIM;
+			part_cs_n 		<= part_ctrl_reg.cmd.cs_n after TPD_BOARD_SIM;
+			part_ba   		<= part_ctrl_reg.ba after TPD_BOARD_SIM;
+			part_addr    	<= part_ctrl_reg.addr after TPD_BOARD_SIM;
+			part_cke  		<= part_ctrl_reg.cke after TPD_BOARD_SIM;
 		end if;
 	end process;
 
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_sdr_wb32.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_sdr_wb32.vhd
index 13aae96..e8865a6 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_sdr_wb32.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_sdr_wb32.vhd
@@ -34,6 +34,7 @@ end;
 architecture struct of tb_ctrl_sdr_wb32 is
 
 	constant CLK_PERIOD		: time := 10 ns;
+	constant TPD_BOARD_SIM	: time := 3 ns;
 	constant SDCLK_PERIOD	: time := 10 ns;
 	constant BURST_LEN		: natural := 2;
 
@@ -104,7 +105,7 @@ begin
 		end if;
 	end process;
 	
-	sdclk_fb	<= part_clk after 1 ns;
+	sdclk_fb	<= part_clk;
 	
 	-- DDR SDRAM Controller Core
 	uut : entity work.ctrl_sdr_wb32
@@ -113,7 +114,8 @@ begin
 		BURST_LEN		=> BURST_LEN,
 		F_SYSCLK	 	=> 100.000,
 		F_SDRCLK	 	=> 100.000,
-		FIFO_DEPTH		=> 4
+		FIFO_DEPTH		=> 4,
+		TPD_BOARD_SIM	=> TPD_BOARD_SIM
 	)
 	PORT MAP
 	(