From 32cbb4fc13154514c83a990eb5af6bcdb3f79a90 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 19 Oct 2008 21:29:45 +0000 Subject: [PATCH] - Cleaned up git-svn-id: http://moon:8086/svn/vhdl/trunk@82 cc03376c-175c-47c8-b038-4cd826a8556b --- projects/mips_sys/src/bootloader.dis | 1319 ----------------------- projects/mips_sys/src/mips_pipeline.vhd | 886 --------------- projects/mips_sys/src/mips_sys_cfg.vhd | 19 - 3 files changed, 2224 deletions(-) delete mode 100644 projects/mips_sys/src/bootloader.dis delete mode 100644 projects/mips_sys/src/mips_pipeline.vhd delete mode 100644 projects/mips_sys/src/mips_sys_cfg.vhd diff --git a/projects/mips_sys/src/bootloader.dis b/projects/mips_sys/src/bootloader.dis deleted file mode 100644 index db10543..0000000 --- a/projects/mips_sys/src/bootloader.dis +++ /dev/null @@ -1,1319 +0,0 @@ - -bootloader.elf: file format elf32-littlemips - -Disassembly of section .stext: - -bfc00000 <__entry>: -bfc00000: 3c1a1040 lui k0,0x1040 -bfc00004: 375a000c ori k0,k0,0xc -bfc00008: 409a6000 mtc0 k0,$12 -bfc0000c: 241a0000 li k0,0 -bfc00010: 409a6800 mtc0 k0,$13 -bfc00014: 401a7800 mfc0 k0,$15 -bfc00018: 00000000 nop -bfc0001c: 409af800 mtc0 k0,$31 -bfc00020: 3c1abfc0 lui k0,0xbfc0 -bfc00024: 275a01c4 addiu k0,k0,452 -bfc00028: 03400008 jr k0 -bfc0002c: 00000000 nop -Disassembly of section .ktext: - -bfc00180 <_exc_handler>: -bfc00180: 401a6800 mfc0 k0,$13 -bfc00184: 3c1ba000 lui k1,0xa000 -bfc00188: 277b0000 addiu k1,k1,0 -bfc0018c: 001ad082 srl k0,k0,0x2 -bfc00190: 335a000f andi k0,k0,0xf -bfc00194: 035bd025 or k0,k0,k1 -bfc00198: af7a0000 sw k0,0(k1) -bfc0019c: 401a6800 mfc0 k0,$13 -bfc001a0: 00000000 nop -bfc001a4: 001ad202 srl k0,k0,0x8 -bfc001a8: 335a00ff andi k0,k0,0xff -bfc001ac: 1740fffb bnez k0,bfc0019c <_exc_handler+0x1c> -bfc001b0: 00000000 nop -bfc001b4: 401a7000 mfc0 k0,$14 -bfc001b8: 00000000 nop -bfc001bc: 03400008 jr k0 -bfc001c0: 42000010 rfe -Disassembly of section .text: - -bfc001c4 <_init>: -bfc001c4: 3c1aa001 275a0008 241b000d a35b0000 ...<..Z'...$..[. -bfc001d4: 3c1dbfd0 27bdfff0 241a0005 1340009f ...<...'...$..@. -bfc001e4: 241afffb 1340009d 241a0000 13400003 ...$..@....$..@. -bfc001f4: 00000000 0bf00118 00000000 241a0005 ...............$ -bfc00204: 241b0006 135b0095 241afffb 135b0093 ...$..[....$..[. -bfc00214: 241a0000 135b0091 241a0006 135b0003 ...$..[....$..[. -bfc00224: 00000000 0bf00118 00000000 241afffb ...............$ -bfc00234: 0741008a 241a0005 07410002 00000000 ..A....$..A..... -bfc00244: 0bf00118 241a0000 07410002 00000000 .......$..A..... -bfc00254: 0bf00118 241afffb 1f400080 241a0000 .......$..@....$ -bfc00264: 1f40007e 241a0005 1f400002 00000000 ~.@....$..@..... -bfc00274: 0bf00118 241a0005 1b400078 241a0000 .......$x.@....$ -bfc00284: 1b400002 00000000 0bf00118 241afffb ..@............$ -bfc00294: 1b400002 00000000 0bf00118 241a0005 ..@............$ -bfc002a4: 0740006e 241a0000 0740006c 241afffb n.@....$l.@....$ -bfc002b4: 07400002 00000000 0bf00118 241a0005 ..@............$ -bfc002c4: 241b0006 175b0002 00000000 0bf00118 ...$..[......... -bfc002d4: 241afffb 175b0002 00000000 0bf00118 ...$..[......... -bfc002e4: 241afffa 175b0002 00000000 0bf00118 ...$..[......... -bfc002f4: 241a0000 175b0002 00000000 0bf00118 ...$..[......... -bfc00304: 241a0006 175b0055 241a0005 17400002 ...$U.[....$..@. -bfc00314: 00000000 0bf00118 241afffb 17400002 ...........$..@. -bfc00324: 00000000 0bf00118 241a0000 1740004b ...........$K.@. -bfc00334: 241b0005 2f7a0006 2f7afffa 241bfffb ...$..z/..z/...$ -bfc00344: 2f7a0006 2f7afffa 241b0006 2f7a0005 ..z/..z/...$..z/ -bfc00354: 2f7afffb 241bfffa 2f7a0005 2f7afffb ..z/...$..z/..z/ -bfc00364: 241b0005 2b7a0006 2b7afffa 241bfffb ...$..z+..z+...$ -bfc00374: 2b7a0006 2b7afffa 241b0006 2b7a0005 ..z+..z+...$..z+ -bfc00384: 2b7afffb 241bfffa 2b7a0005 2b7afffb ..z+...$..z+..z+ -bfc00394: 241a0005 241b0006 035bd02b 241a0005 ...$...$+.[....$ -bfc003a4: 241bfffa 035bd02b 241afffb 241b0006 ...$+.[....$...$ -bfc003b4: 035bd02b 241afffb 241bfffa 035bd02b +.[....$...$+.[. -bfc003c4: 241a0006 241b0005 035bd02b 241a0006 ...$...$+.[....$ -bfc003d4: 241bfffb 035bd02b 241afffa 241b0005 ...$+.[....$...$ -bfc003e4: 035bd02b 241afffa 241bfffb 035bd02b +.[....$...$+.[. -bfc003f4: 241a0005 241b0006 035bd02a 241a0005 ...$...$*.[....$ -bfc00404: 241bfffa 035bd02a 241afffb 241b0006 ...$*.[....$...$ -bfc00414: 035bd02a 241afffb 241bfffa 035bd02a *.[....$...$*.[. -bfc00424: 241a0006 241b0005 035bd02a 241a0006 ...$...$*.[....$ -bfc00434: 241bfffb 035bd02a 241afffa 241b0005 ...$*.[....$...$ -bfc00444: 035bd02a 241afffa 241bfffb 035bd02a *.[....$...$*.[. -bfc00454: 3c1abfc0 275a0f2c 0340f809 ...<,.Z'..@. - -bfc00460 <_terminate>: -bfc00460: 00000000 nop -bfc00464: 0bf00118 j bfc00460 <_terminate> -bfc00468: 00000000 nop - -bfc0046c : -bfc0046c: 27bdfff0 addiu sp,sp,-16 -bfc00470: afbe000c sw s8,12(sp) -bfc00474: 03a0f021 move s8,sp -bfc00478: 40026000 mfc0 v0,$12 -bfc0047c: 03c0e821 move sp,s8 -bfc00480: 8fbe000c lw s8,12(sp) -bfc00484: 03e00008 jr ra -bfc00488: 27bd0010 addiu sp,sp,16 - -bfc0048c : -bfc0048c: 27bdfff0 addiu sp,sp,-16 -bfc00490: afbe000c sw s8,12(sp) -bfc00494: 03a0f021 move s8,sp -bfc00498: 40027800 mfc0 v0,$15 -bfc0049c: 03c0e821 move sp,s8 -bfc004a0: 8fbe000c lw s8,12(sp) -bfc004a4: 03e00008 jr ra -bfc004a8: 27bd0010 addiu sp,sp,16 - -bfc004ac : -bfc004ac: 27bdfff0 addiu sp,sp,-16 -bfc004b0: afbe000c sw s8,12(sp) -bfc004b4: 03a0f021 move s8,sp -bfc004b8: 3c02a001 lui v0,0xa001 -bfc004bc: 34420004 ori v0,v0,0x4 -bfc004c0: afc20004 sw v0,4(s8) -bfc004c4: 3c02a001 lui v0,0xa001 -bfc004c8: afc20000 sw v0,0(s8) -bfc004cc: 8fc20004 lw v0,4(s8) -bfc004d0: 00000000 nop -bfc004d4: 8c420000 lw v0,0(v0) -bfc004d8: 00000000 nop -bfc004dc: 30420010 andi v0,v0,0x10 -bfc004e0: 1040fffa beqz v0,bfc004cc -bfc004e4: 00000000 nop -bfc004e8: 8fc20000 lw v0,0(s8) -bfc004ec: 00000000 nop -bfc004f0: 8c420000 lw v0,0(v0) -bfc004f4: 00000000 nop -bfc004f8: 00021600 sll v0,v0,0x18 -bfc004fc: 00021603 sra v0,v0,0x18 -bfc00500: 03c0e821 move sp,s8 -bfc00504: 8fbe000c lw s8,12(sp) -bfc00508: 27bd0010 addiu sp,sp,16 -bfc0050c: 03e00008 jr ra -bfc00510: 00000000 nop - -bfc00514 : -bfc00514: 27bdffe8 addiu sp,sp,-24 -bfc00518: afbe0014 sw s8,20(sp) -bfc0051c: 03a0f021 move s8,sp -bfc00520: 00801021 move v0,a0 -bfc00524: a3c20008 sb v0,8(s8) -bfc00528: 3c02a001 lui v0,0xa001 -bfc0052c: 34420004 ori v0,v0,0x4 -bfc00530: afc20004 sw v0,4(s8) -bfc00534: 3c02a001 lui v0,0xa001 -bfc00538: afc20000 sw v0,0(s8) -bfc0053c: 8fc20004 lw v0,4(s8) -bfc00540: 00000000 nop -bfc00544: 8c420000 lw v0,0(v0) -bfc00548: 00000000 nop -bfc0054c: 30420002 andi v0,v0,0x2 -bfc00550: 1440fffa bnez v0,bfc0053c -bfc00554: 00000000 nop -bfc00558: 83c30008 lb v1,8(s8) -bfc0055c: 8fc20000 lw v0,0(s8) -bfc00560: 00000000 nop -bfc00564: ac430000 sw v1,0(v0) -bfc00568: 03c0e821 move sp,s8 -bfc0056c: 8fbe0014 lw s8,20(sp) -bfc00570: 27bd0018 addiu sp,sp,24 -bfc00574: 03e00008 jr ra -bfc00578: 00000000 nop - -bfc0057c <_putchar>: -bfc0057c: 27bdfff0 addiu sp,sp,-16 -bfc00580: afbf000c sw ra,12(sp) -bfc00584: afbe0008 sw s8,8(sp) -bfc00588: 03a0f021 move s8,sp -bfc0058c: 00801021 move v0,a0 -bfc00590: a3c20000 sb v0,0(s8) -bfc00594: 83c30000 lb v1,0(s8) -bfc00598: 2402000a li v0,10 -bfc0059c: 1462000b bne v1,v0,bfc005cc <_putchar+0x50> -bfc005a0: 00000000 nop -bfc005a4: 2404000d li a0,13 -bfc005a8: 0ff00145 jal bfc00514 -bfc005ac: 00000000 nop -bfc005b0: 83c20000 lb v0,0(s8) -bfc005b4: 00000000 nop -bfc005b8: 00402021 move a0,v0 -bfc005bc: 0ff00145 jal bfc00514 -bfc005c0: 00000000 nop -bfc005c4: 0bf00178 j bfc005e0 <_putchar+0x64> -bfc005c8: 00000000 nop -bfc005cc: 83c20000 lb v0,0(s8) -bfc005d0: 00000000 nop -bfc005d4: 00402021 move a0,v0 -bfc005d8: 0ff00145 jal bfc00514 -bfc005dc: 00000000 nop -bfc005e0: 03c0e821 move sp,s8 -bfc005e4: 8fbf000c lw ra,12(sp) -bfc005e8: 8fbe0008 lw s8,8(sp) -bfc005ec: 27bd0010 addiu sp,sp,16 -bfc005f0: 03e00008 jr ra -bfc005f4: 00000000 nop - -bfc005f8 : -bfc005f8: 27bdffe8 addiu sp,sp,-24 -bfc005fc: afbf0014 sw ra,20(sp) -bfc00600: afbe0010 sw s8,16(sp) -bfc00604: 03a0f021 move s8,sp -bfc00608: afc40008 sw a0,8(s8) -bfc0060c: 8fc20008 lw v0,8(s8) -bfc00610: 00000000 nop -bfc00614: afc20000 sw v0,0(s8) -bfc00618: 0bf00194 j bfc00650 -bfc0061c: 00000000 nop -bfc00620: 8fc20008 lw v0,8(s8) -bfc00624: 00000000 nop -bfc00628: 80420000 lb v0,0(v0) -bfc0062c: 00000000 nop -bfc00630: 00401821 move v1,v0 -bfc00634: 8fc20008 lw v0,8(s8) -bfc00638: 00000000 nop -bfc0063c: 24420001 addiu v0,v0,1 -bfc00640: afc20008 sw v0,8(s8) -bfc00644: 00602021 move a0,v1 -bfc00648: 0ff0015f jal bfc0057c <_putchar> -bfc0064c: 00000000 nop -bfc00650: 8fc20008 lw v0,8(s8) -bfc00654: 00000000 nop -bfc00658: 80420000 lb v0,0(v0) -bfc0065c: 00000000 nop -bfc00660: 1440ffef bnez v0,bfc00620 -bfc00664: 00000000 nop -bfc00668: 8fc30008 lw v1,8(s8) -bfc0066c: 8fc20000 lw v0,0(s8) -bfc00670: 00000000 nop -bfc00674: 00621023 subu v0,v1,v0 -bfc00678: 03c0e821 move sp,s8 -bfc0067c: 8fbf0014 lw ra,20(sp) -bfc00680: 8fbe0010 lw s8,16(sp) -bfc00684: 27bd0018 addiu sp,sp,24 -bfc00688: 03e00008 jr ra -bfc0068c: 00000000 nop - -bfc00690 : -bfc00690: 27bdffe8 addiu sp,sp,-24 -bfc00694: afbf0014 sw ra,20(sp) -bfc00698: afbe0010 sw s8,16(sp) -bfc0069c: 03a0f021 move s8,sp -bfc006a0: 00801021 move v0,a0 -bfc006a4: a3c20008 sb v0,8(s8) -bfc006a8: afc00004 sw zero,4(s8) -bfc006ac: 0bf001cd j bfc00734 -bfc006b0: 00000000 nop -bfc006b4: 93c20008 lbu v0,8(s8) -bfc006b8: 00000000 nop -bfc006bc: 00021102 srl v0,v0,0x4 -bfc006c0: a3c20000 sb v0,0(s8) -bfc006c4: 83c20008 lb v0,8(s8) -bfc006c8: 00000000 nop -bfc006cc: 00021100 sll v0,v0,0x4 -bfc006d0: a3c20008 sb v0,8(s8) -bfc006d4: 93c20000 lbu v0,0(s8) -bfc006d8: 00000000 nop -bfc006dc: 2c42000a sltiu v0,v0,10 -bfc006e0: 10400007 beqz v0,bfc00700 -bfc006e4: 00000000 nop -bfc006e8: 93c20000 lbu v0,0(s8) -bfc006ec: 00000000 nop -bfc006f0: 24420030 addiu v0,v0,48 -bfc006f4: a3c20001 sb v0,1(s8) -bfc006f8: 0bf001c4 j bfc00710 -bfc006fc: 00000000 nop -bfc00700: 93c20000 lbu v0,0(s8) -bfc00704: 00000000 nop -bfc00708: 24420037 addiu v0,v0,55 -bfc0070c: a3c20001 sb v0,1(s8) -bfc00710: 83c20001 lb v0,1(s8) -bfc00714: 00000000 nop -bfc00718: 00402021 move a0,v0 -bfc0071c: 0ff00145 jal bfc00514 -bfc00720: 00000000 nop -bfc00724: 8fc20004 lw v0,4(s8) -bfc00728: 00000000 nop -bfc0072c: 24420001 addiu v0,v0,1 -bfc00730: afc20004 sw v0,4(s8) -bfc00734: 8fc20004 lw v0,4(s8) -bfc00738: 00000000 nop -bfc0073c: 28420002 slti v0,v0,2 -bfc00740: 1440ffdc bnez v0,bfc006b4 -bfc00744: 00000000 nop -bfc00748: 03c0e821 move sp,s8 -bfc0074c: 8fbf0014 lw ra,20(sp) -bfc00750: 8fbe0010 lw s8,16(sp) -bfc00754: 27bd0018 addiu sp,sp,24 -bfc00758: 03e00008 jr ra -bfc0075c: 00000000 nop - -bfc00760 : -bfc00760: 27bdffe8 addiu sp,sp,-24 -bfc00764: afbf0014 sw ra,20(sp) -bfc00768: afbe0010 sw s8,16(sp) -bfc0076c: 03a0f021 move s8,sp -bfc00770: afc40008 sw a0,8(s8) -bfc00774: afc00004 sw zero,4(s8) -bfc00778: 0bf001f1 j bfc007c4 -bfc0077c: 00000000 nop -bfc00780: 8fc20008 lw v0,8(s8) -bfc00784: 00000000 nop -bfc00788: 00021603 sra v0,v0,0x18 -bfc0078c: a3c20001 sb v0,1(s8) -bfc00790: 83c20001 lb v0,1(s8) -bfc00794: 00000000 nop -bfc00798: 00402021 move a0,v0 -bfc0079c: 0ff001a4 jal bfc00690 -bfc007a0: 00000000 nop -bfc007a4: 8fc20008 lw v0,8(s8) -bfc007a8: 00000000 nop -bfc007ac: 00021200 sll v0,v0,0x8 -bfc007b0: afc20008 sw v0,8(s8) -bfc007b4: 8fc20004 lw v0,4(s8) -bfc007b8: 00000000 nop -bfc007bc: 24420001 addiu v0,v0,1 -bfc007c0: afc20004 sw v0,4(s8) -bfc007c4: 8fc20004 lw v0,4(s8) -bfc007c8: 00000000 nop -bfc007cc: 28420004 slti v0,v0,4 -bfc007d0: 1440ffeb bnez v0,bfc00780 -bfc007d4: 00000000 nop -bfc007d8: 03c0e821 move sp,s8 -bfc007dc: 8fbf0014 lw ra,20(sp) -bfc007e0: 8fbe0010 lw s8,16(sp) -bfc007e4: 27bd0018 addiu sp,sp,24 -bfc007e8: 03e00008 jr ra -bfc007ec: 00000000 nop - -bfc007f0 : -bfc007f0: 27bdffe8 addiu sp,sp,-24 -bfc007f4: afbe0014 sw s8,20(sp) -bfc007f8: 03a0f021 move s8,sp -bfc007fc: afc40008 sw a0,8(s8) -bfc00800: a3c00000 sb zero,0(s8) -bfc00804: afc00004 sw zero,4(s8) -bfc00808: 0bf00229 j bfc008a4 -bfc0080c: 00000000 nop -bfc00810: 8fc30004 lw v1,4(s8) -bfc00814: 8fc20008 lw v0,8(s8) -bfc00818: 00000000 nop -bfc0081c: 00431021 addu v0,v0,v1 -bfc00820: 90420000 lbu v0,0(v0) -bfc00824: 00000000 nop -bfc00828: a3c20001 sb v0,1(s8) -bfc0082c: 93c20001 lbu v0,1(s8) -bfc00830: 00000000 nop -bfc00834: 2c420041 sltiu v0,v0,65 -bfc00838: 14400007 bnez v0,bfc00858 -bfc0083c: 00000000 nop -bfc00840: 93c20001 lbu v0,1(s8) -bfc00844: 00000000 nop -bfc00848: 2442ffc9 addiu v0,v0,-55 -bfc0084c: a3c20001 sb v0,1(s8) -bfc00850: 0bf0021a j bfc00868 -bfc00854: 00000000 nop -bfc00858: 93c20001 lbu v0,1(s8) -bfc0085c: 00000000 nop -bfc00860: 2442ffd0 addiu v0,v0,-48 -bfc00864: a3c20001 sb v0,1(s8) -bfc00868: 93c20000 lbu v0,0(s8) -bfc0086c: 00000000 nop -bfc00870: 00021100 sll v0,v0,0x4 -bfc00874: 00021e00 sll v1,v0,0x18 -bfc00878: 00031e03 sra v1,v1,0x18 -bfc0087c: 83c20001 lb v0,1(s8) -bfc00880: 00000000 nop -bfc00884: 00621025 or v0,v1,v0 -bfc00888: 00021600 sll v0,v0,0x18 -bfc0088c: 00021603 sra v0,v0,0x18 -bfc00890: a3c20000 sb v0,0(s8) -bfc00894: 8fc20004 lw v0,4(s8) -bfc00898: 00000000 nop -bfc0089c: 24420001 addiu v0,v0,1 -bfc008a0: afc20004 sw v0,4(s8) -bfc008a4: 8fc20004 lw v0,4(s8) -bfc008a8: 00000000 nop -bfc008ac: 28420002 slti v0,v0,2 -bfc008b0: 1440ffd7 bnez v0,bfc00810 -bfc008b4: 00000000 nop -bfc008b8: 93c20000 lbu v0,0(s8) -bfc008bc: 03c0e821 move sp,s8 -bfc008c0: 8fbe0014 lw s8,20(sp) -bfc008c4: 27bd0018 addiu sp,sp,24 -bfc008c8: 03e00008 jr ra -bfc008cc: 00000000 nop - -bfc008d0 : -bfc008d0: 27bdffd8 addiu sp,sp,-40 -bfc008d4: afbf0024 sw ra,36(sp) -bfc008d8: afbe0020 sw s8,32(sp) -bfc008dc: 03a0f021 move s8,sp -bfc008e0: afc40010 sw a0,16(s8) -bfc008e4: afc50014 sw a1,20(s8) -bfc008e8: afc60018 sw a2,24(s8) -bfc008ec: 8fc20018 lw v0,24(s8) -bfc008f0: 00000000 nop -bfc008f4: 14400004 bnez v0,bfc00908 -bfc008f8: 00000000 nop -bfc008fc: afc0001c sw zero,28(s8) -bfc00900: 0bf00321 j bfc00c84 -bfc00904: 00000000 nop -bfc00908: 8fc30010 lw v1,16(s8) -bfc0090c: 24020003 li v0,3 -bfc00910: ac620008 sw v0,8(v1) -bfc00914: afc00004 sw zero,4(s8) -bfc00918: 8fc20014 lw v0,20(s8) -bfc0091c: 00000000 nop -bfc00920: 24420001 addiu v0,v0,1 -bfc00924: 90420000 lbu v0,0(v0) -bfc00928: 00000000 nop -bfc0092c: 2c420031 sltiu v0,v0,49 -bfc00930: 14400015 bnez v0,bfc00988 -bfc00934: 00000000 nop -bfc00938: 8fc20014 lw v0,20(s8) -bfc0093c: 00000000 nop -bfc00940: 24420001 addiu v0,v0,1 -bfc00944: 90420000 lbu v0,0(v0) -bfc00948: 00000000 nop -bfc0094c: 2c420034 sltiu v0,v0,52 -bfc00950: 1040000d beqz v0,bfc00988 -bfc00954: 00000000 nop -bfc00958: 8fc20014 lw v0,20(s8) -bfc0095c: 00000000 nop -bfc00960: 24420001 addiu v0,v0,1 -bfc00964: 90420000 lbu v0,0(v0) -bfc00968: 00000000 nop -bfc0096c: 2442ffd1 addiu v0,v0,-47 -bfc00970: afc20004 sw v0,4(s8) -bfc00974: 8fc30010 lw v1,16(s8) -bfc00978: 24020002 li v0,2 -bfc0097c: ac620008 sw v0,8(v1) -bfc00980: 0bf0028c j bfc00a30 -bfc00984: 00000000 nop -bfc00988: 8fc20014 lw v0,20(s8) -bfc0098c: 00000000 nop -bfc00990: 24420001 addiu v0,v0,1 -bfc00994: 90420000 lbu v0,0(v0) -bfc00998: 00000000 nop -bfc0099c: 2c420037 sltiu v0,v0,55 -bfc009a0: 14400017 bnez v0,bfc00a00 -bfc009a4: 00000000 nop -bfc009a8: 8fc20014 lw v0,20(s8) -bfc009ac: 00000000 nop -bfc009b0: 24420001 addiu v0,v0,1 -bfc009b4: 90420000 lbu v0,0(v0) -bfc009b8: 00000000 nop -bfc009bc: 2c42003a sltiu v0,v0,58 -bfc009c0: 1040000f beqz v0,bfc00a00 -bfc009c4: 00000000 nop -bfc009c8: 8fc20014 lw v0,20(s8) -bfc009cc: 00000000 nop -bfc009d0: 24420001 addiu v0,v0,1 -bfc009d4: 90420000 lbu v0,0(v0) -bfc009d8: 00000000 nop -bfc009dc: 00401821 move v1,v0 -bfc009e0: 2402003b li v0,59 -bfc009e4: 00431023 subu v0,v0,v1 -bfc009e8: afc20004 sw v0,4(s8) -bfc009ec: 8fc30010 lw v1,16(s8) -bfc009f0: 24020004 li v0,4 -bfc009f4: ac620008 sw v0,8(v1) -bfc009f8: 0bf0028c j bfc00a30 -bfc009fc: 00000000 nop -bfc00a00: 8fc20014 lw v0,20(s8) -bfc00a04: 00000000 nop -bfc00a08: 24420001 addiu v0,v0,1 -bfc00a0c: 90430000 lbu v1,0(v0) -bfc00a10: 24020030 li v0,48 -bfc00a14: 14620006 bne v1,v0,bfc00a30 -bfc00a18: 00000000 nop -bfc00a1c: 24020002 li v0,2 -bfc00a20: afc20004 sw v0,4(s8) -bfc00a24: 8fc30010 lw v1,16(s8) -bfc00a28: 24020001 li v0,1 -bfc00a2c: ac620008 sw v0,8(v1) -bfc00a30: 8fc20014 lw v0,20(s8) -bfc00a34: 00000000 nop -bfc00a38: 24420002 addiu v0,v0,2 -bfc00a3c: 00402021 move a0,v0 -bfc00a40: 0ff001fc jal bfc007f0 -bfc00a44: 00000000 nop -bfc00a48: a3c20008 sb v0,8(s8) -bfc00a4c: 93c30008 lbu v1,8(s8) -bfc00a50: 8fc20010 lw v0,16(s8) -bfc00a54: 00000000 nop -bfc00a58: ac430004 sw v1,4(v0) -bfc00a5c: 93c20008 lbu v0,8(s8) -bfc00a60: 00000000 nop -bfc00a64: a3c20009 sb v0,9(s8) -bfc00a68: 8fc20010 lw v0,16(s8) -bfc00a6c: 00000000 nop -bfc00a70: ac400000 sw zero,0(v0) -bfc00a74: afc00000 sw zero,0(s8) -bfc00a78: 0bf002c0 j bfc00b00 -bfc00a7c: 00000000 nop -bfc00a80: 8fc20000 lw v0,0(s8) -bfc00a84: 00000000 nop -bfc00a88: 24420002 addiu v0,v0,2 -bfc00a8c: 00021040 sll v0,v0,0x1 -bfc00a90: 00401821 move v1,v0 -bfc00a94: 8fc20014 lw v0,20(s8) -bfc00a98: 00000000 nop -bfc00a9c: 00431021 addu v0,v0,v1 -bfc00aa0: 00402021 move a0,v0 -bfc00aa4: 0ff001fc jal bfc007f0 -bfc00aa8: 00000000 nop -bfc00aac: a3c20008 sb v0,8(s8) -bfc00ab0: 8fc20010 lw v0,16(s8) -bfc00ab4: 00000000 nop -bfc00ab8: 8c420000 lw v0,0(v0) -bfc00abc: 00000000 nop -bfc00ac0: 00021a00 sll v1,v0,0x8 -bfc00ac4: 93c20008 lbu v0,8(s8) -bfc00ac8: 00000000 nop -bfc00acc: 00621825 or v1,v1,v0 -bfc00ad0: 8fc20010 lw v0,16(s8) -bfc00ad4: 00000000 nop -bfc00ad8: ac430000 sw v1,0(v0) -bfc00adc: 93c30009 lbu v1,9(s8) -bfc00ae0: 93c20008 lbu v0,8(s8) -bfc00ae4: 00000000 nop -bfc00ae8: 00621021 addu v0,v1,v0 -bfc00aec: a3c20009 sb v0,9(s8) -bfc00af0: 8fc20000 lw v0,0(s8) -bfc00af4: 00000000 nop -bfc00af8: 24420001 addiu v0,v0,1 -bfc00afc: afc20000 sw v0,0(s8) -bfc00b00: 8fc20000 lw v0,0(s8) -bfc00b04: 8fc30004 lw v1,4(s8) -bfc00b08: 00000000 nop -bfc00b0c: 0043102a slt v0,v0,v1 -bfc00b10: 1440ffdb bnez v0,bfc00a80 -bfc00b14: 00000000 nop -bfc00b18: 8fc20010 lw v0,16(s8) -bfc00b1c: 00000000 nop -bfc00b20: 8c430004 lw v1,4(v0) -bfc00b24: 8fc20004 lw v0,4(s8) -bfc00b28: 00000000 nop -bfc00b2c: 00021027 nor v0,zero,v0 -bfc00b30: 00621821 addu v1,v1,v0 -bfc00b34: 8fc20010 lw v0,16(s8) -bfc00b38: 00000000 nop -bfc00b3c: ac430004 sw v1,4(v0) -bfc00b40: 8fc20004 lw v0,4(s8) -bfc00b44: 00000000 nop -bfc00b48: 24420002 addiu v0,v0,2 -bfc00b4c: 00021040 sll v0,v0,0x1 -bfc00b50: 00401821 move v1,v0 -bfc00b54: 8fc20014 lw v0,20(s8) -bfc00b58: 00000000 nop -bfc00b5c: 00431821 addu v1,v0,v1 -bfc00b60: 8fc20010 lw v0,16(s8) -bfc00b64: 00000000 nop -bfc00b68: ac43000c sw v1,12(v0) -bfc00b6c: afc00000 sw zero,0(s8) -bfc00b70: 0bf002fb j bfc00bec -bfc00b74: 00000000 nop -bfc00b78: 8fc20010 lw v0,16(s8) -bfc00b7c: 00000000 nop -bfc00b80: 8c43000c lw v1,12(v0) -bfc00b84: 8fc20000 lw v0,0(s8) -bfc00b88: 00000000 nop -bfc00b8c: 00021040 sll v0,v0,0x1 -bfc00b90: 00621021 addu v0,v1,v0 -bfc00b94: 00402021 move a0,v0 -bfc00b98: 0ff001fc jal bfc007f0 -bfc00b9c: 00000000 nop -bfc00ba0: a3c20008 sb v0,8(s8) -bfc00ba4: 8fc20010 lw v0,16(s8) -bfc00ba8: 00000000 nop -bfc00bac: 8c43000c lw v1,12(v0) -bfc00bb0: 8fc20000 lw v0,0(s8) -bfc00bb4: 00000000 nop -bfc00bb8: 00621821 addu v1,v1,v0 -bfc00bbc: 93c20008 lbu v0,8(s8) -bfc00bc0: 00000000 nop -bfc00bc4: a0620000 sb v0,0(v1) -bfc00bc8: 93c30009 lbu v1,9(s8) -bfc00bcc: 93c20008 lbu v0,8(s8) -bfc00bd0: 00000000 nop -bfc00bd4: 00621021 addu v0,v1,v0 -bfc00bd8: a3c20009 sb v0,9(s8) -bfc00bdc: 8fc20000 lw v0,0(s8) -bfc00be0: 00000000 nop -bfc00be4: 24420001 addiu v0,v0,1 -bfc00be8: afc20000 sw v0,0(s8) -bfc00bec: 8fc20010 lw v0,16(s8) -bfc00bf0: 00000000 nop -bfc00bf4: 8c420004 lw v0,4(v0) -bfc00bf8: 00000000 nop -bfc00bfc: 00401821 move v1,v0 -bfc00c00: 8fc20000 lw v0,0(s8) -bfc00c04: 00000000 nop -bfc00c08: 0043102a slt v0,v0,v1 -bfc00c0c: 1440ffda bnez v0,bfc00b78 -bfc00c10: 00000000 nop -bfc00c14: 93c20009 lbu v0,9(s8) -bfc00c18: 00000000 nop -bfc00c1c: 00021027 nor v0,zero,v0 -bfc00c20: a3c20009 sb v0,9(s8) -bfc00c24: 8fc20010 lw v0,16(s8) -bfc00c28: 00000000 nop -bfc00c2c: 8c43000c lw v1,12(v0) -bfc00c30: 8fc20000 lw v0,0(s8) -bfc00c34: 00000000 nop -bfc00c38: 00021040 sll v0,v0,0x1 -bfc00c3c: 00621021 addu v0,v1,v0 -bfc00c40: 00402021 move a0,v0 -bfc00c44: 0ff001fc jal bfc007f0 -bfc00c48: 00000000 nop -bfc00c4c: a3c20008 sb v0,8(s8) -bfc00c50: 93c30009 lbu v1,9(s8) -bfc00c54: 93c20008 lbu v0,8(s8) -bfc00c58: 00000000 nop -bfc00c5c: 10620004 beq v1,v0,bfc00c70 -bfc00c60: 00000000 nop -bfc00c64: afc0001c sw zero,28(s8) -bfc00c68: 0bf00321 j bfc00c84 -bfc00c6c: 00000000 nop -bfc00c70: 8fc20010 lw v0,16(s8) -bfc00c74: 00000000 nop -bfc00c78: 8c420008 lw v0,8(v0) -bfc00c7c: 00000000 nop -bfc00c80: afc2001c sw v0,28(s8) -bfc00c84: 8fc2001c lw v0,28(s8) -bfc00c88: 03c0e821 move sp,s8 -bfc00c8c: 8fbf0024 lw ra,36(sp) -bfc00c90: 8fbe0020 lw s8,32(sp) -bfc00c94: 27bd0028 addiu sp,sp,40 -bfc00c98: 03e00008 jr ra -bfc00c9c: 00000000 nop - -bfc00ca0 : -bfc00ca0: 27bdffe8 addiu sp,sp,-24 -bfc00ca4: afbf0014 sw ra,20(sp) -bfc00ca8: afbe0010 sw s8,16(sp) -bfc00cac: 03a0f021 move s8,sp -bfc00cb0: afc40008 sw a0,8(s8) -bfc00cb4: afc00000 sw zero,0(s8) -bfc00cb8: 0ff0012b jal bfc004ac -bfc00cbc: 00000000 nop -bfc00cc0: a3c20004 sb v0,4(s8) -bfc00cc4: 83c30004 lb v1,4(s8) -bfc00cc8: 24020073 li v0,115 -bfc00ccc: 10620015 beq v1,v0,bfc00d24 -bfc00cd0: 00000000 nop -bfc00cd4: 83c30004 lb v1,4(s8) -bfc00cd8: 24020053 li v0,83 -bfc00cdc: 1462fff6 bne v1,v0,bfc00cb8 -bfc00ce0: 00000000 nop -bfc00ce4: 0bf00349 j bfc00d24 -bfc00ce8: 00000000 nop -bfc00cec: 8fc30000 lw v1,0(s8) -bfc00cf0: 8fc20008 lw v0,8(s8) -bfc00cf4: 00000000 nop -bfc00cf8: 00431821 addu v1,v0,v1 -bfc00cfc: 93c20004 lbu v0,4(s8) -bfc00d00: 00000000 nop -bfc00d04: a0620000 sb v0,0(v1) -bfc00d08: 8fc20000 lw v0,0(s8) -bfc00d0c: 00000000 nop -bfc00d10: 24420001 addiu v0,v0,1 -bfc00d14: afc20000 sw v0,0(s8) -bfc00d18: 0ff0012b jal bfc004ac -bfc00d1c: 00000000 nop -bfc00d20: a3c20004 sb v0,4(s8) -bfc00d24: 83c30004 lb v1,4(s8) -bfc00d28: 2402000d li v0,13 -bfc00d2c: 10620005 beq v1,v0,bfc00d44 -bfc00d30: 00000000 nop -bfc00d34: 83c30004 lb v1,4(s8) -bfc00d38: 2402000a li v0,10 -bfc00d3c: 1462ffeb bne v1,v0,bfc00cec -bfc00d40: 00000000 nop -bfc00d44: 8fc20000 lw v0,0(s8) -bfc00d48: 03c0e821 move sp,s8 -bfc00d4c: 8fbf0014 lw ra,20(sp) -bfc00d50: 8fbe0010 lw s8,16(sp) -bfc00d54: 27bd0018 addiu sp,sp,24 -bfc00d58: 03e00008 jr ra -bfc00d5c: 00000000 nop - -bfc00d60 : -bfc00d60: 27bdfff0 addiu sp,sp,-16 -bfc00d64: afbe000c sw s8,12(sp) -bfc00d68: 03a0f021 move s8,sp -bfc00d6c: afc40000 sw a0,0(s8) -bfc00d70: 401a6000 mfc0 k0,$12 -bfc00d74: 3c1bffbf lui k1,0xffbf -bfc00d78: 377bffff ori k1,k1,0xffff -bfc00d7c: 035bd024 and k0,k0,k1 -bfc00d80: 409a6000 mtc0 k0,$12 -bfc00d84: 00800008 jr a0 -bfc00d88: 42000010 rfe -bfc00d8c: 03c0e821 move sp,s8 -bfc00d90: 8fbe000c lw s8,12(sp) -bfc00d94: 03e00008 jr ra -bfc00d98: 27bd0010 addiu sp,sp,16 - -bfc00d9c : -bfc00d9c: 27bdffd0 addiu sp,sp,-48 -bfc00da0: afbf002c sw ra,44(sp) -bfc00da4: afbe0028 sw s8,40(sp) -bfc00da8: 03a0f021 move s8,sp -bfc00dac: 3c02bfc0 lui v0,0xbfc0 -bfc00db0: 24421738 addiu v0,v0,5944 -bfc00db4: afc20008 sw v0,8(s8) -bfc00db8: 3c02bfc0 lui v0,0xbfc0 -bfc00dbc: 24421740 addiu v0,v0,5952 -bfc00dc0: afc2000c sw v0,12(s8) -bfc00dc4: 3c02bfc0 lui v0,0xbfc0 -bfc00dc8: 24421748 addiu v0,v0,5960 -bfc00dcc: afc20010 sw v0,16(s8) -bfc00dd0: 3c02bfc0 lui v0,0xbfc0 -bfc00dd4: 24421750 addiu v0,v0,5968 -bfc00dd8: afc20014 sw v0,20(s8) -bfc00ddc: 3c02bfc0 lui v0,0xbfc0 -bfc00de0: 24421758 addiu v0,v0,5976 -bfc00de4: afc20018 sw v0,24(s8) -bfc00de8: 3c02bfc0 lui v0,0xbfc0 -bfc00dec: 24421760 addiu v0,v0,5984 -bfc00df0: afc2001c sw v0,28(s8) -bfc00df4: 3c02bfc0 lui v0,0xbfc0 -bfc00df8: 2442176c addiu v0,v0,5996 -bfc00dfc: afc20020 sw v0,32(s8) -bfc00e00: 0ff0011b jal bfc0046c -bfc00e04: 00000000 nop -bfc00e08: afc20004 sw v0,4(s8) -bfc00e0c: 3c02bfc0 lui v0,0xbfc0 -bfc00e10: 24441774 addiu a0,v0,6004 -bfc00e14: 0ff0017e jal bfc005f8 -bfc00e18: 00000000 nop -bfc00e1c: 8fc40004 lw a0,4(s8) -bfc00e20: 0ff001d8 jal bfc00760 -bfc00e24: 00000000 nop -bfc00e28: 3c02bfc0 lui v0,0xbfc0 -bfc00e2c: 24441780 addiu a0,v0,6016 -bfc00e30: 0ff0017e jal bfc005f8 -bfc00e34: 00000000 nop -bfc00e38: 0ff00123 jal bfc0048c -bfc00e3c: 00000000 nop -bfc00e40: afc20004 sw v0,4(s8) -bfc00e44: 8fc20004 lw v0,4(s8) -bfc00e48: 00000000 nop -bfc00e4c: 00021203 sra v0,v0,0x8 -bfc00e50: 304200ff andi v0,v0,0xff -bfc00e54: afc20000 sw v0,0(s8) -bfc00e58: 3c02bfc0 lui v0,0xbfc0 -bfc00e5c: 24441784 addiu a0,v0,6020 -bfc00e60: 0ff0017e jal bfc005f8 -bfc00e64: 00000000 nop -bfc00e68: 8fc20000 lw v0,0(s8) -bfc00e6c: 00000000 nop -bfc00e70: 18400020 blez v0,bfc00ef4 -bfc00e74: 00000000 nop -bfc00e78: 8fc20000 lw v0,0(s8) -bfc00e7c: 00000000 nop -bfc00e80: 28420007 slti v0,v0,7 -bfc00e84: 1040001b beqz v0,bfc00ef4 -bfc00e88: 00000000 nop -bfc00e8c: 8fc20000 lw v0,0(s8) -bfc00e90: 00000000 nop -bfc00e94: 00021080 sll v0,v0,0x2 -bfc00e98: 03c21021 addu v0,s8,v0 -bfc00e9c: 8c420008 lw v0,8(v0) -bfc00ea0: 00000000 nop -bfc00ea4: 00402021 move a0,v0 -bfc00ea8: 0ff0017e jal bfc005f8 -bfc00eac: 00000000 nop -bfc00eb0: 3c02bfc0 lui v0,0xbfc0 -bfc00eb4: 24441790 addiu a0,v0,6032 -bfc00eb8: 0ff0017e jal bfc005f8 -bfc00ebc: 00000000 nop -bfc00ec0: 8fc20004 lw v0,4(s8) -bfc00ec4: 00000000 nop -bfc00ec8: 304200ff andi v0,v0,0xff -bfc00ecc: afc20000 sw v0,0(s8) -bfc00ed0: 8fc20000 lw v0,0(s8) -bfc00ed4: 00000000 nop -bfc00ed8: 00021600 sll v0,v0,0x18 -bfc00edc: 00021603 sra v0,v0,0x18 -bfc00ee0: 00402021 move a0,v0 -bfc00ee4: 0ff001a4 jal bfc00690 -bfc00ee8: 00000000 nop -bfc00eec: 0bf003c1 j bfc00f04 -bfc00ef0: 00000000 nop -bfc00ef4: 3c02bfc0 lui v0,0xbfc0 -bfc00ef8: 24441798 addiu a0,v0,6040 -bfc00efc: 0ff0017e jal bfc005f8 -bfc00f00: 00000000 nop -bfc00f04: 3c02bfc0 lui v0,0xbfc0 -bfc00f08: 24441780 addiu a0,v0,6016 -bfc00f0c: 0ff0017e jal bfc005f8 -bfc00f10: 00000000 nop -bfc00f14: 03c0e821 move sp,s8 -bfc00f18: 8fbf002c lw ra,44(sp) -bfc00f1c: 8fbe0028 lw s8,40(sp) -bfc00f20: 27bd0030 addiu sp,sp,48 -bfc00f24: 03e00008 jr ra -bfc00f28: 00000000 nop - -bfc00f2c
: -bfc00f2c: 27bdfea0 addiu sp,sp,-352 -bfc00f30: afbf015c sw ra,348(sp) -bfc00f34: afbe0158 sw s8,344(sp) -bfc00f38: 03a0f021 move s8,sp -bfc00f3c: afc40148 sw a0,328(s8) -bfc00f40: afc5014c sw a1,332(s8) -bfc00f44: 3c02a000 lui v0,0xa000 -bfc00f48: afc20024 sw v0,36(s8) -bfc00f4c: 3c02a400 lui v0,0xa400 -bfc00f50: afc20014 sw v0,20(s8) -bfc00f54: 3c02a002 lui v0,0xa002 -bfc00f58: afc20010 sw v0,16(s8) -bfc00f5c: 3c024000 lui v0,0x4000 -bfc00f60: afc2000c sw v0,12(s8) -bfc00f64: 3c024000 lui v0,0x4000 -bfc00f68: afc20008 sw v0,8(s8) -bfc00f6c: 3c024000 lui v0,0x4000 -bfc00f70: afc20004 sw v0,4(s8) -bfc00f74: 3c02bfc0 lui v0,0xbfc0 -bfc00f78: 244217a0 addiu v0,v0,6048 -bfc00f7c: afc20000 sw v0,0(s8) -bfc00f80: 8fc20024 lw v0,36(s8) -bfc00f84: 00000000 nop -bfc00f88: ac400000 sw zero,0(v0) -bfc00f8c: afc00028 sw zero,40(s8) -bfc00f90: 0ff00367 jal bfc00d9c -bfc00f94: 00000000 nop -bfc00f98: 8fc30014 lw v1,20(s8) -bfc00f9c: 3c021234 lui v0,0x1234 -bfc00fa0: 34425678 ori v0,v0,0x5678 -bfc00fa4: ac620000 sw v0,0(v1) -bfc00fa8: 8fc20014 lw v0,20(s8) -bfc00fac: 00000000 nop -bfc00fb0: 24430004 addiu v1,v0,4 -bfc00fb4: 3c02aaaa lui v0,0xaaaa -bfc00fb8: 34425555 ori v0,v0,0x5555 -bfc00fbc: ac620000 sw v0,0(v1) -bfc00fc0: 8fc20014 lw v0,20(s8) -bfc00fc4: 00000000 nop -bfc00fc8: 24430008 addiu v1,v0,8 -bfc00fcc: 3c02ffff lui v0,0xffff -bfc00fd0: ac620000 sw v0,0(v1) -bfc00fd4: 8fc20014 lw v0,20(s8) -bfc00fd8: 00000000 nop -bfc00fdc: 2443000c addiu v1,v0,12 -bfc00fe0: 3402ffff li v0,0xffff -bfc00fe4: ac620000 sw v0,0(v1) -bfc00fe8: 8fc20014 lw v0,20(s8) -bfc00fec: 00000000 nop -bfc00ff0: 8c430000 lw v1,0(v0) -bfc00ff4: 8fc20024 lw v0,36(s8) -bfc00ff8: 00000000 nop -bfc00ffc: ac430000 sw v1,0(v0) -bfc01000: 8fc20014 lw v0,20(s8) -bfc01004: 00000000 nop -bfc01008: 24420004 addiu v0,v0,4 -bfc0100c: 8c430000 lw v1,0(v0) -bfc01010: 8fc20024 lw v0,36(s8) -bfc01014: 00000000 nop -bfc01018: ac430000 sw v1,0(v0) -bfc0101c: 8fc20014 lw v0,20(s8) -bfc01020: 00000000 nop -bfc01024: 24420008 addiu v0,v0,8 -bfc01028: 8c430000 lw v1,0(v0) -bfc0102c: 8fc20024 lw v0,36(s8) -bfc01030: 00000000 nop -bfc01034: ac430000 sw v1,0(v0) -bfc01038: 8fc20014 lw v0,20(s8) -bfc0103c: 00000000 nop -bfc01040: 2442000c addiu v0,v0,12 -bfc01044: 8c430000 lw v1,0(v0) -bfc01048: 8fc20024 lw v0,36(s8) -bfc0104c: 00000000 nop -bfc01050: ac430000 sw v1,0(v0) -bfc01054: 8fc30010 lw v1,16(s8) -bfc01058: 3c021234 lui v0,0x1234 -bfc0105c: 34425678 ori v0,v0,0x5678 -bfc01060: ac620000 sw v0,0(v1) -bfc01064: 8fc20010 lw v0,16(s8) -bfc01068: 00000000 nop -bfc0106c: 24430004 addiu v1,v0,4 -bfc01070: 3c02aaaa lui v0,0xaaaa -bfc01074: 34425555 ori v0,v0,0x5555 -bfc01078: ac620000 sw v0,0(v1) -bfc0107c: 8fc20010 lw v0,16(s8) -bfc01080: 00000000 nop -bfc01084: 24430008 addiu v1,v0,8 -bfc01088: 3c02ffff lui v0,0xffff -bfc0108c: ac620000 sw v0,0(v1) -bfc01090: 8fc20010 lw v0,16(s8) -bfc01094: 00000000 nop -bfc01098: 2443000c addiu v1,v0,12 -bfc0109c: 3402ffff li v0,0xffff -bfc010a0: ac620000 sw v0,0(v1) -bfc010a4: 8fc20010 lw v0,16(s8) -bfc010a8: 00000000 nop -bfc010ac: 8c430000 lw v1,0(v0) -bfc010b0: 8fc20024 lw v0,36(s8) -bfc010b4: 00000000 nop -bfc010b8: ac430000 sw v1,0(v0) -bfc010bc: 8fc20010 lw v0,16(s8) -bfc010c0: 00000000 nop -bfc010c4: 24420004 addiu v0,v0,4 -bfc010c8: 8c430000 lw v1,0(v0) -bfc010cc: 8fc20024 lw v0,36(s8) -bfc010d0: 00000000 nop -bfc010d4: ac430000 sw v1,0(v0) -bfc010d8: 8fc20010 lw v0,16(s8) -bfc010dc: 00000000 nop -bfc010e0: 24420008 addiu v0,v0,8 -bfc010e4: 8c430000 lw v1,0(v0) -bfc010e8: 8fc20024 lw v0,36(s8) -bfc010ec: 00000000 nop -bfc010f0: ac430000 sw v1,0(v0) -bfc010f4: 8fc20010 lw v0,16(s8) -bfc010f8: 00000000 nop -bfc010fc: 2442000c addiu v0,v0,12 -bfc01100: 8c430000 lw v1,0(v0) -bfc01104: 8fc20024 lw v0,36(s8) -bfc01108: 00000000 nop -bfc0110c: ac430000 sw v1,0(v0) -bfc01110: 3c024000 lui v0,0x4000 -bfc01114: afc20018 sw v0,24(s8) -bfc01118: afc0001c sw zero,28(s8) -bfc0111c: afc0002c sw zero,44(s8) -bfc01120: 0bf0045c j bfc01170 -bfc01124: 00000000 nop -bfc01128: 8fc2001c lw v0,28(s8) -bfc0112c: 00000000 nop -bfc01130: 8c430000 lw v1,0(v0) -bfc01134: 8fc20018 lw v0,24(s8) -bfc01138: 00000000 nop -bfc0113c: ac430000 sw v1,0(v0) -bfc01140: 8fc20018 lw v0,24(s8) -bfc01144: 00000000 nop -bfc01148: 24420004 addiu v0,v0,4 -bfc0114c: afc20018 sw v0,24(s8) -bfc01150: 8fc2001c lw v0,28(s8) -bfc01154: 00000000 nop -bfc01158: 24420004 addiu v0,v0,4 -bfc0115c: afc2001c sw v0,28(s8) -bfc01160: 8fc2002c lw v0,44(s8) -bfc01164: 00000000 nop -bfc01168: 24420004 addiu v0,v0,4 -bfc0116c: afc2002c sw v0,44(s8) -bfc01170: 8fc2002c lw v0,44(s8) -bfc01174: 00000000 nop -bfc01178: 28421c00 slti v0,v0,7168 -bfc0117c: 1440ffea bnez v0,bfc01128 -bfc01180: 00000000 nop -bfc01184: 3c044000 lui a0,0x4000 -bfc01188: 0ff00358 jal bfc00d60 -bfc0118c: 00000000 nop -bfc01190: 3c02bfc0 lui v0,0xbfc0 -bfc01194: 244417ac addiu a0,v0,6060 -bfc01198: 0ff0017e jal bfc005f8 -bfc0119c: 00000000 nop -bfc011a0: 3c02bfc0 lui v0,0xbfc0 -bfc011a4: 244417c0 addiu a0,v0,6080 -bfc011a8: 0ff0017e jal bfc005f8 -bfc011ac: 00000000 nop -bfc011b0: afc0002c sw zero,44(s8) -bfc011b4: 0bf0047b j bfc011ec -bfc011b8: 00000000 nop -bfc011bc: 8fc3002c lw v1,44(s8) -bfc011c0: 8fc2000c lw v0,12(s8) -bfc011c4: 00000000 nop -bfc011c8: 00431821 addu v1,v0,v1 -bfc011cc: 8fc2002c lw v0,44(s8) -bfc011d0: 00000000 nop -bfc011d4: 304200ff andi v0,v0,0xff -bfc011d8: a0620000 sb v0,0(v1) -bfc011dc: 8fc2002c lw v0,44(s8) -bfc011e0: 00000000 nop -bfc011e4: 24420001 addiu v0,v0,1 -bfc011e8: afc2002c sw v0,44(s8) -bfc011ec: 8fc2002c lw v0,44(s8) -bfc011f0: 3c030040 lui v1,0x40 -bfc011f4: 0043102a slt v0,v0,v1 -bfc011f8: 1440fff0 bnez v0,bfc011bc -bfc011fc: 00000000 nop -bfc01200: 3c02bfc0 lui v0,0xbfc0 -bfc01204: 244417d8 addiu a0,v0,6104 -bfc01208: 0ff0017e jal bfc005f8 -bfc0120c: 00000000 nop -bfc01210: 3c02bfc0 lui v0,0xbfc0 -bfc01214: 244417e0 addiu a0,v0,6112 -bfc01218: 0ff0017e jal bfc005f8 -bfc0121c: 00000000 nop -bfc01220: 3c02003f lui v0,0x3f -bfc01224: 3442ffff ori v0,v0,0xffff -bfc01228: afc2002c sw v0,44(s8) -bfc0122c: 0bf0049b j bfc0126c -bfc01230: 00000000 nop -bfc01234: 8fc3002c lw v1,44(s8) -bfc01238: 8fc2000c lw v0,12(s8) -bfc0123c: 00000000 nop -bfc01240: 00431021 addu v0,v0,v1 -bfc01244: 90430000 lbu v1,0(v0) -bfc01248: 8fc2002c lw v0,44(s8) -bfc0124c: 00000000 nop -bfc01250: 304200ff andi v0,v0,0xff -bfc01254: 14620009 bne v1,v0,bfc0127c -bfc01258: 00000000 nop -bfc0125c: 8fc2002c lw v0,44(s8) -bfc01260: 00000000 nop -bfc01264: 2442ffff addiu v0,v0,-1 -bfc01268: afc2002c sw v0,44(s8) -bfc0126c: 8fc2002c lw v0,44(s8) -bfc01270: 00000000 nop -bfc01274: 0441ffef bgez v0,bfc01234 -bfc01278: 00000000 nop -bfc0127c: 8fc2002c lw v0,44(s8) -bfc01280: 00000000 nop -bfc01284: 24420001 addiu v0,v0,1 -bfc01288: afc2002c sw v0,44(s8) -bfc0128c: 8fc2002c lw v0,44(s8) -bfc01290: 00000000 nop -bfc01294: 10400007 beqz v0,bfc012b4 -bfc01298: 00000000 nop -bfc0129c: 3c02bfc0 lui v0,0xbfc0 -bfc012a0: 244417fc addiu a0,v0,6140 -bfc012a4: 0ff0017e jal bfc005f8 -bfc012a8: 00000000 nop -bfc012ac: 0bf004b1 j bfc012c4 -bfc012b0: 00000000 nop -bfc012b4: 3c02bfc0 lui v0,0xbfc0 -bfc012b8: 24441808 addiu a0,v0,6152 -bfc012bc: 0ff0017e jal bfc005f8 -bfc012c0: 00000000 nop -bfc012c4: 3c02bfc0 lui v0,0xbfc0 -bfc012c8: 24441814 addiu a0,v0,6164 -bfc012cc: 0ff0017e jal bfc005f8 -bfc012d0: 00000000 nop -bfc012d4: afc0002c sw zero,44(s8) -bfc012d8: 0bf004c6 j bfc01318 -bfc012dc: 00000000 nop -bfc012e0: 8fc2002c lw v0,44(s8) -bfc012e4: 00000000 nop -bfc012e8: 00021840 sll v1,v0,0x1 -bfc012ec: 8fc20008 lw v0,8(s8) -bfc012f0: 00000000 nop -bfc012f4: 00431821 addu v1,v0,v1 -bfc012f8: 8fc2002c lw v0,44(s8) -bfc012fc: 00000000 nop -bfc01300: 3042ffff andi v0,v0,0xffff -bfc01304: a4620000 sh v0,0(v1) -bfc01308: 8fc2002c lw v0,44(s8) -bfc0130c: 00000000 nop -bfc01310: 24420001 addiu v0,v0,1 -bfc01314: afc2002c sw v0,44(s8) -bfc01318: 8fc2002c lw v0,44(s8) -bfc0131c: 3c030020 lui v1,0x20 -bfc01320: 0043102a slt v0,v0,v1 -bfc01324: 1440ffee bnez v0,bfc012e0 -bfc01328: 00000000 nop -bfc0132c: 3c02bfc0 lui v0,0xbfc0 -bfc01330: 244417d8 addiu a0,v0,6104 -bfc01334: 0ff0017e jal bfc005f8 -bfc01338: 00000000 nop -bfc0133c: 3c02bfc0 lui v0,0xbfc0 -bfc01340: 24441830 addiu a0,v0,6192 -bfc01344: 0ff0017e jal bfc005f8 -bfc01348: 00000000 nop -bfc0134c: 3c02001f lui v0,0x1f -bfc01350: 3442ffff ori v0,v0,0xffff -bfc01354: afc2002c sw v0,44(s8) -bfc01358: 0bf004e8 j bfc013a0 -bfc0135c: 00000000 nop -bfc01360: 8fc2002c lw v0,44(s8) -bfc01364: 00000000 nop -bfc01368: 00021840 sll v1,v0,0x1 -bfc0136c: 8fc20008 lw v0,8(s8) -bfc01370: 00000000 nop -bfc01374: 00431021 addu v0,v0,v1 -bfc01378: 94430000 lhu v1,0(v0) -bfc0137c: 8fc2002c lw v0,44(s8) -bfc01380: 00000000 nop -bfc01384: 3042ffff andi v0,v0,0xffff -bfc01388: 14620009 bne v1,v0,bfc013b0 -bfc0138c: 00000000 nop -bfc01390: 8fc2002c lw v0,44(s8) -bfc01394: 00000000 nop -bfc01398: 2442ffff addiu v0,v0,-1 -bfc0139c: afc2002c sw v0,44(s8) -bfc013a0: 8fc2002c lw v0,44(s8) -bfc013a4: 00000000 nop -bfc013a8: 0441ffed bgez v0,bfc01360 -bfc013ac: 00000000 nop -bfc013b0: 8fc2002c lw v0,44(s8) -bfc013b4: 00000000 nop -bfc013b8: 24420001 addiu v0,v0,1 -bfc013bc: afc2002c sw v0,44(s8) -bfc013c0: 8fc2002c lw v0,44(s8) -bfc013c4: 00000000 nop -bfc013c8: 10400007 beqz v0,bfc013e8 -bfc013cc: 00000000 nop -bfc013d0: 3c02bfc0 lui v0,0xbfc0 -bfc013d4: 244417fc addiu a0,v0,6140 -bfc013d8: 0ff0017e jal bfc005f8 -bfc013dc: 00000000 nop -bfc013e0: 0bf004fe j bfc013f8 -bfc013e4: 00000000 nop -bfc013e8: 3c02bfc0 lui v0,0xbfc0 -bfc013ec: 24441808 addiu a0,v0,6152 -bfc013f0: 0ff0017e jal bfc005f8 -bfc013f4: 00000000 nop -bfc013f8: 3c02bfc0 lui v0,0xbfc0 -bfc013fc: 2444184c addiu a0,v0,6220 -bfc01400: 0ff0017e jal bfc005f8 -bfc01404: 00000000 nop -bfc01408: afc0002c sw zero,44(s8) -bfc0140c: 0bf00512 j bfc01448 -bfc01410: 00000000 nop -bfc01414: 8fc2002c lw v0,44(s8) -bfc01418: 00000000 nop -bfc0141c: 00021880 sll v1,v0,0x2 -bfc01420: 8fc20004 lw v0,4(s8) -bfc01424: 00000000 nop -bfc01428: 00431821 addu v1,v0,v1 -bfc0142c: 8fc2002c lw v0,44(s8) -bfc01430: 00000000 nop -bfc01434: ac620000 sw v0,0(v1) -bfc01438: 8fc2002c lw v0,44(s8) -bfc0143c: 00000000 nop -bfc01440: 24420001 addiu v0,v0,1 -bfc01444: afc2002c sw v0,44(s8) -bfc01448: 8fc2002c lw v0,44(s8) -bfc0144c: 3c030010 lui v1,0x10 -bfc01450: 0043102a slt v0,v0,v1 -bfc01454: 1440ffef bnez v0,bfc01414 -bfc01458: 00000000 nop -bfc0145c: 3c02bfc0 lui v0,0xbfc0 -bfc01460: 244417d8 addiu a0,v0,6104 -bfc01464: 0ff0017e jal bfc005f8 -bfc01468: 00000000 nop -bfc0146c: 3c02bfc0 lui v0,0xbfc0 -bfc01470: 24441868 addiu a0,v0,6248 -bfc01474: 0ff0017e jal bfc005f8 -bfc01478: 00000000 nop -bfc0147c: 3c02000f lui v0,0xf -bfc01480: 3442ffff ori v0,v0,0xffff -bfc01484: afc2002c sw v0,44(s8) -bfc01488: 0bf00533 j bfc014cc -bfc0148c: 00000000 nop -bfc01490: 8fc2002c lw v0,44(s8) -bfc01494: 00000000 nop -bfc01498: 00021880 sll v1,v0,0x2 -bfc0149c: 8fc20004 lw v0,4(s8) -bfc014a0: 00000000 nop -bfc014a4: 00431021 addu v0,v0,v1 -bfc014a8: 8c430000 lw v1,0(v0) -bfc014ac: 8fc2002c lw v0,44(s8) -bfc014b0: 00000000 nop -bfc014b4: 14620009 bne v1,v0,bfc014dc -bfc014b8: 00000000 nop -bfc014bc: 8fc2002c lw v0,44(s8) -bfc014c0: 00000000 nop -bfc014c4: 2442ffff addiu v0,v0,-1 -bfc014c8: afc2002c sw v0,44(s8) -bfc014cc: 8fc2002c lw v0,44(s8) -bfc014d0: 00000000 nop -bfc014d4: 0441ffee bgez v0,bfc01490 -bfc014d8: 00000000 nop -bfc014dc: 8fc2002c lw v0,44(s8) -bfc014e0: 00000000 nop -bfc014e4: 24420001 addiu v0,v0,1 -bfc014e8: afc2002c sw v0,44(s8) -bfc014ec: 8fc2002c lw v0,44(s8) -bfc014f0: 00000000 nop -bfc014f4: 10400007 beqz v0,bfc01514 -bfc014f8: 00000000 nop -bfc014fc: 3c02bfc0 lui v0,0xbfc0 -bfc01500: 244417fc addiu a0,v0,6140 -bfc01504: 0ff0017e jal bfc005f8 -bfc01508: 00000000 nop -bfc0150c: 0bf00549 j bfc01524 -bfc01510: 00000000 nop -bfc01514: 3c02bfc0 lui v0,0xbfc0 -bfc01518: 24441808 addiu a0,v0,6152 -bfc0151c: 0ff0017e jal bfc005f8 -bfc01520: 00000000 nop -bfc01524: afc0002c sw zero,44(s8) -bfc01528: 0bf00557 j bfc0155c -bfc0152c: 00000000 nop -bfc01530: 8fc2002c lw v0,44(s8) -bfc01534: 00000000 nop -bfc01538: 00021880 sll v1,v0,0x2 -bfc0153c: 8fc20004 lw v0,4(s8) -bfc01540: 00000000 nop -bfc01544: 00431021 addu v0,v0,v1 -bfc01548: ac400000 sw zero,0(v0) -bfc0154c: 8fc2002c lw v0,44(s8) -bfc01550: 00000000 nop -bfc01554: 24420001 addiu v0,v0,1 -bfc01558: afc2002c sw v0,44(s8) -bfc0155c: 8fc2002c lw v0,44(s8) -bfc01560: 3c030010 lui v1,0x10 -bfc01564: 0043102a slt v0,v0,v1 -bfc01568: 1440fff1 bnez v0,bfc01530 -bfc0156c: 00000000 nop -bfc01570: 8fc40000 lw a0,0(s8) -bfc01574: 0ff0017e jal bfc005f8 -bfc01578: 00000000 nop -bfc0157c: 27c20034 addiu v0,s8,52 -bfc01580: 00402021 move a0,v0 -bfc01584: 0ff00328 jal bfc00ca0 -bfc01588: 00000000 nop -bfc0158c: afc20030 sw v0,48(s8) -bfc01590: 27c20134 addiu v0,s8,308 -bfc01594: 27c30034 addiu v1,s8,52 -bfc01598: 00402021 move a0,v0 -bfc0159c: 00602821 move a1,v1 -bfc015a0: 8fc60030 lw a2,48(s8) -bfc015a4: 0ff00234 jal bfc008d0 -bfc015a8: 00000000 nop -bfc015ac: afc20030 sw v0,48(s8) -bfc015b0: 8fc20024 lw v0,36(s8) -bfc015b4: 00000000 nop -bfc015b8: ac400000 sw zero,0(v0) -bfc015bc: 8fc20030 lw v0,48(s8) -bfc015c0: 00000000 nop -bfc015c4: afc20150 sw v0,336(s8) -bfc015c8: 24020002 li v0,2 -bfc015cc: 8fc30150 lw v1,336(s8) -bfc015d0: 00000000 nop -bfc015d4: 10620008 beq v1,v0,bfc015f8 -bfc015d8: 00000000 nop -bfc015dc: 24020004 li v0,4 -bfc015e0: 8fc30150 lw v1,336(s8) -bfc015e4: 00000000 nop -bfc015e8: 1062002f beq v1,v0,bfc016a8 -bfc015ec: 00000000 nop -bfc015f0: 0bf005c5 j bfc01714 -bfc015f4: 00000000 nop -bfc015f8: 8fc30134 lw v1,308(s8) -bfc015fc: 8fc20138 lw v0,312(s8) -bfc01600: 00000000 nop -bfc01604: 00621821 addu v1,v1,v0 -bfc01608: 8fc20028 lw v0,40(s8) -bfc0160c: 00000000 nop -bfc01610: 0043102b sltu v0,v0,v1 -bfc01614: 10400006 beqz v0,bfc01630 -bfc01618: 00000000 nop -bfc0161c: 8fc20134 lw v0,308(s8) -bfc01620: 8fc30138 lw v1,312(s8) -bfc01624: 00000000 nop -bfc01628: 00431021 addu v0,v0,v1 -bfc0162c: afc20028 sw v0,40(s8) -bfc01630: 8fc20134 lw v0,308(s8) -bfc01634: 00000000 nop -bfc01638: afc20020 sw v0,32(s8) -bfc0163c: afc0002c sw zero,44(s8) -bfc01640: 0bf005a2 j bfc01688 -bfc01644: 00000000 nop -bfc01648: 8fc30140 lw v1,320(s8) -bfc0164c: 8fc2002c lw v0,44(s8) -bfc01650: 00000000 nop -bfc01654: 00621021 addu v0,v1,v0 -bfc01658: 90430000 lbu v1,0(v0) -bfc0165c: 8fc20020 lw v0,32(s8) -bfc01660: 00000000 nop -bfc01664: a0430000 sb v1,0(v0) -bfc01668: 8fc20020 lw v0,32(s8) -bfc0166c: 00000000 nop -bfc01670: 24420001 addiu v0,v0,1 -bfc01674: afc20020 sw v0,32(s8) -bfc01678: 8fc2002c lw v0,44(s8) -bfc0167c: 00000000 nop -bfc01680: 24420001 addiu v0,v0,1 -bfc01684: afc2002c sw v0,44(s8) -bfc01688: 8fc2002c lw v0,44(s8) -bfc0168c: 8fc30138 lw v1,312(s8) -bfc01690: 00000000 nop -bfc01694: 0043102b sltu v0,v0,v1 -bfc01698: 1440ffeb bnez v0,bfc01648 -bfc0169c: 00000000 nop -bfc016a0: 0bf005c5 j bfc01714 -bfc016a4: 00000000 nop -bfc016a8: 8fc30024 lw v1,36(s8) -bfc016ac: 24020001 li v0,1 -bfc016b0: ac620000 sw v0,0(v1) -bfc016b4: 8fc20134 lw v0,308(s8) -bfc016b8: 00000000 nop -bfc016bc: 00402021 move a0,v0 -bfc016c0: 0ff001d8 jal bfc00760 -bfc016c4: 00000000 nop -bfc016c8: 3c02bfc0 lui v0,0xbfc0 -bfc016cc: 24441884 addiu a0,v0,6276 -bfc016d0: 0ff0017e jal bfc005f8 -bfc016d4: 00000000 nop -bfc016d8: 8fc20028 lw v0,40(s8) -bfc016dc: 00000000 nop -bfc016e0: 2442fffc addiu v0,v0,-4 -bfc016e4: 00402021 move a0,v0 -bfc016e8: 0ff001d8 jal bfc00760 -bfc016ec: 00000000 nop -bfc016f0: 3c02bfc0 lui v0,0xbfc0 -bfc016f4: 2444188c addiu a0,v0,6284 -bfc016f8: 0ff0017e jal bfc005f8 -bfc016fc: 00000000 nop -bfc01700: 8fc20134 lw v0,308(s8) -bfc01704: 00000000 nop -bfc01708: 00402021 move a0,v0 -bfc0170c: 0ff00358 jal bfc00d60 -bfc01710: 00000000 nop -bfc01714: 8fc20030 lw v0,48(s8) -bfc01718: 00000000 nop -bfc0171c: 1440ff97 bnez v0,bfc0157c -bfc01720: 00000000 nop -bfc01724: 8fc30024 lw v1,36(s8) -bfc01728: 3c024000 lui v0,0x4000 -bfc0172c: ac620000 sw v0,0(v1) -bfc01730: 0bf0055c j bfc01570 -bfc01734: 00000000 nop diff --git a/projects/mips_sys/src/mips_pipeline.vhd b/projects/mips_sys/src/mips_pipeline.vhd deleted file mode 100644 index ab2d777..0000000 --- a/projects/mips_sys/src/mips_pipeline.vhd +++ /dev/null @@ -1,886 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The pipeline --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -library work; -use work.mips_types.all; -use work.mips_instr.all; - -entity pipeline is - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - halt : in STD_LOGIC; - int : in unsigned(5 downto 0); - imem_rdy : in STD_LOGIC; - imem_en : out STD_LOGIC; - imem_addr : out word_t; - imem_data : in word_t; - dmem_rdy : in STD_LOGIC; - dmem_en : out STD_LOGIC; - dmem_re : out STD_LOGIC; - dmem_we : out unsigned(3 downto 0); - dmem_addr : out word_t; - dmem_din : in word_t; - dmem_dout : out word_t - ); -end pipeline; - -architecture Behavioral of pipeline is - --------------------------------------------------------------------------- - COMPONENT reg_dual is - Generic - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port - ( - clk_w : in STD_LOGIC; - en : in STD_LOGIC; - we : in STD_LOGIC; - wptr : in unsigned (addr_width-1 downto 0); - din : in unsigned (data_width-1 downto 0); - rptr_a : in unsigned (addr_width-1 downto 0); - rptr_b : in unsigned (addr_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); - END COMPONENT; - --------------------------------------------------------------------------- - COMPONENT idecode_rom is - Port - ( - nop : in std_logic; - inst_in : in word_t; - ctrl_out : out ctrl_lines_t - ); - END COMPONENT; - --------------------------------------------------------------------------- - COMPONENT shifter is - Generic - ( - data_width : integer - ); - Port - ( - shift_ctrl : in shift_ctrl_t; - din : in unsigned (data_width-1 downto 0); - dout : out unsigned (data_width-1 downto 0) - ); - END COMPONENT; - --------------------------------------------------------------------------- - COMPONENT alu is - Generic - ( - data_width : integer - ); - Port - ( - op1_in : in unsigned (data_width-1 downto 0); - op2_in : in unsigned (data_width-1 downto 0); - op2_shifted : in unsigned (data_width-1 downto 0); - ctrl : in alu_ctrl_t; - result : out unsigned (data_width-1 downto 0); - flags : out alu_flags_t - ); - END COMPONENT; - --------------------------------------------------------------------------- - COMPONENT bcu is - Generic - ( - data_width : integer - ); - Port - ( - op1_in : in unsigned (data_width-1 downto 0); - op2_in : in unsigned (data_width-1 downto 0); - flags : out bcu_flags_t - ); - END COMPONENT; - --------------------------------------------------------------------------- - COMPONENT cop is - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - IR_valid : in STD_LOGIC; - IR : in word_t; - events : in event_t; - ctrl_in : in cop_ctrl_in_t; - ctrl_out : out cop_ctrl_out_t; - din : in word_t; - dout : out word_t - ); - END COMPONENT; - --------------------------------------------------------------------------- - COMPONENT muldiv is - Port - ( - rst : in std_logic; - clk : in std_logic; - hilo_we : in std_logic; - din_hi : in word_t; - din_lo : in word_t; - mul_divn : in std_logic; - start : in std_logic; - s_un : in std_logic; - hilo_sel : in std_logic; - busy : out std_logic; - dout : out word_t - ); - END COMPONENT; - --------------------------------------------------------------------------- - constant RESET_VECTOR : word_t := X"BFC00000"; - - signal ID_stage : ID_t; - signal EX_stage : EX_t; - signal MEM_stage : MEM_t; - signal WB_stage : WB_t; - signal clk_2, clk_1 : STD_LOGIC; - signal hdu : hdu_t; - signal cpu_rst : STD_LOGIC; - signal reg_a : word_t; - signal reg_b : word_t; - signal ctrl_lines : ctrl_lines_t; - signal ID_act : STD_LOGIC; - signal EX_act : STD_LOGIC; - signal MEM_act : STD_LOGIC; - signal WB_act : STD_LOGIC; - signal ID_nop : STD_LOGIC; - signal EX_nop : STD_LOGIC; - signal MEM_nop : STD_LOGIC; - signal WB_nop : STD_LOGIC; - signal IF_stall : STD_LOGIC; - signal EX_stall : STD_LOGIC; - signal MEM_stall : STD_LOGIC; - signal WB_stall : STD_LOGIC; - signal cpu_run : STD_LOGIC; - signal branch_ce : STD_LOGIC; - signal run_en : STD_LOGIC; - signal mul_dep : STD_LOGIC; - signal imem_dep : STD_LOGIC; - signal dmem_dep : STD_LOGIC; - signal cop_en : STD_LOGIC; - signal cop_ctrl : cop_ctrl_in_t; - signal cop_din : word_t; - signal cop_dout : word_t; - signal alu_result : word_t; - signal mul_result : word_t; - signal mul_busy : STD_LOGIC; - signal events : event_t; - signal bcu_op_a : word_t; - signal bcu_op_b : word_t; - signal bcu_flags : bcu_flags_t; - - attribute ram_style : string; - - attribute ram_style of reg_a: signal is "distributed"; - attribute ram_style of reg_b: signal is "distributed"; - - signal pc : pc_t; - --------------------------------------------------------------------------- -begin - - clk_1 <= clk; - clk_2 <= not clk; - cpu_run <= not halt and run_en; - - events.Int <= int; - events.illegal <= EX_stage.ctrl.exc_illegal; - events.break <= EX_stage.ctrl.exc_break; - events.syscall <= EX_stage.ctrl.exc_syscall; - - -- Stall Detection Unit --------------------------------------------------- - imem_en <= run_en and (not (ID_stage.cop_stat.exc_strobe or mul_dep) or ID_stage.cop_stat.ec) and not dmem_dep; - - ID_nop <= cpu_rst or imem_dep; - EX_nop <= cpu_rst or EX_stage.cop_stat.exc_strobe or mul_dep; - MEM_nop <= cpu_rst or EX_stage.cop_stat.exc_strobe; - WB_nop <= cpu_rst or EX_stage.cop_stat.exc_strobe or dmem_dep; - - IF_stall <= not cpu_run or mul_dep or ID_stage.cop_stat.ec or imem_dep or dmem_dep; - EX_stall <= not cpu_run or dmem_dep; - MEM_stall <= not cpu_run or dmem_dep; - WB_stall <= not cpu_run; - - mul_dep <= ID_stage.ctrl.mul_access and (EX_stage.ctrl.mul_start or mul_busy); - imem_dep <= not imem_rdy; - dmem_dep <= not dmem_rdy and MEM_stage.ctrl.dmem_en; - --------------------------------------------------------------------------- - - events.inst_load_err <= '1' when EX_stage.epc(1 downto 0) /= "00" else '0'; - events.inst_priv_addr <= EX_stage.epc(word_t'left); - - cop_en <= not ID_nop; - --------------------------------------------------------------------------- --- Muldiv --------------------------------------------------------------------------- -inst_muldiv: muldiv - PORT MAP - ( - rst => cpu_rst, - clk => clk, - hilo_we => EX_stage.ctrl.mul_hilo_we, - din_hi => EX_stage.reg_a, - din_lo => EX_stage.reg_b, - mul_divn => EX_stage.ctrl.mul_mul_divn, - start => EX_stage.ctrl.mul_start, - s_un => EX_stage.ctrl.mul_s_un, - hilo_sel => EX_stage.ctrl.mul_hilo_sel, - busy => mul_busy, - dout => mul_result - ); - --------------------------------------------------------------------------- --- Coprocessor --------------------------------------------------------------------------- -inst_cop: cop - PORT MAP - ( - rst => cpu_rst, - clk => clk, - ce => cop_en, - events => events, - IR_valid => ID_stage.ctrl.cop_instr_en, - IR => ID_stage.IR, - ctrl_in => cop_ctrl, - ctrl_out => ID_stage.cop_stat, - dout => cop_dout, - din => cop_din - ); - - cop_ctrl.bd_ex <= EX_stage.ctrl.branch; - cop_ctrl.bd_mem <= MEM_stage.ctrl.branch; - cop_ctrl.bd_wb <= WB_stage.ctrl.branch; - cop_ctrl.epc_id <= ID_stage.epc; - cop_ctrl.epc_ex <= EX_stage.epc; - cop_ctrl.epc_mem <= MEM_stage.epc; - cop_ctrl.epc_wb <= WB_stage.epc; - cop_ctrl.dmem_addr <= EX_stage.va; - --------------------------------------------------------------------------- --- IF stage --------------------------------------------------------------------------- - imem_addr <= pc.curr; - -proc_stage_pc: - process(pc, rst, IF_stall) - begin - if rst = '1' then - pc.curr <= RESET_VECTOR after 2 ns; - elsif IF_stall = '0' then - if pc.is_branch then - pc.curr <= pc.pc_branch after 2 ns; - else - pc.curr <= pc.nxt after 2 ns; - end if; - end if; - end process; - -proc_stage_pc_branch: - process(clk_1) - begin - if rising_edge(clk_1) then - if IF_stall = '0' then - pc.pc_branch <= pc.curr + ID_stage.bimm18; - end if; - end if; - end process; - -proc_stage_pc_next: - process(clk_1) - begin - if rising_edge(clk_1) then - branch_ce <= '0'; - if rst = '1' then - pc.nxt <= RESET_VECTOR; - pc.last <= RESET_VECTOR; - elsif ID_stage.cop_stat.exc_strobe = '1' then - pc.nxt <= ID_stage.cop_stat.exc_vec; - elsif IF_stall = '0' then - branch_ce <= '1'; - pc.last <= pc.curr; - if ID_stage.ctrl.jump = '1' then - pc.nxt <= ID_stage.jimm32; - elsif ID_stage.ctrl.jump_long = '1' then - pc.nxt <= ID_stage.reg_a; - else - pc.nxt <= pc.curr + 4; - end if; - end if; - end if; - end process; - -proc_stage_branch: - process(clk_2) - begin - if rising_edge(clk_2) and branch_ce = '1' then - pc.is_branch <= false; - if EX_stage.ctrl.branch = '1' then - - case EX_stage.ctrl.bc_src is - - when bc_eq_ne => - if (EX_stage.ctrl.bc_not xor bcu_flags.eq) = '1' then - pc.is_branch <= true; - end if; - - when bc_lez_gtz => - if (EX_stage.ctrl.bc_not xor (bcu_flags.z or bcu_flags.ltz)) = '1' then - pc.is_branch <= true; - end if; - - when bc_ltz_gez => - if (EX_stage.ctrl.bc_not xor bcu_flags.ltz) = '1' then - pc.is_branch <= true; - end if; - - when others => null; - end case; - end if; - end if; - end process; - - process(rst, clk_1) - variable reset_delay : unsigned (5 downto 0); - begin - if rst = '1' then - reset_delay := (others => '1'); - cpu_rst <= '1'; - run_en <= '0'; - elsif rising_edge(clk_1) then - if reset_delay /= (5 downto 0 => '0') then - reset_delay := reset_delay - 1; - else - cpu_rst <= '0'; - end if; - if reset_delay(reset_delay'left) = '0' then - run_en <= '1'; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ID stage --------------------------------------------------------------------------- - ID_act <= not ID_nop; - ID_stage.IR <= imem_data; - ID_stage.pcn <= pc.curr; - ID_stage.op <= decode_op(ID_stage.IR) when ID_nop = '0' else NOP; - ID_stage.jimm32 <= extract_jimm32(ID_stage.IR, ID_stage.pcn); - ID_stage.bimm18 <= extract_bimm18(ID_stage.IR, ID_stage.pcn); - ID_stage.shamt <= extract_shamt(ID_stage.IR); - ID_stage.reg_a_rptr <= extract_rs(ID_stage.IR); - ID_stage.reg_b_rptr <= extract_rt(ID_stage.IR); - ID_stage.ctrl <= ctrl_lines; - ID_stage.reg_write <= ID_stage.ctrl.reg_write or ID_stage.cop_stat.reg_write; - ID_stage.epc <= pc.last; - -proc_stage_hdu: - process(ID_stage, EX_stage, MEM_stage, WB_stage) - variable read_a, read_b : boolean; - variable raw_a_EX, raw_a_MEM, raw_a_WB : boolean; - variable raw_b_EX, raw_b_MEM, raw_b_WB : boolean; - variable reg_ptr_a : reg_ptr_t; - variable reg_ptr_b : reg_ptr_t; - begin - - reg_ptr_a := ID_stage.reg_a_rptr; - reg_ptr_b := ID_stage.reg_b_rptr; - raw_a_EX := reg_ptr_a = EX_stage.reg_wptr and EX_stage.wreg_we = '1'; - raw_a_MEM := reg_ptr_a = MEM_stage.reg_wptr and MEM_stage.wreg_we = '1'; - raw_a_WB := reg_ptr_a = WB_stage.reg_wptr and WB_stage.wreg_we = '1'; - raw_b_EX := reg_ptr_b = EX_stage.reg_wptr and EX_stage.wreg_we = '1'; - raw_b_MEM := reg_ptr_b = MEM_stage.reg_wptr and MEM_stage.wreg_we = '1'; - raw_b_WB := reg_ptr_b = WB_stage.reg_wptr and WB_stage.wreg_we = '1'; - - hdu.alu_fwd_a_ex <= raw_a_EX after 1 ns; - hdu.alu_fwd_a_mem <= raw_a_MEM after 1 ns; - hdu.alu_fwd_a_wb <= raw_a_WB after 1 ns; - hdu.alu_fwd_b_ex <= raw_b_EX after 1 ns; - hdu.alu_fwd_b_mem <= raw_b_MEM after 1 ns; - hdu.alu_fwd_b_wb <= raw_b_WB after 1 ns; - - end process; - -proc_stage_fwd_a: - process(reg_a, hdu, EX_stage, MEM_stage, WB_stage) - variable data : word_t; - begin - data := reg_a; - if hdu.alu_fwd_a_ex then - data := EX_stage.result; - elsif hdu.alu_fwd_a_mem then - data := MEM_stage.data; - elsif hdu.alu_fwd_a_wb then - data := WB_stage.data; - end if; - ID_stage.reg_a <= data after 2 ns; - end process; - -proc_stage_fwd_b: - process(reg_b, hdu, EX_stage, MEM_stage, WB_stage) - variable data : word_t; - begin - data := reg_b; - if hdu.alu_fwd_b_ex then - data := EX_stage.result; - elsif hdu.alu_fwd_b_mem then - data := MEM_stage.data; - elsif hdu.alu_fwd_b_wb then - data := WB_stage.data; - end if; - ID_stage.reg_b <= data after 2 ns; - end process; - -proc_imm_mux: - process(ID_stage) - variable data : word_t; - begin - data := extract_uimm16(ID_stage.IR); - - case ID_stage.ctrl.imm_src is - - when src_imm32 => - data := extract_simm32(ID_stage.IR); - - when src_imm16 => - data := extract_uimm16(ID_stage.IR); - - when src_imm16_high => - data := ID_stage.IR(word_t'length/2-1 downto 0) & (word_t'length/2-1 downto 0 => '0'); - - when others => null; - - end case; - - ID_stage.imm <= data after 2 ns; - - end process; - --------------------------------------------------------------------------- -inst_idecode_rom: idecode_rom - PORT MAP - ( - nop => ID_nop, - inst_in => ID_stage.IR, - ctrl_out => ctrl_lines - ); - -inst_reg_dual: reg_dual - GENERIC MAP - ( - addr_width => reg_ptr_t'length, - data_width => word_t'length - ) - PORT MAP - ( - clk_w => clk_1, - we => WB_stage.wreg_we, - en => '1', - wptr => WB_stage.reg_wptr, - din => WB_stage.data, - rptr_a => ID_stage.reg_a_rptr, - rptr_b => ID_stage.reg_b_rptr, - dout_a => reg_a, - dout_b => reg_b - ); - --------------------------------------------------------------------------- --- EX stage --------------------------------------------------------------------------- - EX_stage.reg_a_rptr <= extract_rs(EX_stage.IR); - EX_stage.reg_b_rptr <= extract_rt(EX_stage.IR); - EX_stage.result <= mul_result when EX_stage.ctrl.mul_access = '1' else alu_result; - EX_act <= not (EX_nop or EX_stall); - -proc_stage_ID_EX_1: - process(clk_1) - begin - if rising_edge(clk_1) then - if cpu_rst = '1' then - EX_stage.epc <= (others => '0'); - elsif EX_stall = '0' then - EX_stage.op <= ID_stage.op; - if ID_nop = '0' then - EX_stage.IR <= ID_stage.IR; - else - EX_stage.IR <= (others => '0'); - end if; - EX_stage.ctrl <= ID_stage.ctrl; - EX_stage.reg_write <= ID_stage.reg_write; - EX_stage.pcn <= ID_stage.pcn; - EX_stage.epc <= ID_stage.epc; - EX_stage.cop_stat <= ID_stage.cop_stat; - if EX_nop = '1' then - EX_stage.op <= NOP; - EX_stage.IR <= (others => '0'); - EX_stage.ctrl <= ctrl_lines_default; - EX_stage.cop_stat.exc_strobe <= '0'; - EX_stage.reg_write <= '0'; - end if; - end if; - end if; - end process; - -proc_stage_EX_except: - process(EX_stage) - begin - events.data_load_err <= '0'; - events.data_store_err <= '0'; - events.alu_ovf <= '0'; - events.alu_uvf <= '0'; - if EX_stage.ctrl.alu_exc_en = '1' then - if EX_stage.alu_flags.ovf = '1' then - events.alu_ovf <= '1'; - end if; - if EX_stage.alu_flags.uvf = '1' then - events.alu_uvf <= '1'; - end if; - end if; - if EX_stage.ctrl.except_en = '1' then - if EX_stage.ctrl.word2_en = '1' then - if EX_stage.va(0) = '1' then - events.data_load_err <= EX_stage.ctrl.dmem_en and not EX_stage.ctrl.dmem_we; - events.data_store_err <= EX_stage.ctrl.dmem_en and EX_stage.ctrl.dmem_we; - end if; - elsif EX_stage.va(1 downto 0) /= "00" then - events.data_load_err <= EX_stage.ctrl.dmem_en and not EX_stage.ctrl.dmem_we; - events.data_store_err <= EX_stage.ctrl.dmem_en and EX_stage.ctrl.dmem_we; - end if; - end if; - end process; - -proc_stage_DMEM_ADDR: - process(clk_1) - variable vaddr : word_t; - begin - if rising_edge(clk_1) and EX_act = '1' then - vaddr := ID_stage.reg_a + extract_simm32(ID_stage.IR); - EX_stage.va <= vaddr; - if ID_stage.cop_stat.RE = '1' then - EX_stage.pa_off <= not vaddr(1 downto 0); - else - EX_stage.pa_off <= vaddr(1 downto 0); - end if; - end if; - end process; - dmem_we <= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_we, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.byte_en_byp) after 1 ns; - dmem_re <= not EX_stage.ctrl.dmem_we; - dmem_en <= EX_stage.ctrl.dmem_en and not(ID_stage.cop_stat.exc_strobe) after 1 ns; - dmem_dout <= store_shift(EX_stage.reg_b, EX_stage.pa_off, EX_stage.ctrl.shift_offset, EX_stage.ctrl.shift_byp) after 1ns; - dmem_addr <= EX_stage.va; - cop_din <= EX_stage.reg_b; - --------------------------------------------------------------------------- -proc_wptr_mux: - process(EX_stage) - variable opclass : opcode_t; - variable reg_wptr : reg_ptr_t; - begin - - opclass := extract_opc(EX_stage.IR); - case opclass is - when "000000" => - reg_wptr := extract_rd(EX_stage.IR); - when others => - reg_wptr := extract_rt(EX_stage.IR); - end case; - - EX_stage.wreg_we <= EX_stage.reg_write after 1 ns; - if reg_wptr = "00000" then - EX_stage.wreg_we <= '0' after 1 ns; - end if; - - EX_stage.reg_wptr <= reg_wptr after 1 ns; - case EX_stage.ctrl.wptr_srcsel is - when wptr_src_imm => - EX_stage.reg_wptr <= reg_wptr after 1 ns; - - when wptr_src_const => - EX_stage.reg_wptr <= to_unsigned(31, reg_ptr_t'length) after 1 ns; - EX_stage.wreg_we <= '1' after 1 ns; - - when others => null; - end case; - - end process; - --------------------------------------------------------------------------- -proc_stage_fwd_reg_a: - process(clk_1) - begin - if rising_edge(clk_1) then - if EX_act = '1' then - EX_stage.reg_a <= ID_stage.reg_a; - bcu_op_a <= ID_stage.reg_a; - end if; - end if; - end process; - -proc_stage_fwd_reg_b: - process(clk_1) - begin - if rising_edge(clk_1) then - if EX_act = '1' then - EX_stage.reg_b <= ID_stage.reg_b; - bcu_op_b <= ID_stage.reg_b; - end if; - end if; - end process; - -alu_op1_mux: - process(EX_stage) - variable data : word_t; - begin - - data := EX_stage.reg_a; - --- case EX_stage.ctrl.alu.op1_src is --- --- when alu_src_reg => --- data := EX_stage.reg_a; --- --- when alu_src_muldiv => --- data := mul_result; --- --- when others => null; --- --- end case; - - EX_stage.alu_op1 <= data; - - end process; - -alu_op2_mux: - process(clk_1) - variable data : word_t; - begin - - if rising_edge(clk_1) and EX_act = '1' then - data := ID_stage.reg_b; - - case ID_stage.ctrl.alu.op2_src is - - when alu_src_reg => - data := ID_stage.reg_b; - - when alu_src_imm => - data := ID_stage.imm; - - when others => null; - - end case; - - EX_stage.alu_op2 <= data; - end if; - - end process; - -shifter_sa_mux: - process(clk_1) - variable data : shamt_t; - variable data_inv : shamt_t; - - begin - if rising_edge(clk_1) and EX_act = '1' then - data := ID_stage.reg_a(4 downto 0); - case ID_stage.ctrl.shamt2_srcsel is - - when sa_src_reg => - data := ID_stage.reg_a(4 downto 0); - - when sa_src_imm => - data := ID_stage.shamt; - - when others => null; - - end case; - data_inv := not data + 1; - if ID_stage.ctrl.alu.shift_right = '0' then - EX_stage.shift_ctrl.shamt_rnd <= data_inv after 2 ns; - else - EX_stage.shift_ctrl.shamt_rnd <= data after 2 ns; - end if; - EX_stage.shift_ctrl.shamt_nrm <= data after 1 ns; - EX_stage.shift_ctrl.shift_right <= ID_stage.ctrl.alu.shift_right; - EX_stage.shift_ctrl.shift_arith <= ID_stage.ctrl.alu.shift_arith; - end if; - - end process; - --------------------------------------------------------------------------- -inst_shifter: shifter - GENERIC MAP - ( - data_width => word_t'length - ) - PORT MAP - ( - shift_ctrl => EX_stage.shift_ctrl, - din => EX_stage.reg_b, - dout => EX_stage.alu_op2_s - ); - -inst_alu: alu - GENERIC MAP - ( - data_width => word_t'length - ) - PORT MAP - ( - op1_in => EX_stage.alu_op1, - op2_in => EX_stage.alu_op2, - op2_shifted => EX_stage.alu_op2_s, - ctrl => EX_stage.ctrl.alu, - result => alu_result, - flags => EX_stage.alu_flags - ); - -inst_bcu: bcu - GENERIC MAP - ( - data_width => word_t'length - ) - PORT MAP - ( - op1_in => bcu_op_a, - op2_in => bcu_op_b, - flags => bcu_flags - ); - --------------------------------------------------------------------------- --- MEM stage --------------------------------------------------------------------------- - MEM_act <= not (MEM_nop or MEM_stall); - -proc_stage_MEM_n: - process(clk_1) - begin - if rising_edge(clk_1) then - if MEM_stall = '0' then - MEM_stage.op <= EX_stage.op; - MEM_stage.wreg_we <= EX_stage.wreg_we; - MEM_stage.ctrl <= EX_stage.ctrl; - MEM_stage.pcn <= EX_stage.pcn; - MEM_stage.epc <= EX_stage.epc; - MEM_stage.pa_off <= EX_stage.pa_off; - MEM_stage.reg_wptr <= EX_stage.reg_wptr; - MEM_stage.cop_stat <= EX_stage.cop_stat; - if EX_stage.ctrl.dmem_en = '1' then - MEM_stage.ex_result <= EX_stage.reg_b; - else - MEM_stage.ex_result <= EX_stage.result; - end if; - if MEM_nop = '1' then - MEM_stage.op <= NOP; - MEM_stage.wreg_we <= '0'; - MEM_stage.ctrl <= ctrl_lines_default; - -- MEM_stage.epc <= (others => '0'); - -- MEM_stage.pcn <= (others => '0'); - -- MEM_stage.pa_off <= (others => '0'); - -- MEM_stage.reg_wptr <= (others => '0'); - -- MEM_stage.ex_result <= (others => '0'); - end if; - end if; - end if; - end process; - -proc_stage_MEM_mux: - process(MEM_stage, dmem_din, cop_dout) - variable temp1 : word_t; - variable temp2 : word_t; - variable data : word_t; - variable be : unsigned(3 downto 0); - begin - data := MEM_stage.ex_result; - be := load_be(MEM_stage.pa_off, MEM_stage.ctrl.align_left, MEM_stage.ctrl.byte_en_byp); - if MEM_stage.cop_stat.cop_access = '1' then - data := cop_dout; - elsif MEM_stage.ctrl.reg_link = '1' then - data := MEM_stage.pcn + 4; - elsif MEM_stage.ctrl.dmem_en = '1' then - temp1 := load_shift(dmem_din, MEM_stage.pa_off, MEM_stage.ctrl.shift_offset, MEM_stage.ctrl.shift_byp); - temp2 := load_sign_ext(temp1, MEM_stage.ctrl.sign_ext_byp, MEM_stage.ctrl.load_signed, MEM_stage.ctrl.word2_en, MEM_stage.ctrl.word4_en); - if be(0) = '1' then - data(7 downto 0) := temp2(7 downto 0); - end if; - if be(1) = '1' then - data(15 downto 8) := temp2(15 downto 8); - end if; - if be(2) = '1' then - data(23 downto 16) := temp2(23 downto 16); - end if; - if be(3) = '1' then - data(31 downto 24) := temp2(31 downto 24); - end if; - end if; - MEM_stage.data <= data after 1 ns; - - end process; - --------------------------------------------------------------------------- --- WB stage --------------------------------------------------------------------------- - WB_act <= not (WB_nop or WB_stall); - -proc_stage_WB_p: - process(clk_1) - begin - if rising_edge(clk_1) then - if WB_stall = '0' then - WB_stage.op <= MEM_stage.op; - WB_stage.ctrl <= MEM_stage.ctrl; - WB_stage.wreg_we <= MEM_stage.wreg_we; - WB_stage.reg_wptr <= MEM_stage.reg_wptr; - WB_stage.data <= MEM_stage.data; - WB_stage.epc <= MEM_stage.epc; - if WB_nop = '1' then - WB_stage.op <= NOP; - WB_stage.ctrl <= ctrl_lines_default; - WB_stage.wreg_we <= '0'; - -- WB_stage.epc <= (others => '0'); - -- WB_stage.reg_wptr <= (others => '0'); - -- WB_stage.data <= (others => '0'); - end if; - end if; - end if; - end process; - --------------------------------------------------------------------------- -end Behavioral; diff --git a/projects/mips_sys/src/mips_sys_cfg.vhd b/projects/mips_sys/src/mips_sys_cfg.vhd deleted file mode 100644 index 6d279b3..0000000 --- a/projects/mips_sys/src/mips_sys_cfg.vhd +++ /dev/null @@ -1,19 +0,0 @@ -library IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -configuration cpu_irom of cpu_embedded is - for rtl - for inst_irom : irom - use entity work.irom(loadable); - end for; - end for; -end configuration cpu_irom; - -configuration system_xrom of systest is - for behavior - for inst_xrom : xrom - use entity work.xrom(loadable); - end for; - end for; -end configuration system_xrom;